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    /tg68kc/trunk
    from Rev 4 to Rev 5
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Rev 4 → Rev 5

/TG68K_ALU.vhd
34,46 → 34,45
DIV_Mode : integer; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
BarrelShifter :integer --0=>no, 1=>yes, 2=>switchable with CPU(1)
);
port(clk : in std_logic;
Reset : in std_logic;
clkena_lw : in std_logic:='1';
execOPC : in bit;
decodeOPC : in bit;
exe_condition : in std_logic;
exec_tas : in std_logic;
long_start : in bit;
non_aligned : in std_logic;
movem_presub : in bit;
set_stop : in bit;
Z_error : in bit;
rot_bits : in std_logic_vector(1 downto 0);
exec : in bit_vector(lastOpcBit downto 0);
OP1out : in std_logic_vector(31 downto 0);
OP2out : in std_logic_vector(31 downto 0);
reg_QA : in std_logic_vector(31 downto 0);
reg_QB : in std_logic_vector(31 downto 0);
opcode : in std_logic_vector(15 downto 0);
-- datatype : in std_logic_vector(1 downto 0);
exe_opcode : in std_logic_vector(15 downto 0);
exe_datatype : in std_logic_vector(1 downto 0);
sndOPC : in std_logic_vector(15 downto 0);
last_data_read : in std_logic_vector(15 downto 0);
data_read : in std_logic_vector(15 downto 0);
FlagsSR : in std_logic_vector(7 downto 0);
port(clk : in std_logic;
Reset : in std_logic;
clkena_lw : in std_logic:='1';
execOPC : in bit;
decodeOPC : in bit;
exe_condition : in std_logic;
exec_tas : in std_logic;
long_start : in bit;
non_aligned : in std_logic;
movem_presub : in bit;
set_stop : in bit;
Z_error : in bit;
rot_bits : in std_logic_vector(1 downto 0);
exec : in bit_vector(lastOpcBit downto 0);
OP1out : in std_logic_vector(31 downto 0);
OP2out : in std_logic_vector(31 downto 0);
reg_QA : in std_logic_vector(31 downto 0);
reg_QB : in std_logic_vector(31 downto 0);
opcode : in std_logic_vector(15 downto 0);
exe_opcode : in std_logic_vector(15 downto 0);
exe_datatype : in std_logic_vector(1 downto 0);
sndOPC : in std_logic_vector(15 downto 0);
last_data_read : in std_logic_vector(15 downto 0);
data_read : in std_logic_vector(15 downto 0);
FlagsSR : in std_logic_vector(7 downto 0);
micro_state : in micro_states;
bf_ext_in : in std_logic_vector(7 downto 0);
bf_ext_out : out std_logic_vector(7 downto 0);
bf_shift : in std_logic_vector(5 downto 0);
bf_width : in std_logic_vector(5 downto 0);
bf_ffo_offset : in std_logic_vector(31 downto 0);
bf_loffset : in std_logic_vector(4 downto 0);
set_V_Flag : buffer bit;
Flags : buffer std_logic_vector(7 downto 0);
c_out : buffer std_logic_vector(2 downto 0);
addsub_q : buffer std_logic_vector(31 downto 0);
ALUout : out std_logic_vector(31 downto 0)
);
bf_ext_in : in std_logic_vector(7 downto 0);
bf_ext_out : out std_logic_vector(7 downto 0);
bf_shift : in std_logic_vector(5 downto 0);
bf_width : in std_logic_vector(5 downto 0);
bf_ffo_offset : in std_logic_vector(31 downto 0);
bf_loffset : in std_logic_vector(4 downto 0);
 
set_V_Flag : buffer bit;
Flags : buffer std_logic_vector(7 downto 0);
c_out : buffer std_logic_vector(2 downto 0);
addsub_q : buffer std_logic_vector(31 downto 0);
ALUout : out std_logic_vector(31 downto 0)
);
end TG68K_ALU;
 
architecture logic of TG68K_ALU is
452,20 → 451,20
bf_fffo <= '0';
bf_d32 <= '0';
bf_s32 <= '0';
-- 000-bftst, 001-bfextu, 010-bfchg, 011-bfexts, 100-bfclr, 101-bfff0, 110-bfset, 111-bfins
-- 000-bftst, 001-bfextu, 010-bfchg, 011-bfexts, 100-bfclr, 101-bfff0, 110-bfset, 111-bfins
IF opcode(5 downto 4) ="00" THEN
bf_s32 <= '1';
END IF;
CASE opcode(10 downto 8) IS
WHEN "010" => bf_bchg <= '1'; --BFCHG
WHEN "011" => bf_exts <= '1'; --BFEXTS
-- WHEN "100" => insert <= (OTHERS =>'0'); --BFCLR
WHEN "101" => bf_fffo <= '1'; --BFFFO
WHEN "110" => bf_bset <= '1'; --BFSET
WHEN "010" => bf_bchg <= '1'; --BFCHG
WHEN "011" => bf_exts <= '1'; --BFEXTS
-- WHEN "100" => insert <= (OTHERS =>'0'); --BFCLR
WHEN "101" => bf_fffo <= '1'; --BFFFO
WHEN "110" => bf_bset <= '1'; --BFSET
WHEN "111" => bf_ins <= '1'; --BFINS
bf_s32 <= '1';
bf_s32 <= '1';
WHEN OTHERS => NULL;
END CASE;
-- IF
-- bf_ins <= '1';
-- END IF;
IF opcode(4 downto 3)="00" THEN
bf_d32 <= '1';
END IF;
/TG68KdotC_Kernel.vhd
80,46 → 80,45
 
entity TG68KdotC_Kernel is
generic(
SR_Read : integer:= 1; --0=>user, 1=>privileged, 2=>switchable with CPU(0)
VBR_Stackframe : integer:= 1; --0=>no, 1=>yes/extended, 2=>switchable with CPU(0)
extAddr_Mode : integer:= 1; --0=>no, 1=>yes, 2=>switchable with CPU(1)
MUL_Mode : integer := 1; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
MUL_Hardware : integer := 1; --0=>no, 1=>yes,
DIV_Mode : integer := 1; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
BarrelShifter : integer := 2; --0=>no, 1=>yes, 2=>switchable with CPU(1)
BitField : integer := 1 --0=>no, 1=>yes, 2=>switchable with CPU(1)
-- SR_Read : integer:= 0; --0=>user, 1=>privileged, 2=>switchable with CPU(0)
-- VBR_Stackframe : integer:= 0; --0=>no, 1=>yes/extended, 2=>switchable with CPU(0)
-- extAddr_Mode : integer:= 0; --0=>no, 1=>yes, 2=>switchable with CPU(1)
-- MUL_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
-- MUL_Hardware : integer := 1; --0=>no, 1=>yes,
-- DIV_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
-- BarrelShifter : integer := 0; --0=>no, 1=>yes, 2=>switchable with CPU(1)
-- BitField : integer := 0 --0=>no, 1=>yes, 2=>switchable with CPU(1)
SR_Read : integer:= 1; --0=>user, 1=>privileged, 2=>switchable with CPU(0)
VBR_Stackframe : integer:= 1; --0=>no, 1=>yes/extended, 2=>switchable with CPU(0)
extAddr_Mode : integer:= 1; --0=>no, 1=>yes, 2=>switchable with CPU(1)
MUL_Mode : integer := 1; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
MUL_Hardware : integer := 1; --0=>no, 1=>yes,
DIV_Mode : integer := 1; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
BarrelShifter : integer := 2; --0=>no, 1=>yes, 2=>switchable with CPU(1)
BitField : integer := 1 --0=>no, 1=>yes, 2=>switchable with CPU(1)
-- SR_Read : integer:= 0; --0=>user, 1=>privileged, 2=>switchable with CPU(0)
-- VBR_Stackframe : integer:= 0; --0=>no, 1=>yes/extended, 2=>switchable with CPU(0)
-- extAddr_Mode : integer:= 0; --0=>no, 1=>yes, 2=>switchable with CPU(1)
-- MUL_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
-- MUL_Hardware : integer := 1; --0=>no, 1=>yes,
-- DIV_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
-- BarrelShifter : integer := 0; --0=>no, 1=>yes, 2=>switchable with CPU(1)
-- BitField : integer := 0 --0=>no, 1=>yes, 2=>switchable with CPU(1)
);
port(clk : in std_logic;
nReset : in std_logic; --low active
clkena_in : in std_logic:='1';
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0):="111";
IPL_autovector : in std_logic:='0';
berr : in std_logic:='0'; -- only 68000 Stackpointer dummy
CPU : in std_logic_vector(1 downto 0):="00"; -- 00->68000 01->68010 11->68020(only some parts - yet)
addr_out : out std_logic_vector(31 downto 0);
data_write : out std_logic_vector(15 downto 0);
nWr : out std_logic;
nUDS, nLDS : out std_logic;
busstate : out std_logic_vector(1 downto 0); -- 00-> fetch code 10->read data 11->write data 01->no memaccess
nResetOut : out std_logic;
FC : out std_logic_vector(2 downto 0);
--
clr_berr : out std_logic;
-- for debug
skipFetch : out std_logic;
-- regin : buffer std_logic_vector(31 downto 0)
regin_out : out std_logic_vector(31 downto 0);
CACR_out : out std_logic_vector( 3 downto 0);
VBR_out : out std_logic_vector(31 downto 0)
port(clk : in std_logic;
nReset : in std_logic; --low active
clkena_in : in std_logic:='1';
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0):="111";
IPL_autovector : in std_logic:='0';
berr : in std_logic:='0'; -- only 68000 Stackpointer dummy
CPU : in std_logic_vector(1 downto 0):="00"; -- 00->68000 01->68010 11->68020(only some parts - yet)
addr_out : out std_logic_vector(31 downto 0);
data_write : out std_logic_vector(15 downto 0);
nWr : out std_logic;
nUDS : out std_logic;
nLDS : out std_logic;
busstate : out std_logic_vector(1 downto 0); -- 00-> fetch code 10->read data 11->write data 01->no memaccess
nResetOut : out std_logic;
FC : out std_logic_vector(2 downto 0);
clr_berr : out std_logic;
-- for debug
skipFetch : out std_logic;
regin_out : out std_logic_vector(31 downto 0);
CACR_out : out std_logic_vector( 3 downto 0);
VBR_out : out std_logic_vector(31 downto 0)
);
end TG68KdotC_Kernel;
 
339,58 → 338,57
DIV_Mode => DIV_Mode, --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
BarrelShifter => BarrelShifter --0=>no, 1=>yes, 2=>switchable with CPU(1)
)
port map(
clk => clk, --: in std_logic;
Reset => Reset, --: in std_logic;
clkena_lw => clkena_lw, --: in std_logic:='1';
execOPC => execOPC, --: in bit;
decodeOPC => decodeOPC, --: in bit;
exe_condition => exe_condition, --: in std_logic;
exec_tas => exec_tas, --: in std_logic;
long_start => long_start_alu, --: in bit;
non_aligned => non_aligned,
movem_presub => movem_presub, --: in bit;
set_stop => set_stop, --: in bit;
Z_error => Z_error, --: in bit;
port map(
clk => clk, --: in std_logic;
Reset => Reset, --: in std_logic;
clkena_lw => clkena_lw, --: in std_logic:='1';
execOPC => execOPC, --: in bit;
decodeOPC => decodeOPC, --: in bit;
exe_condition => exe_condition, --: in std_logic;
exec_tas => exec_tas, --: in std_logic;
long_start => long_start_alu, --: in bit;
non_aligned => non_aligned,
movem_presub => movem_presub, --: in bit;
set_stop => set_stop, --: in bit;
Z_error => Z_error, --: in bit;
 
rot_bits => rot_bits, --: in std_logic_vector(1 downto 0);
exec => exec, --: in bit_vector(lastOpcBit downto 0);
OP1out => OP1out, --: in std_logic_vector(31 downto 0);
OP2out => OP2out, --: in std_logic_vector(31 downto 0);
reg_QA => reg_QA, --: in std_logic_vector(31 downto 0);
reg_QB => reg_QB, --: in std_logic_vector(31 downto 0);
opcode => opcode, --: in std_logic_vector(15 downto 0);
-- datatype => datatype, --: in std_logic_vector(1 downto 0);
exe_opcode => exe_opcode, --: in std_logic_vector(15 downto 0);
exe_datatype => exe_datatype, --: in std_logic_vector(1 downto 0);
sndOPC => sndOPC, --: in std_logic_vector(15 downto 0);
last_data_read => last_data_read(15 downto 0), --: in std_logic_vector(31 downto 0);
data_read => data_read(15 downto 0), --: in std_logic_vector(31 downto 0);
FlagsSR => FlagsSR, --: in std_logic_vector(7 downto 0);
micro_state => micro_state, --: in micro_states;
bf_ext_in => bf_ext_in,
bf_ext_out => bf_ext_out,
bf_shift => alu_bf_shift,
bf_width => alu_width,
bf_ffo_offset => alu_bf_ffo_offset,
bf_loffset => alu_bf_loffset(4 downto 0),
set_V_Flag => set_V_Flag, --: buffer bit;
Flags => Flags, --: buffer std_logic_vector(8 downto 0);
c_out => c_out, --: buffer std_logic_vector(2 downto 0);
addsub_q => addsub_q, --: buffer std_logic_vector(31 downto 0);
ALUout => ALUout --: buffer std_logic_vector(31 downto 0)
);
long_start_alu <= to_bit(NOT memmaskmux(3));
process (memmaskmux)
begin
non_aligned <= '0';
if (memmaskmux(5 downto 4) = "01") or (memmaskmux(5 downto 4) = "10") then
non_aligned <= '1';
end if;
end process;
rot_bits => rot_bits, --: in std_logic_vector(1 downto 0);
exec => exec, --: in bit_vector(lastOpcBit downto 0);
OP1out => OP1out, --: in std_logic_vector(31 downto 0);
OP2out => OP2out, --: in std_logic_vector(31 downto 0);
reg_QA => reg_QA, --: in std_logic_vector(31 downto 0);
reg_QB => reg_QB, --: in std_logic_vector(31 downto 0);
opcode => opcode, --: in std_logic_vector(15 downto 0);
exe_opcode => exe_opcode, --: in std_logic_vector(15 downto 0);
exe_datatype => exe_datatype, --: in std_logic_vector(1 downto 0);
sndOPC => sndOPC, --: in std_logic_vector(15 downto 0);
last_data_read => last_data_read(15 downto 0), --: in std_logic_vector(31 downto 0);
data_read => data_read(15 downto 0), --: in std_logic_vector(31 downto 0);
FlagsSR => FlagsSR, --: in std_logic_vector(7 downto 0);
micro_state => micro_state, --: in micro_states;
bf_ext_in => bf_ext_in,
bf_ext_out => bf_ext_out,
bf_shift => alu_bf_shift,
bf_width => alu_width,
bf_ffo_offset => alu_bf_ffo_offset,
bf_loffset => alu_bf_loffset(4 downto 0),
 
set_V_Flag => set_V_Flag, --: buffer bit;
Flags => Flags, --: buffer std_logic_vector(8 downto 0);
c_out => c_out, --: buffer std_logic_vector(2 downto 0);
addsub_q => addsub_q, --: buffer std_logic_vector(31 downto 0);
ALUout => ALUout --: buffer std_logic_vector(31 downto 0)
);
 
long_start_alu <= to_bit(NOT memmaskmux(3));
 
process (memmaskmux)
begin
non_aligned <= '0';
if (memmaskmux(5 downto 4) = "01") or (memmaskmux(5 downto 4) = "10") then
non_aligned <= '1';
end if;
end process;
-----------------------------------------------------------------------------
-- Bus control
-----------------------------------------------------------------------------
401,9 → 399,9
busstate <= state;
nResetOut <= '0' WHEN exec(opcRESET)='1' ELSE '1';
-- does shift for byte access. note active low me
-- should produce address error on 68000
memmaskmux <= memmask when addr(0) = '1' else memmask(4 downto 0) & '1';
-- does shift for byte access. note active low me
-- should produce address error on 68000
memmaskmux <= memmask when addr(0) = '1' else memmask(4 downto 0) & '1';
nUDS <= memmaskmux(5);
nLDS <= memmaskmux(4);
clkena_lw <= '1' WHEN clkena_in='1' AND memmaskmux(3)='1' ELSE '0';
575,11 → 573,11
ELSIF set(briefext)='1' THEN
rf_dest_addr <= brief(15 downto 12);
ELSIF set(get_bfoffset)='1' THEN
IF opcode(15 downto 12)="1110" THEN
-- IF opcode(15 downto 12)="1110" THEN
rf_dest_addr <= '0'&sndOPC(8 downto 6);
ELSE
rf_dest_addr <= sndOPC(9 downto 6);
END IF;
-- ELSE
-- rf_dest_addr <= sndOPC(9 downto 6);
-- END IF;
ELSIF dest_2ndHbits='1' THEN
rf_dest_addr <= '0'&sndOPC(14 downto 12);
ELSIF set(write_reminder)='1' THEN
1177,7 → 1175,7
END IF;
IF rising_edge(clk) THEN
IF Reset = '1' THEN
IF Reset = '1' THEN
PCbase <= '1';
ELSIF clkena_lw='1' THEN
PCbase <= set_PCbase OR PCbase;

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