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URL https://opencores.org/ocsvn/tg68kc/tg68kc/trunk

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Rev 3 → Rev 4

/trunk/TG68K_ALU.vhd
1,9 → 1,9
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2018 Tobias Gubener --
-- Copyright (c) 2009-2019 Tobias Gubener --
-- Patches by MikeJ, Till Harbaum, Rok Krajnk, ... --
-- Subdesign fAMpIGA by TobiFlex --
-- Patches by MikeJ, Till Harbaum, Rok Krajnk, ... --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published --
29,10 → 29,10
 
entity TG68K_ALU is
generic(
MUL_Mode : integer; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
MUL_Hardware : integer; --0=>no, 1=>yes,
DIV_Mode : integer; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
BarrelShifter :integer --0=>no, 1=>yes, 2=>switchable with CPU(1)
MUL_Mode : integer; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
MUL_Hardware : integer; --0=>no, 1=>yes,
DIV_Mode : integer; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
BarrelShifter :integer --0=>no, 1=>yes, 2=>switchable with CPU(1)
);
port(clk : in std_logic;
Reset : in std_logic;
444,7 → 444,7
shifted_bitmask, bf_loffset, bitmaskmux0, bitmaskmux1, bitmaskmux2, bitmaskmux3, bf_width)
BEGIN
IF rising_edge(clk) THEN
IF clkena_lw = '1' THEN
IF clkena_lw = '1' THEN
bf_bset <= '0';
bf_bchg <= '0';
bf_ins <= '0';
954,7 → 954,9
END IF;
IF rising_edge(clk) THEN
IF clkena_lw = '1' THEN
IF Reset='1' THEN
Flags(7 downto 0) <= "00000000";
ELSIF clkena_lw = '1' THEN
IF exec(directSR)='1' OR set_stop='1' THEN
Flags(7 downto 0) <= data_read(7 downto 0);
END IF;
/trunk/TG68KdotC_Kernel.vhd
1,9 → 1,9
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2018 Tobias Gubener --
-- Copyright (c) 2009-2019 Tobias Gubener --
-- Patches by MikeJ, Till Harbaum, Rok Krajnk, ... --
-- Subdesign fAMpIGA by TobiFlex --
-- Patches by MikeJ, Till Harbaum, Rok Krajnk, ... --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published --
21,6 → 21,9
------------------------------------------------------------------------------
------------------------------------------------------------------------------
 
-- 30.10.2019 TG bugfix RTR in 68020-mode
-- 30.10.2019 TG bugfix BFINS again
-- 19.10.2019 TG insert some bugfixes from apolkosnik
-- 05.12.2018 TG insert RTD opcode
-- 03.12.2018 TG insert barrel shifter
-- 01.11.2017 TG bugfix V-Flag for ASL/ASR - thanks Peter Graf
94,231 → 97,233
-- BarrelShifter : integer := 0; --0=>no, 1=>yes, 2=>switchable with CPU(1)
-- BitField : integer := 0 --0=>no, 1=>yes, 2=>switchable with CPU(1)
);
port(clk : in std_logic;
nReset : in std_logic; --low active
clkena_in : in std_logic:='1';
data_in : in std_logic_vector(15 downto 0);
port(clk : in std_logic;
nReset : in std_logic; --low active
clkena_in : in std_logic:='1';
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0):="111";
IPL_autovector : in std_logic:='0';
berr : in std_logic:='0'; -- only 68000 Stackpointer dummy
CPU : in std_logic_vector(1 downto 0):="00"; -- 00->68000 01->68010 11->68020(only some parts - yet)
addr : buffer std_logic_vector(31 downto 0);
data_write : out std_logic_vector(15 downto 0);
addr_out : out std_logic_vector(31 downto 0);
data_write : out std_logic_vector(15 downto 0);
nWr : out std_logic;
nUDS, nLDS : out std_logic;
busstate : out std_logic_vector(1 downto 0); -- 00-> fetch code 10->read data 11->write data 01->no memaccess
nResetOut : out std_logic;
FC : out std_logic_vector(2 downto 0);
FC : out std_logic_vector(2 downto 0);
--
clr_berr : out std_logic;
-- for debug
skipFetch : out std_logic;
-- regin : buffer std_logic_vector(31 downto 0)
-- regin_out : out std_logic_vector(31 downto 0);
-- regin : buffer std_logic_vector(31 downto 0)
regin_out : out std_logic_vector(31 downto 0);
CACR_out : out std_logic_vector( 3 downto 0);
VBR_out : out std_logic_vector(31 downto 0)
);
);
end TG68KdotC_Kernel;
 
architecture logic of TG68KdotC_Kernel is
 
 
signal syncReset : std_logic_vector(3 downto 0);
signal Reset : std_logic;
signal clkena_lw : std_logic;
signal TG68_PC : std_logic_vector(31 downto 0);
signal tmp_TG68_PC : std_logic_vector(31 downto 0);
signal TG68_PC_add : std_logic_vector(31 downto 0);
signal PC_dataa : std_logic_vector(31 downto 0);
signal PC_datab : std_logic_vector(31 downto 0);
signal memaddr : std_logic_vector(31 downto 0);
signal state : std_logic_vector(1 downto 0);
signal datatype : std_logic_vector(1 downto 0);
signal set_datatype : std_logic_vector(1 downto 0);
signal exe_datatype : std_logic_vector(1 downto 0);
signal setstate : std_logic_vector(1 downto 0);
signal syncReset : std_logic_vector(3 downto 0);
signal Reset : std_logic;
signal clkena_lw : std_logic;
signal TG68_PC : std_logic_vector(31 downto 0);
signal tmp_TG68_PC : std_logic_vector(31 downto 0);
signal TG68_PC_add : std_logic_vector(31 downto 0);
signal PC_dataa : std_logic_vector(31 downto 0);
signal PC_datab : std_logic_vector(31 downto 0);
signal memaddr : std_logic_vector(31 downto 0);
signal state : std_logic_vector(1 downto 0);
signal datatype : std_logic_vector(1 downto 0);
signal set_datatype : std_logic_vector(1 downto 0);
signal exe_datatype : std_logic_vector(1 downto 0);
signal setstate : std_logic_vector(1 downto 0);
 
signal opcode : std_logic_vector(15 downto 0);
signal exe_opcode : std_logic_vector(15 downto 0);
signal sndOPC : std_logic_vector(15 downto 0);
signal opcode : std_logic_vector(15 downto 0);
signal exe_opcode : std_logic_vector(15 downto 0);
signal sndOPC : std_logic_vector(15 downto 0);
 
signal last_opc_read : std_logic_vector(15 downto 0);
signal registerin : std_logic_vector(31 downto 0);
signal reg_QA : std_logic_vector(31 downto 0);
signal reg_QB : std_logic_vector(31 downto 0);
signal Wwrena,Lwrena : bit;
signal Bwrena : bit;
signal Regwrena_now : bit;
signal last_opc_read : std_logic_vector(15 downto 0);
signal registerin : std_logic_vector(31 downto 0);
signal reg_QA : std_logic_vector(31 downto 0);
signal reg_QB : std_logic_vector(31 downto 0);
signal Wwrena,Lwrena : bit;
signal Bwrena : bit;
signal Regwrena_now : bit;
signal rf_dest_addr : std_logic_vector(3 downto 0);
signal rf_source_addr : std_logic_vector(3 downto 0);
signal rf_source_addrd : std_logic_vector(3 downto 0);
signal regin : std_logic_vector(31 downto 0);
type regfile_t is array(0 to 15) of std_logic_vector(31 downto 0);
signal regfile : regfile_t := (OTHERS => (OTHERS => '0')); -- mikej stops sim X issues;
signal RDindex_A : integer range 0 to 15;
signal RDindex_B : integer range 0 to 15;
signal WR_AReg : std_logic;
signal regin : std_logic_vector(31 downto 0);
type regfile_t is array(0 to 15) of std_logic_vector(31 downto 0);
signal regfile : regfile_t := (OTHERS => (OTHERS => '0')); -- mikej stops sim X issues;
signal RDindex_A : integer range 0 to 15;
signal RDindex_B : integer range 0 to 15;
signal WR_AReg : std_logic;
 
 
signal memaddr_reg : std_logic_vector(31 downto 0);
signal memaddr_delta : std_logic_vector(31 downto 0);
signal use_base : bit;
signal addr : std_logic_vector(31 downto 0);
signal memaddr_reg : std_logic_vector(31 downto 0);
signal memaddr_delta : std_logic_vector(31 downto 0);
signal use_base : bit;
signal ea_data : std_logic_vector(31 downto 0);
signal OP1out, OP2out : std_logic_vector(31 downto 0);
signal OP1outbrief : std_logic_vector(15 downto 0);
signal OP1in : std_logic_vector(31 downto 0);
signal ALUout : std_logic_vector(31 downto 0);
signal data_write_tmp : std_logic_vector(31 downto 0);
signal data_write_muxin : std_logic_vector(31 downto 0);
signal data_write_mux : std_logic_vector(47 downto 0);
signal nextpass : bit;
signal setnextpass : bit;
signal setdispbyte : bit;
signal setdisp : bit;
signal regdirectsource :bit; -- checken !!!
signal addsub_q : std_logic_vector(31 downto 0);
signal briefdata : std_logic_vector(31 downto 0);
-- signal c_in : std_logic_vector(3 downto 0);
signal c_out : std_logic_vector(2 downto 0);
signal ea_data : std_logic_vector(31 downto 0);
signal OP1out : std_logic_vector(31 downto 0);
signal OP2out : std_logic_vector(31 downto 0);
signal OP1outbrief : std_logic_vector(15 downto 0);
signal OP1in : std_logic_vector(31 downto 0);
signal ALUout : std_logic_vector(31 downto 0);
signal data_write_tmp : std_logic_vector(31 downto 0);
signal data_write_muxin : std_logic_vector(31 downto 0);
signal data_write_mux : std_logic_vector(47 downto 0);
signal nextpass : bit;
signal setnextpass : bit;
signal setdispbyte : bit;
signal setdisp : bit;
signal regdirectsource :bit; -- checken !!!
signal addsub_q : std_logic_vector(31 downto 0);
signal briefdata : std_logic_vector(31 downto 0);
-- signal c_in : std_logic_vector(3 downto 0);
signal c_out : std_logic_vector(2 downto 0);
 
signal mem_address : std_logic_vector(31 downto 0);
signal memaddr_a : std_logic_vector(31 downto 0);
signal mem_address : std_logic_vector(31 downto 0);
signal memaddr_a : std_logic_vector(31 downto 0);
 
signal TG68_PC_brw : bit;
signal TG68_PC_word : bit;
signal getbrief : bit;
signal brief : std_logic_vector(15 downto 0);
signal dest_areg : std_logic;
signal source_areg : std_logic;
signal data_is_source : bit;
signal store_in_tmp : bit;
signal write_back : bit;
signal exec_write_back: bit;
signal setstackaddr : bit;
signal writePC : bit;
signal writePCbig : bit;
signal set_writePCbig : bit;
signal setopcode : bit;
signal decodeOPC : bit;
signal execOPC : bit;
signal setexecOPC : bit;
signal endOPC : bit;
signal setendOPC : bit;
signal Flags : std_logic_vector(7 downto 0); -- ...XNZVC
signal FlagsSR : std_logic_vector(7 downto 0); -- T.S..III
signal SRin : std_logic_vector(7 downto 0);
signal exec_DIRECT : bit;
signal exec_tas : std_logic;
signal set_exec_tas : std_logic;
signal TG68_PC_brw : bit;
signal TG68_PC_word : bit;
signal getbrief : bit;
signal brief : std_logic_vector(15 downto 0);
signal dest_areg : std_logic;
signal source_areg : std_logic;
signal data_is_source : bit;
signal store_in_tmp : bit;
signal write_back : bit;
signal exec_write_back : bit;
signal setstackaddr : bit;
signal writePC : bit;
signal writePCbig : bit;
signal set_writePCbig : bit;
signal setopcode : bit;
signal decodeOPC : bit;
signal execOPC : bit;
signal setexecOPC : bit;
signal endOPC : bit;
signal setendOPC : bit;
signal Flags : std_logic_vector(7 downto 0); -- ...XNZVC
signal FlagsSR : std_logic_vector(7 downto 0); -- T.S.0III
signal SRin : std_logic_vector(7 downto 0);
signal exec_DIRECT : bit;
signal exec_tas : std_logic;
signal set_exec_tas : std_logic;
 
signal exe_condition : std_logic;
signal ea_only : bit;
signal source_lowbits : bit;
signal source_2ndHbits : bit;
signal source_2ndLbits : bit;
signal dest_2ndHbits : bit;
signal dest_hbits : bit;
signal rot_bits : std_logic_vector(1 downto 0);
signal set_rot_bits : std_logic_vector(1 downto 0);
signal rot_cnt : std_logic_vector(5 downto 0);
signal set_rot_cnt : std_logic_vector(5 downto 0);
signal movem_actiond : bit;
signal movem_regaddr : std_logic_vector(3 downto 0);
signal movem_mux : std_logic_vector(3 downto 0);
signal movem_presub : bit;
signal movem_run : bit;
signal ea_calc_b : std_logic_vector(31 downto 0);
signal set_direct_data: bit;
signal use_direct_data: bit;
signal direct_data : bit;
signal exe_condition : std_logic;
signal ea_only : bit;
signal source_lowbits : bit;
signal source_2ndHbits : bit;
signal source_2ndLbits : bit;
signal dest_2ndHbits : bit;
signal dest_hbits : bit;
signal rot_bits : std_logic_vector(1 downto 0);
signal set_rot_bits : std_logic_vector(1 downto 0);
signal rot_cnt : std_logic_vector(5 downto 0);
signal set_rot_cnt : std_logic_vector(5 downto 0);
signal movem_actiond : bit;
signal movem_regaddr : std_logic_vector(3 downto 0);
signal movem_mux : std_logic_vector(3 downto 0);
signal movem_presub : bit;
signal movem_run : bit;
signal ea_calc_b : std_logic_vector(31 downto 0);
signal set_direct_data : bit;
signal use_direct_data : bit;
signal direct_data : bit;
 
signal set_V_Flag : bit;
signal set_vectoraddr : bit;
signal writeSR : bit;
signal trap_berr : bit;
signal trap_illegal : bit;
signal trap_addr_error : bit;
signal trap_priv : bit;
signal trap_trace : bit;
signal trap_1010 : bit;
signal trap_1111 : bit;
signal trap_trap : bit;
signal trap_trapv : bit;
signal trap_interrupt : bit;
signal trapmake : bit;
signal trapd : bit;
signal trap_SR : std_logic_vector(7 downto 0);
signal make_trace : std_logic;
signal make_berr : std_logic;
signal set_V_Flag : bit;
signal set_vectoraddr : bit;
signal writeSR : bit;
signal trap_berr : bit;
signal trap_illegal : bit;
signal trap_addr_error : bit;
signal trap_priv : bit;
signal trap_trace : bit;
signal trap_1010 : bit;
signal trap_1111 : bit;
signal trap_trap : bit;
signal trap_trapv : bit;
signal trap_interrupt : bit;
signal trapmake : bit;
signal trapd : bit;
signal trap_SR : std_logic_vector(7 downto 0);
signal make_trace : std_logic;
signal make_berr : std_logic;
signal set_stop : bit;
signal stop : bit;
signal trap_vector : std_logic_vector(31 downto 0);
signal trap_vector_vbr : std_logic_vector(31 downto 0);
signal USP : std_logic_vector(31 downto 0);
-- signal illegal_write_mode : bit;
-- signal illegal_read_mode : bit;
-- signal illegal_byteaddr : bit;
signal set_stop : bit;
signal stop : bit;
signal trap_vector : std_logic_vector(31 downto 0);
signal trap_vector_vbr : std_logic_vector(31 downto 0);
signal USP : std_logic_vector(31 downto 0);
-- signal illegal_write_mode : bit;
-- signal illegal_read_mode : bit;
-- signal illegal_byteaddr : bit;
 
signal IPL_nr : std_logic_vector(2 downto 0);
signal rIPL_nr : std_logic_vector(2 downto 0);
signal IPL_vec : std_logic_vector(7 downto 0);
signal interrupt : bit;
signal setinterrupt : bit;
signal SVmode : std_logic;
signal preSVmode : std_logic;
signal Suppress_Base : bit;
signal set_Suppress_Base : bit;
signal set_Z_error : bit;
signal Z_error : bit;
signal ea_build_now : bit;
signal build_logical : bit;
signal build_bcd : bit;
signal IPL_nr : std_logic_vector(2 downto 0);
signal rIPL_nr : std_logic_vector(2 downto 0);
signal IPL_vec : std_logic_vector(7 downto 0);
signal interrupt : bit;
signal setinterrupt : bit;
signal SVmode : std_logic;
signal preSVmode : std_logic;
signal Suppress_Base : bit;
signal set_Suppress_Base: bit;
signal set_Z_error : bit;
signal Z_error : bit;
signal ea_build_now : bit;
signal build_logical : bit;
signal build_bcd : bit;
signal data_read : std_logic_vector(31 downto 0);
signal bf_ext_in : std_logic_vector(7 downto 0);
signal bf_ext_out : std_logic_vector(7 downto 0);
-- signal byte : bit;
signal long_start : bit;
signal data_read : std_logic_vector(31 downto 0);
signal bf_ext_in : std_logic_vector(7 downto 0);
signal bf_ext_out : std_logic_vector(7 downto 0);
-- signal byte : bit;
signal long_start : bit;
signal long_start_alu : bit;
signal non_aligned : std_logic;
signal long_done : bit;
signal memmask : std_logic_vector(5 downto 0);
signal set_memmask : std_logic_vector(5 downto 0);
signal memread : std_logic_vector(3 downto 0);
signal wbmemmask : std_logic_vector(5 downto 0);
signal memmaskmux : std_logic_vector(5 downto 0);
signal oddout : std_logic;
signal set_oddout : std_logic;
signal PCbase : std_logic;
signal set_PCbase : std_logic;
signal non_aligned : std_logic;
signal long_done : bit;
signal memmask : std_logic_vector(5 downto 0);
signal set_memmask : std_logic_vector(5 downto 0);
signal memread : std_logic_vector(3 downto 0);
signal wbmemmask : std_logic_vector(5 downto 0);
signal memmaskmux : std_logic_vector(5 downto 0);
signal oddout : std_logic;
signal set_oddout : std_logic;
signal PCbase : std_logic;
signal set_PCbase : std_logic;
signal last_data_read : std_logic_vector(31 downto 0);
signal last_data_in : std_logic_vector(31 downto 0);
signal last_data_read : std_logic_vector(31 downto 0);
signal last_data_in : std_logic_vector(31 downto 0);
 
signal bf_offset : std_logic_vector(5 downto 0);
signal bf_width : std_logic_vector(5 downto 0);
signal bf_bhits : std_logic_vector(5 downto 0);
signal bf_shift : std_logic_vector(5 downto 0);
signal alu_width : std_logic_vector(5 downto 0);
signal alu_bf_shift : std_logic_vector(5 downto 0);
signal bf_loffset : std_logic_vector(5 downto 0);
signal bf_full_offset : std_logic_vector(31 downto 0);
signal alu_bf_ffo_offset : std_logic_vector(31 downto 0);
signal alu_bf_loffset : std_logic_vector(5 downto 0);
signal bf_offset : std_logic_vector(5 downto 0);
signal bf_width : std_logic_vector(5 downto 0);
signal bf_bhits : std_logic_vector(5 downto 0);
signal bf_shift : std_logic_vector(5 downto 0);
signal alu_width : std_logic_vector(5 downto 0);
signal alu_bf_shift : std_logic_vector(5 downto 0);
signal bf_loffset : std_logic_vector(5 downto 0);
signal bf_full_offset : std_logic_vector(31 downto 0);
signal alu_bf_ffo_offset: std_logic_vector(31 downto 0);
signal alu_bf_loffset : std_logic_vector(5 downto 0);
 
signal movec_data : std_logic_vector(31 downto 0);
signal VBR : std_logic_vector(31 downto 0);
signal CACR : std_logic_vector(3 downto 0);
signal DFC : std_logic_vector(2 downto 0);
signal SFC : std_logic_vector(2 downto 0);
signal movec_data : std_logic_vector(31 downto 0);
signal VBR : std_logic_vector(31 downto 0);
signal CACR : std_logic_vector(3 downto 0);
signal DFC : std_logic_vector(2 downto 0);
signal SFC : std_logic_vector(2 downto 0);
 
signal set : bit_vector(lastOpcBit downto 0);
signal set_exec : bit_vector(lastOpcBit downto 0);
signal exec : bit_vector(lastOpcBit downto 0);
signal set : bit_vector(lastOpcBit downto 0);
signal set_exec : bit_vector(lastOpcBit downto 0);
signal exec : bit_vector(lastOpcBit downto 0);
 
signal micro_state : micro_states;
signal next_micro_state : micro_states;
329,10 → 334,10
 
ALU: TG68K_ALU
generic map(
MUL_Mode => MUL_Mode, --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
MUL_Hardware => MUL_Hardware, --0=>no, 1=>yes,
DIV_Mode => DIV_Mode, --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
BarrelShifter => BarrelShifter --0=>no, 1=>yes, 2=>switchable with CPU(1)
MUL_Mode => MUL_Mode, --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
MUL_Hardware => MUL_Hardware, --0=>no, 1=>yes,
DIV_Mode => DIV_Mode, --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
BarrelShifter => BarrelShifter --0=>no, 1=>yes, 2=>switchable with CPU(1)
)
port map(
clk => clk, --: in std_logic;
343,13 → 348,13
exe_condition => exe_condition, --: in std_logic;
exec_tas => exec_tas, --: in std_logic;
long_start => long_start_alu, --: in bit;
non_aligned => non_aligned,
non_aligned => non_aligned,
movem_presub => movem_presub, --: in bit;
set_stop => set_stop, --: in bit;
Z_error => Z_error, --: in bit;
 
rot_bits => rot_bits, --: in std_logic_vector(1 downto 0);
exec => exec, --: in bit_vector(lastOpcBit downto 0);
exec => exec, --: in bit_vector(lastOpcBit downto 0);
OP1out => OP1out, --: in std_logic_vector(31 downto 0);
OP2out => OP2out, --: in std_logic_vector(31 downto 0);
reg_QA => reg_QA, --: in std_logic_vector(31 downto 0);
362,13 → 367,13
last_data_read => last_data_read(15 downto 0), --: in std_logic_vector(31 downto 0);
data_read => data_read(15 downto 0), --: in std_logic_vector(31 downto 0);
FlagsSR => FlagsSR, --: in std_logic_vector(7 downto 0);
micro_state => micro_state, --: in micro_states;
bf_ext_in => bf_ext_in,
bf_ext_out => bf_ext_out,
bf_shift => alu_bf_shift,
bf_width => alu_width,
bf_ffo_offset => alu_bf_ffo_offset,
bf_loffset => alu_bf_loffset(4 downto 0),
micro_state => micro_state, --: in micro_states;
bf_ext_in => bf_ext_in,
bf_ext_out => bf_ext_out,
bf_shift => alu_bf_shift,
bf_width => alu_width,
bf_ffo_offset => alu_bf_ffo_offset,
bf_loffset => alu_bf_loffset(4 downto 0),
set_V_Flag => set_V_Flag, --: buffer bit;
Flags => Flags, --: buffer std_logic_vector(8 downto 0);
377,18 → 382,21
ALUout => ALUout --: buffer std_logic_vector(31 downto 0)
);
long_start_alu <= to_bit(NOT memmaskmux(3));
long_start_alu <= to_bit(NOT memmaskmux(3));
process (memmaskmux)
begin
non_aligned <= '0';
if (memmaskmux(5 downto 4) = "01") or (memmaskmux(5 downto 4) = "10") then
non_aligned <= '1';
end if;
non_aligned <= '0';
if (memmaskmux(5 downto 4) = "01") or (memmaskmux(5 downto 4) = "10") then
non_aligned <= '1';
end if;
end process;
-----------------------------------------------------------------------------
-- Bus control
-----------------------------------------------------------------------------
regin_out <= regin;
 
 
nWr <= '0' WHEN state="11" ELSE '1';
busstate <= state;
nResetOut <= '0' WHEN exec(opcRESET)='1' ELSE '1';
566,12 → 574,16
rf_dest_addr <= rf_source_addrd;
ELSIF set(briefext)='1' THEN
rf_dest_addr <= brief(15 downto 12);
ELSIF set(get_bfoffset)='1' THEN
rf_dest_addr <= sndOPC(9 downto 6);
ELSIF set(get_bfoffset)='1' THEN
IF opcode(15 downto 12)="1110" THEN
rf_dest_addr <= '0'&sndOPC(8 downto 6);
ELSE
rf_dest_addr <= sndOPC(9 downto 6);
END IF;
ELSIF dest_2ndHbits='1' THEN
rf_dest_addr <= sndOPC(15 downto 12);
rf_dest_addr <= '0'&sndOPC(14 downto 12);
ELSIF set(write_reminder)='1' THEN
rf_dest_addr <= sndOPC(3 downto 0);
rf_dest_addr <= '0'&sndOPC(2 downto 0);
ELSIF setstackaddr='1' THEN
rf_dest_addr <= "1111";
ELSIF dest_hbits='1' THEN
597,9 → 609,9
rf_source_addr <= movem_regaddr;
END IF;
ELSIF source_2ndLbits='1' THEN
rf_source_addr <= sndOPC(3 downto 0);
rf_source_addr <= '0'&sndOPC(2 downto 0);
ELSIF source_2ndHbits='1' THEN
rf_source_addr <= sndOPC(15 downto 12);
rf_source_addr <= '0'&sndOPC(14 downto 12);
ELSIF source_lowbits='1' THEN
rf_source_addr <= source_areg&opcode(2 downto 0);
ELSIF exec(linksp)='1' THEN
887,6 → 899,8
 
-- if access done, and not aligned, don't increment
addr <= memaddr_reg+memaddr_delta;
addr_out <= memaddr_reg + memaddr_delta;
 
IF use_base='0' THEN
memaddr_reg <= (others=>'0');
ELSE
898,7 → 912,7
-- PC Calc + fetch opcode
-----------------------------------------------------------------------------
PROCESS (clk, IPL, setstate, state, exec_write_back, set_direct_data, next_micro_state, stop, make_trace, make_berr, IPL_nr, FlagsSR, set_rot_cnt, opcode, writePCbig, set_exec, exec,
PC_dataa, PC_datab, setnextpass, last_data_read, TG68_PC_brw, TG68_PC_word, Z_error, trap_trap, trap_trapv, interrupt, tmp_TG68_PC, TG68_PC)
PC_dataa, PC_datab, setnextpass, last_data_read, TG68_PC_brw, TG68_PC_word, Z_error, trap_trap, trap_trapv, interrupt, tmp_TG68_PC, TG68_PC)
BEGIN
PC_dataa <= TG68_PC;
955,7 → 969,7
IPL_nr <= NOT IPL;
IF rising_edge(clk) THEN
IF Reset = '1' THEN
IF Reset = '1' THEN
state <= "01";
opcode <= X"2E79"; --move $0,a7
trap_interrupt <= '0';
1210,6 → 1224,8
bf_bhits <= bf_width+bf_offset;
set_oddout <= NOT bf_bhits(3);
 
-- bf_loffset is used for the shifted_bitmask
IF opcode(10 downto 8)="111" THEN --INS
bf_loffset <= 32-bf_shift;
ELSE
1216,10 → 1232,6
bf_loffset <= bf_shift;
END IF;
bf_loffset(5) <= '0';
-- IF set_exec(exec_BS)='1' THEN
-- bf_width(4 downto 0)<="01111";
-- bf_loffset(4 downto 0) <= "00000";
-- END IF;
IF opcode(4 downto 3)="00" THEN
IF opcode(10 downto 8)="111" THEN --INS
1229,29 → 1241,30
END IF;
bf_shift(5) <= '0';
ELSE
IF opcode(10 downto 8)="111" THEN --INS
bf_shift <= "011"&("001"+bf_bhits(2 downto 0));
IF opcode(10 downto 8)="111" THEN --INS
bf_shift <= "011001"+("000"&bf_bhits(2 downto 0));
bf_shift(5) <= '0';
ELSE
bf_shift <= "000"&("111"-bf_bhits(2 downto 0));
END IF;
bf_offset(4 downto 3) <= "00";
END IF;
CASE bf_bhits(5 downto 3) IS
WHEN "000" =>
set_memmask <= "101111";
WHEN "001" =>
set_memmask <= "100111";
WHEN "010" =>
set_memmask <= "100011";
WHEN "011" =>
set_memmask <= "100001";
WHEN OTHERS =>
set_memmask <= "100000";
END CASE;
IF setstate="00" THEN
CASE bf_bhits(5 downto 3) IS
WHEN "000" =>
set_memmask <= "101111";
WHEN "001" =>
set_memmask <= "100111";
END IF;
WHEN "010" =>
set_memmask <= "100011";
WHEN "011" =>
set_memmask <= "100001";
WHEN OTHERS =>
set_memmask <= "100000";
END CASE;
IF setstate="00" THEN
set_memmask <= "100111";
END IF;
END PROCESS;
------------------------------------------------------------------------------
1270,12 → 1283,12
END IF;
IF rising_edge(clk) THEN
IF Reset='1' THEN
IF Reset='1' THEN
FlagsSR(5) <= '1';
FC(2) <= '1';
SVmode <= '1';
preSVmode <= '1';
FlagsSR(2 downto 0) <= "111";
FlagsSR(3 downto 0) <= "0111";
make_trace <= '0';
ELSIF clkena_lw = '1' THEN
IF setopcode='1' THEN
1303,11 → 1316,9
IF interrupt='1' AND trap_interrupt='1' THEN
FlagsSR(2 downto 0) <=rIPL_nr;
END IF;
-- IF exec(to_CCR)='1' AND exec(to_SR)='1' THEN
IF exec(to_SR)='1' THEN
FlagsSR(7 downto 0) <= SRin; --SR
FC(2) <= SRin(5);
-- END IF;
ELSIF exec(update_FC)='1' THEN
FC(2) <= FlagsSR(5);
END IF;
1314,6 → 1325,7
IF interrupt='1' THEN
FC(2) <= '1';
END IF;
FlagsSR(3) <= '0';
END IF;
END IF;
END PROCESS;
1766,7 → 1778,6
WHEN "000"=>
IF opcode(7 downto 6)="11" THEN --move from SR
IF SR_Read=0 OR (cpu(0)='0' AND SR_Read=2) OR SVmode='1' THEN
-- IF SVmode='1' THEN
ea_build_now <= '1';
set_exec(opcMOVESR) <= '1';
datatype <= "01";
3138,16 → 3149,16
setstate <= "10";
set(postadd) <= '1';
setstackaddr <= '1';
IF VBR_Stackframe=0 OR (cpu(0)='0' AND VBR_Stackframe=2) THEN
set(directPC) <= '1';
IF VBR_Stackframe=0 OR (cpu(0)='0' AND VBR_Stackframe=2) OR opcode(2)='1' THEN --opcode(2)='1' => opcode is RTR
set(update_FC) <= '1';
set(direct_delta) <= '1';
END IF;
set(directPC) <= '1';
next_micro_state <= rte2;
WHEN rte2 => -- RTE
datatype <= "01";
set(update_FC) <= '1';
IF VBR_Stackframe=1 OR (cpu(0)='1' AND VBR_Stackframe=2) THEN
IF (VBR_Stackframe=1 OR (cpu(0)='1' AND VBR_Stackframe=2)) AND opcode(2)='0' THEN
setstate <= "10";
set(postadd) <= '1';
setstackaddr <= '1';

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