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Rev 51 → Rev 52

/FT64v5/rtl/common/FT64_config.vh
28,8 → 28,8
 
`define AMSB 31
`define ABITS `AMSB:0
`define QBITS 2:0
`define QENTRIES 8
`define QBITS 3:0
`define QENTRIES 10
`define XBITS 7:0
 
//`define SUPPORT_DBG 1'b1
64,4 → 64,7
`define WB_DEPTH 8 // must be one more than desired depth
 
// Uncomment to allow SIMD operations
`define SIMD 1'b1
`define SIMD 1'b1
 
// Comment the following to disable registering the output of instruction decoders.
`define REGISTER_DECODE
/FT64v5/rtl/common/FT64_idecoder.v
22,6 → 22,7
//
// ============================================================================
//
`include ".\FT64_config.vh"
`include ".\FT64_defines.vh"
 
module FT64_idecoder(clk,idv_i,id_i,instr,vl,ven,thrd,predict_taken,Rt,bus,id_o,idv_o);
926,7 → 927,11
endcase
endfunction
 
`ifdef REGISTER_DECODE
always @(posedge clk)
`else
always @*
`endif
begin
bus <= 144'h0;
bus[`IB_CONST] <= instr[6]==1'b1 ? {{34{instr[47]}},instr[47:18]} :
/FT64v5/rtl/common/FT64_iexpander.v
202,7 → 202,7
5'b10??0:
begin
expand[47:32] = 16'h0000;
expand[31:21] = {{6{cinstr[11]}},cinstr[11:8],cinstr[5]};
expand[31:21] = {{4{cinstr[13]}},cinstr[13:8],cinstr[5]};
expand[20:18] = 3'd0; // BEQ
expand[17:13] = 5'd0; // r0
expand[12:8] = cinstr[4:0]; // Ra
212,7 → 212,7
5'b11??0:
begin
expand[47:32] = 16'h0000;
expand[31:21] = {{6{cinstr[11]}},cinstr[11:8],cinstr[5]};
expand[31:21] = {{4{cinstr[13]}},cinstr[13:8],cinstr[5]};
expand[20:18] = 3'd1; // BNE
expand[17:13] = 5'd0; // r0
expand[12:8] = cinstr[4:0]; // Ra
/FT64v5/rtl/common/FT64_mpu.v
89,7 → 89,7
wire [31:0] adr;
reg [63:0] dati;
wire [3:0] irq;
wire [6:0] cause;
wire [7:0] cause;
wire mmu_ack;
wire [31:0] mmu_dato;
wire pic_ack;
/FT64v5/rtl/common/FT64_pic.v
57,8 → 57,8
//
// 0x80 - irq control for irq #0
// 0x84 - irq control for irq #1
// bits 0 to 6 = cause code to issue
// bits 8 to 10 = irq level to issue
// bits 0 to 7 = cause code to issue
// bits 8 to 11 = irq level to issue
// bit 16 = irq enable
// bit 17 = edge sensitivity
//=============================================================================
97,7 → 97,7
reg [31:0] es;
reg [5:0] cause_base;
reg [3:0] irq [0:31];
reg [6:0] cause [0:31];
reg [7:0] cause [0:31];
integer n;
 
initial begin
105,7 → 105,7
es <= 32'hFFFFFFFF;
rste <= 32'h0;
for (n = 0; n < 32; n = n + 1) begin
cause[n] <= 7'h00;
cause[n] <= 8'h00;
irq[n] <= 4'h8;
end
end
138,7 → 138,7
6'd5: rste[dat_i[4:0]] <= 1'b1;
6'b1?????:
begin
cause[adr_i[6:2]] <= dat_i[6:0];
cause[adr_i[6:2]] <= dat_i[7:0];
irq[adr_i[6:2]] <= dat_i[11:8];
ie[adr_i[6:2]] <= dat_i[16];
es[adr_i[6:2]] <= dat_i[17];
155,7 → 155,7
if (cs)
casez (adr_i[7:2])
6'd0: dat_o <= {cause_base,3'd0} + irqenc;
6'b1?????: dat_o <= {es[adr_i[6:2]],ie[adr_i[6:2]],4'b0,irq[adr_i[6:2]],1'b0,cause[adr_i[6:2]]};
6'b1?????: dat_o <= {es[adr_i[6:2]],ie[adr_i[6:2]],4'b0,irq[adr_i[6:2]],cause[adr_i[6:2]]};
default: dat_o <= ie;
endcase
else
163,7 → 163,7
end
 
assign irqo = (irqenc == 5'h0) ? 4'd0 : irq[irqenc];
assign causeo = (irqenc == 5'h0) ? 7'd0 : cause[irqenc];
assign causeo = (irqenc == 5'h0) ? 8'd0 : cause[irqenc];
assign nmio = nmii & ie[0];
 
// Edge detect circuit
/FT64v5/rtl/twoway/FT64.v
99,7 → 99,7
parameter NTHREAD = 1;
reg [3:0] i;
integer n;
integer j;
integer j, k;
genvar g;
parameter TRUE = 1'b1;
parameter FALSE = 1'b0;
167,10 → 167,10
reg [63:0] wbrcd;
 
reg [PREGS-1:0] rf_v;
reg [4:0] rf_source[0:AREGS-1];
reg [5:0] rf_source[0:AREGS-1];
initial begin
for (n = 0; n < AREGS; n = n + 1)
rf_source[n] = 5'd0;
rf_source[n] = 6'd0;
end
wire [`ABITS] pc0;
wire [`ABITS] pc1;
197,6 → 197,7
wire snr = cr0[17]; // sequence number reset
wire dce = cr0[30]; // data cache enable
wire bpe = cr0[32]; // branch predictor enable
wire wbm = cr0[34];
wire ctgtxe = cr0[33];
reg [63:0] pmr;
wire id1_available = pmr[0];
386,7 → 387,8
wire int_commit;
reg StatusHWI;
reg [47:0] insn0, insn1, insn2;
wire [47:0] insn0a, insn1a, insn1b, insn2a, insn2b;
wire [47:0] insn0a, insn1b, insn2b;
reg [47:0] insn1a, insn2a;
reg tgtq;
// Only need enough bits in the seqnence number to cover the instructions in
// the queue plus an extra count for skipping on branch misses. In this case
402,7 → 404,7
reg queuedNop;
 
reg [47:0] codebuf[0:63];
reg [7:0] setpred;
reg [QENTRIES-1:0] setpred;
 
// instruction queue (ROB)
reg [31:0] iqentry_sn [0:QENTRIES-1]; // instruction sequence number
415,6 → 417,7
reg [QENTRIES-1:0] iqentry_thrd; // which thread the instruction is in
reg [QENTRIES-1:0] iqentry_pt; // predict taken
reg [QENTRIES-1:0] iqentry_bt; // update branch target buffer
reg [QENTRIES-1:0] iqentry_takb; // take branch record
reg [QENTRIES-1:0] iqentry_jal;
reg [QENTRIES-1:0] iqentry_agen; // address-generate ... signifies that address is ready (only for LW/SW)
reg [1:0] iqentry_state [0:QENTRIES-1];
511,6 → 514,19
wire [PREGS-1:1] iqentry_5_livetarget;
wire [PREGS-1:1] iqentry_6_livetarget;
wire [PREGS-1:1] iqentry_7_livetarget;
wire [PREGS-1:1] iqentry_8_livetarget;
wire [PREGS-1:1] iqentry_9_livetarget;
wire [PREGS-1:1] iqentry_livetarget [0:QENTRIES-1];
assign iqentry_livetarget[0] = iqentry_0_livetarget;
assign iqentry_livetarget[1] = iqentry_1_livetarget;
assign iqentry_livetarget[2] = iqentry_2_livetarget;
assign iqentry_livetarget[3] = iqentry_3_livetarget;
assign iqentry_livetarget[4] = iqentry_4_livetarget;
assign iqentry_livetarget[5] = iqentry_5_livetarget;
assign iqentry_livetarget[6] = iqentry_6_livetarget;
assign iqentry_livetarget[7] = iqentry_7_livetarget;
assign iqentry_livetarget[8] = iqentry_8_livetarget;
assign iqentry_livetarget[9] = iqentry_9_livetarget;
wire [PREGS-1:1] iqentry_0_latestID;
wire [PREGS-1:1] iqentry_1_latestID;
wire [PREGS-1:1] iqentry_2_latestID;
519,6 → 535,8
wire [PREGS-1:1] iqentry_5_latestID;
wire [PREGS-1:1] iqentry_6_latestID;
wire [PREGS-1:1] iqentry_7_latestID;
wire [PREGS-1:1] iqentry_8_latestID;
wire [PREGS-1:1] iqentry_9_latestID;
wire [PREGS-1:1] iqentry_0_cumulative;
wire [PREGS-1:1] iqentry_1_cumulative;
wire [PREGS-1:1] iqentry_2_cumulative;
527,6 → 545,9
wire [PREGS-1:1] iqentry_5_cumulative;
wire [PREGS-1:1] iqentry_6_cumulative;
wire [PREGS-1:1] iqentry_7_cumulative;
wire [PREGS-1:1] iqentry_8_cumulative;
wire [PREGS-1:1] iqentry_9_cumulative;
reg [PREGS-1:1] iqentry_cumulative [0:QENTRIES-1];
wire [PREGS-1:1] iq0_out;
wire [PREGS-1:1] iq1_out;
wire [PREGS-1:1] iq2_out;
535,6 → 556,8
wire [PREGS-1:1] iq5_out;
wire [PREGS-1:1] iq6_out;
wire [PREGS-1:1] iq7_out;
wire [PREGS-1:1] iq8_out;
wire [PREGS-1:1] iq9_out;
 
reg [`QBITS] tail0;
reg [`QBITS] tail1;
546,6 → 569,8
reg [`QBITS] head5; // used only to determine memory-access ordering
reg [`QBITS] head6; // used only to determine memory-access ordering
reg [`QBITS] head7; // used only to determine memory-access ordering
reg [`QBITS] head8;
reg [`QBITS] head9;
 
wire take_branch0;
wire take_branch1;
667,6 → 692,7
wire alu1_branchmiss;
wire [`ABITS] alu1_misspc;
 
wire [`XBITS] fpu_exc;
reg fpu1_ld;
reg fpu1_dataready = 1'b1;
wire fpu1_done = 1'b1;
752,6 → 778,7
reg [QENTRIES-1:0] wbo_id;
reg [7:0] wb_sel [0:`WB_DEPTH-1];
reg wb_en;
reg wb_shift;
 
reg branchmiss = 1'b0;
reg branchmiss_thrd = 1'b0;
939,27 → 966,23
wire [`ABITS] pc0plus6 = pc0 + 32'd6;
wire [`ABITS] pc0plus12 = pc0 + 32'd12;
 
`ifdef SUPPORT_SMT
generate begin : gInsnVar
if (`WAYS > 1) begin
assign insn1a = insn1b;
always @*
if (thread_en)
insn1a <= insn1b;
else
insn1a = {insn1b,insn0a} >> {fnInsLength(insn0a),3'b0};
end
if (`WAYS > 2) begin
assign insn2a = insn2b;
always @*
if (thread_en)
insn2a <= insn2b;
else
insn2a = {insn2b,insn1b,insn0a} >> {fnInsLength(insn0a) + fnInsLength(insn1a),3'b0};
end
end
endgenerate
`else
generate begin : gInsnVar
if (`WAYS > 1) begin
assign insn1a = {insn1b,insn0a} >> {fnInsLength(insn0a),3'b0};
end
if (`WAYS > 2) begin
assign insn2a = {insn2b,insn1b,insn0a} >> {fnInsLength(insn0a) + fnInsLength(insn1a),3'b0};
end
end
endgenerate
`endif
 
FT64_L1_icache uic0
(
985,11 → 1008,7
.nxt(icnxt),
.wr(L1_wr1),
.en(L1_en),
`ifdef SUPPORT_SMT
.adr(icstate==IDLE||icstate==IC8 ? {pcr[5:0],pc1} : L1_adr),
`else
.adr(icstate==IDLE||icstate==IC8 ? {pcr[5:0],pc0plus6} : L1_adr),
`endif
.adr(icstate==IDLE||icstate==IC8 ? (thread_en ? {pcr[5:0],pc1}: {pcr[5:0],pc0plus6} ): L1_adr),
.wadr(L1_adr),
.i(L2_rdat),
.o(insn1b),
1009,11 → 1028,7
.nxt(icnxt),
.wr(L1_wr2),
.en(L1_en),
`ifdef SUPPORT_SMT
.adr(icstate==IDLE||icstate==IC8 ? {pcr[5:0],pc2} : L1_adr),
`else
.adr(icstate==IDLE||icstate==IC8 ? {pcr[5:0],pc0plus12} : L1_adr),
`endif
.adr(icstate==IDLE||icstate==IC8 ? (thread_en ? {pcr[5:0],pc2} : {pcr[5:0],pc0plus12}) : L1_adr),
.wadr(L1_adr),
.i(L2_rdat),
.o(insn2b),
1127,8 → 1142,8
.pcD(fetchbufD_pc),
.xpc0(iqentry_pc[head0]),
.xpc1(iqentry_pc[head1]),
.takb0(commit0_v & iqentry_res[head0][0]),
.takb1(commit1_v & iqentry_res[head1][0]),
.takb0(commit0_v & iqentry_takb[head0]),
.takb1(commit1_v & iqentry_takb[head1]),
.predict_takenA(predict_takenA),
.predict_takenB(predict_takenB),
.predict_takenC(predict_takenC),
1381,10 → 1396,10
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
 
// hirq squashes the pc increment if there's an irq.
wire hirq = (irq_i > im) && ~int_commit;
// freezePC squashes the pc increment if there's an irq.
wire freezePC = (irq_i > im) && ~int_commit;
always @*
if (hirq)
if (freezePC)
insn0 <= {8'd0,3'd0,irq_i,1'b0,vec_i,2'b00,`BRK};
else if (phit) begin
if (insn0a[`INSTRUCTION_OP]==`BRK && insn0a[23:21]==3'd0 && insn0a[7:6]==2'b00)
1397,7 → 1412,9
generate begin : gInsnMux
if (`WAYS > 1) begin
always @*
if (phit) begin
if (freezePC && !thread_en)
insn1 <= {8'd0,3'd0,irq_i,1'b0,vec_i,2'b00,`BRK};
else if (phit) begin
if (insn1a[`INSTRUCTION_OP]==`BRK && insn1a[23:21]==3'd0 && insn1a[7:6]==2'b00)
insn1 <= {8'd1,3'd0,4'b0,1'b0,`FLT_PRIV,2'b00,`BRK};
else
1408,7 → 1425,9
end
if (`WAYS > 2) begin
always @*
if (phit) begin
if (freezePC && !thread_en)
insn2 <= {8'd0,3'd0,irq_i,1'b0,vec_i,2'b00,`BRK};
else if (phit) begin
if (insn2a[`INSTRUCTION_OP]==`BRK && insn1a[23:21]==3'd0 && insn2a[7:6]==2'b00)
insn2 <= {8'd1,3'd0,4'b0,1'b0,`FLT_PRIV,2'b00,`BRK};
else
1492,114 → 1511,52
 
function [`QBITS] idp1;
input [`QBITS] id;
case(id)
3'd0: idp1 = 3'd1;
3'd1: idp1 = 3'd2;
3'd2: idp1 = 3'd3;
3'd3: idp1 = 3'd4;
3'd4: idp1 = 3'd5;
3'd5: idp1 = 3'd6;
3'd6: idp1 = 3'd7;
3'd7: idp1 = 3'd0;
endcase
idp1 = (id + 1) % QENTRIES;
endfunction
 
function [`QBITS] idp2;
input [`QBITS] id;
case(id)
3'd0: idp2 = 3'd2;
3'd1: idp2 = 3'd3;
3'd2: idp2 = 3'd4;
3'd3: idp2 = 3'd5;
3'd4: idp2 = 3'd6;
3'd5: idp2 = 3'd7;
3'd6: idp2 = 3'd0;
3'd7: idp2 = 3'd1;
endcase
idp2 = (id + 2) % QENTRIES;
endfunction
 
function [`QBITS] idp3;
input [`QBITS] id;
case(id)
3'd0: idp3 = 3'd3;
3'd1: idp3 = 3'd4;
3'd2: idp3 = 3'd5;
3'd3: idp3 = 3'd6;
3'd4: idp3 = 3'd7;
3'd5: idp3 = 3'd0;
3'd6: idp3 = 3'd1;
3'd7: idp3 = 3'd2;
endcase
idp3 = (id + 3) % QENTRIES;
endfunction
 
function [`QBITS] idp4;
input [`QBITS] id;
case(id)
3'd0: idp4 = 3'd4;
3'd1: idp4 = 3'd5;
3'd2: idp4 = 3'd6;
3'd3: idp4 = 3'd7;
3'd4: idp4 = 3'd0;
3'd5: idp4 = 3'd1;
3'd6: idp4 = 3'd2;
3'd7: idp4 = 3'd3;
endcase
idp4 = (id + 4) % QENTRIES;
endfunction
 
function [`QBITS] idp5;
input [`QBITS] id;
case(id)
3'd0: idp5 = 3'd5;
3'd1: idp5 = 3'd6;
3'd2: idp5 = 3'd7;
3'd3: idp5 = 3'd0;
3'd4: idp5 = 3'd1;
3'd5: idp5 = 3'd2;
3'd6: idp5 = 3'd3;
3'd7: idp5 = 3'd4;
endcase
idp5 = (id + 5) % QENTRIES;
endfunction
 
function [`QBITS] idp6;
input [`QBITS] id;
case(id)
3'd0: idp6 = 3'd6;
3'd1: idp6 = 3'd7;
3'd2: idp6 = 3'd0;
3'd3: idp6 = 3'd1;
3'd4: idp6 = 3'd2;
3'd5: idp6 = 3'd3;
3'd6: idp6 = 3'd4;
3'd7: idp6 = 3'd5;
endcase
idp6 = (id + 6) % QENTRIES;
endfunction
 
function [`QBITS] idp7;
input [`QBITS] id;
case(id)
3'd0: idp7 = 3'd7;
3'd1: idp7 = 3'd0;
3'd2: idp7 = 3'd1;
3'd3: idp7 = 3'd2;
3'd4: idp7 = 3'd3;
3'd5: idp7 = 3'd4;
3'd6: idp7 = 3'd5;
3'd7: idp7 = 3'd6;
endcase
idp7 = (id + 7) % QENTRIES;
endfunction
 
function [`QBITS] idp8;
input [`QBITS] id;
idp8 = (id + 8) % QENTRIES;
endfunction
 
function [`QBITS] idp9;
input [`QBITS] id;
idp9 = (id + 9) % QENTRIES;
endfunction
 
function [`QBITS] idm1;
input [`QBITS] id;
case(id)
3'd0: idm1 = 3'd7;
3'd1: idm1 = 3'd0;
3'd2: idm1 = 3'd1;
3'd3: idm1 = 3'd2;
3'd4: idm1 = 3'd3;
3'd5: idm1 = 3'd4;
3'd6: idm1 = 3'd5;
3'd7: idm1 = 3'd6;
endcase
idm1 = (id - 1) % QENTRIES;
endfunction
 
`ifdef SUPPORT_SMT
2834,7 → 2791,7
endcase
else
fnSelect = 8'h00;
`LB,`LBU,`SB:
`LB,`LBU,`SB:
case(adr[2:0])
3'd0: fnSelect = 8'h01;
3'd1: fnSelect = 8'h02;
3208,6 → 3165,8
decoder8 iq5(.num({iqentry_tgt[5][8:7],iqentry_tgt[5][5:0]}), .out(iq5_out));
decoder8 iq6(.num({iqentry_tgt[6][8:7],iqentry_tgt[6][5:0]}), .out(iq6_out));
decoder8 iq7(.num({iqentry_tgt[7][8:7],iqentry_tgt[7][5:0]}), .out(iq7_out));
decoder8 iq8(.num({iqentry_tgt[8][8:7],iqentry_tgt[8][5:0]}), .out(iq8_out));
decoder8 iq9(.num({iqentry_tgt[9][8:7],iqentry_tgt[9][5:0]}), .out(iq9_out));
`else
decoder7 iq0(.num({iqentry_tgt[0][7],iqentry_tgt[0][5:0]}), .out(iq0_out));
decoder7 iq1(.num({iqentry_tgt[1][7],iqentry_tgt[1][5:0]}), .out(iq1_out));
3217,6 → 3176,8
decoder7 iq5(.num({iqentry_tgt[5][7],iqentry_tgt[5][5:0]}), .out(iq5_out));
decoder7 iq6(.num({iqentry_tgt[6][7],iqentry_tgt[6][5:0]}), .out(iq6_out));
decoder7 iq7(.num({iqentry_tgt[7][7],iqentry_tgt[7][5:0]}), .out(iq7_out));
decoder7 iq8(.num({iqentry_tgt[8][7],iqentry_tgt[8][5:0]}), .out(iq8_out));
decoder7 iq9(.num({iqentry_tgt[9][7],iqentry_tgt[9][5:0]}), .out(iq9_out));
/*
decoder6 iq0(.num({iqentry_tgt[0][5:0]}), .out(iq0_out));
decoder6 iq1(.num({iqentry_tgt[1][5:0]}), .out(iq1_out));
3275,7 → 3236,7
.we_i(we_o),
.adr_i(adr_o[15:0]),
.dat_i(dat_o[31:0]),
.hirq(hirq),
.freezePC(freezePC),
.regLR(regLR),
.thread_en(thread_en),
.insn0(insn0),
3354,7 → 3315,10
iqentry_4_livetarget[g] |
iqentry_5_livetarget[g] |
iqentry_6_livetarget[g] |
iqentry_7_livetarget[g];
iqentry_7_livetarget[g] |
iqentry_8_livetarget[g] |
iqentry_9_livetarget[g]
;
end
end
endgenerate
3366,14 → 3330,27
iqentry_4_livetarget = {PREGS {iqentry_v[4]}} & {PREGS {~iqentry_stomp[4] && iqentry_thrd[4]==branchmiss_thrd}} & iq4_out,
iqentry_5_livetarget = {PREGS {iqentry_v[5]}} & {PREGS {~iqentry_stomp[5] && iqentry_thrd[5]==branchmiss_thrd}} & iq5_out,
iqentry_6_livetarget = {PREGS {iqentry_v[6]}} & {PREGS {~iqentry_stomp[6] && iqentry_thrd[6]==branchmiss_thrd}} & iq6_out,
iqentry_7_livetarget = {PREGS {iqentry_v[7]}} & {PREGS {~iqentry_stomp[7] && iqentry_thrd[7]==branchmiss_thrd}} & iq7_out;
iqentry_7_livetarget = {PREGS {iqentry_v[7]}} & {PREGS {~iqentry_stomp[7] && iqentry_thrd[7]==branchmiss_thrd}} & iq7_out,
iqentry_8_livetarget = {PREGS {iqentry_v[8]}} & {PREGS {~iqentry_stomp[8] && iqentry_thrd[8]==branchmiss_thrd}} & iq8_out,
iqentry_9_livetarget = {PREGS {iqentry_v[9]}} & {PREGS {~iqentry_stomp[9] && iqentry_thrd[9]==branchmiss_thrd}} & iq9_out
;
 
//
// BRANCH-MISS LOGIC: latestID
//
// latestID is the instruction queue ID of the newest instruction (latest) that targets
// a particular register. looks a lot like scheduling logic, but in reverse.
//
//
// BRANCH-MISS LOGIC: latestID
//
// latestID is the instruction queue ID of the newest instruction (latest) that targets
// a particular register. looks a lot like scheduling logic, but in reverse.
//
always @*
for (n = 0; n < QENTRIES; n = n + 1) begin
iqentry_cumulative[n] = 0;
for (j = n; j < n + QENTRIES; j = j + 1) begin
if (missid==(j % QENTRIES))
for (k = n; k <= j; k = k + 1)
iqentry_cumulative[n] = iqentry_cumulative[n] | iqentry_livetarget[k % QENTRIES];
end
end
/*
assign iqentry_0_cumulative = (missid==3'd0) ? iqentry_0_livetarget :
(missid==3'd1) ? iqentry_0_livetarget |
iqentry_1_livetarget :
3412,28 → 3389,28
iqentry_7_livetarget :
{PREGS{1'b0}};
 
assign iqentry_1_cumulative = (missid==3'd1) ? iqentry_1_livetarget :
(missid==3'd2) ? iqentry_1_livetarget |
assign iqentry_1_cumulative = (missid==4'd1) ? iqentry_1_livetarget :
(missid==4'd2) ? iqentry_1_livetarget |
iqentry_2_livetarget :
(missid==3'd3) ? iqentry_1_livetarget |
(missid==4'd3) ? iqentry_1_livetarget |
iqentry_2_livetarget |
iqentry_3_livetarget :
(missid==3'd4) ? iqentry_1_livetarget |
(missid==4'd4) ? iqentry_1_livetarget |
iqentry_2_livetarget |
iqentry_3_livetarget |
iqentry_4_livetarget :
(missid==3'd5) ? iqentry_1_livetarget |
(missid==4'd5) ? iqentry_1_livetarget |
iqentry_2_livetarget |
iqentry_3_livetarget |
iqentry_4_livetarget |
iqentry_5_livetarget :
(missid==3'd6) ? iqentry_1_livetarget |
(missid==4'd6) ? iqentry_1_livetarget |
iqentry_2_livetarget |
iqentry_3_livetarget |
iqentry_4_livetarget |
iqentry_5_livetarget |
iqentry_6_livetarget :
(missid==3'd7) ? iqentry_1_livetarget |
(missid==4'd7) ? iqentry_1_livetarget |
iqentry_2_livetarget |
iqentry_3_livetarget |
iqentry_4_livetarget |
3440,7 → 3417,7
iqentry_5_livetarget |
iqentry_6_livetarget |
iqentry_7_livetarget :
(missid==3'd0) ? iqentry_1_livetarget |
(missid==4'd0) ? iqentry_1_livetarget |
iqentry_2_livetarget |
iqentry_3_livetarget |
iqentry_4_livetarget |
3450,28 → 3427,28
iqentry_0_livetarget :
{PREGS{1'b0}};
 
assign iqentry_2_cumulative = (missid==3'd2) ? iqentry_2_livetarget :
(missid==3'd3) ? iqentry_2_livetarget |
assign iqentry_2_cumulative = (missid==4'd2) ? iqentry_2_livetarget :
(missid==4'd3) ? iqentry_2_livetarget |
iqentry_3_livetarget :
(missid==3'd4) ? iqentry_2_livetarget |
(missid==4'd4) ? iqentry_2_livetarget |
iqentry_3_livetarget |
iqentry_4_livetarget :
(missid==3'd5) ? iqentry_2_livetarget |
(missid==4'd5) ? iqentry_2_livetarget |
iqentry_3_livetarget |
iqentry_4_livetarget |
iqentry_5_livetarget :
(missid==3'd6) ? iqentry_2_livetarget |
(missid==4'd6) ? iqentry_2_livetarget |
iqentry_3_livetarget |
iqentry_4_livetarget |
iqentry_5_livetarget |
iqentry_6_livetarget :
(missid==3'd7) ? iqentry_2_livetarget |
(missid==4'd7) ? iqentry_2_livetarget |
iqentry_3_livetarget |
iqentry_4_livetarget |
iqentry_5_livetarget |
iqentry_6_livetarget |
iqentry_7_livetarget :
(missid==3'd0) ? iqentry_2_livetarget |
(missid==4'd0) ? iqentry_2_livetarget |
iqentry_3_livetarget |
iqentry_4_livetarget |
iqentry_5_livetarget |
3478,7 → 3455,7
iqentry_6_livetarget |
iqentry_7_livetarget |
iqentry_0_livetarget :
(missid==3'd1) ? iqentry_2_livetarget |
(missid==4'd1) ? iqentry_2_livetarget |
iqentry_3_livetarget |
iqentry_4_livetarget |
iqentry_5_livetarget |
3488,28 → 3465,28
iqentry_1_livetarget :
{PREGS{1'b0}};
 
assign iqentry_3_cumulative = (missid==3'd3) ? iqentry_3_livetarget :
(missid==3'd4) ? iqentry_3_livetarget |
assign iqentry_3_cumulative = (missid==4'd3) ? iqentry_3_livetarget :
(missid==4'd4) ? iqentry_3_livetarget |
iqentry_4_livetarget :
(missid==3'd5) ? iqentry_3_livetarget |
(missid==4'd5) ? iqentry_3_livetarget |
iqentry_4_livetarget |
iqentry_5_livetarget :
(missid==3'd6) ? iqentry_3_livetarget |
(missid==4'd6) ? iqentry_3_livetarget |
iqentry_4_livetarget |
iqentry_5_livetarget |
iqentry_6_livetarget :
(missid==3'd7) ? iqentry_3_livetarget |
(missid==4'd7) ? iqentry_3_livetarget |
iqentry_4_livetarget |
iqentry_5_livetarget |
iqentry_6_livetarget |
iqentry_7_livetarget :
(missid==3'd0) ? iqentry_3_livetarget |
(missid==4'd0) ? iqentry_3_livetarget |
iqentry_4_livetarget |
iqentry_5_livetarget |
iqentry_6_livetarget |
iqentry_7_livetarget |
iqentry_0_livetarget :
(missid==3'd1) ? iqentry_3_livetarget |
(missid==4'd1) ? iqentry_3_livetarget |
iqentry_4_livetarget |
iqentry_5_livetarget |
iqentry_6_livetarget |
3516,7 → 3493,7
iqentry_7_livetarget |
iqentry_0_livetarget |
iqentry_1_livetarget :
(missid==3'd2) ? iqentry_3_livetarget |
(missid==4'd2) ? iqentry_3_livetarget |
iqentry_4_livetarget |
iqentry_5_livetarget |
iqentry_6_livetarget |
3526,28 → 3503,28
iqentry_2_livetarget :
{PREGS{1'b0}};
 
assign iqentry_4_cumulative = (missid==3'd4) ? iqentry_4_livetarget :
(missid==3'd5) ? iqentry_4_livetarget |
assign iqentry_4_cumulative = (missid==4'd4) ? iqentry_4_livetarget :
(missid==4'd5) ? iqentry_4_livetarget |
iqentry_5_livetarget :
(missid==3'd6) ? iqentry_4_livetarget |
(missid==4'd6) ? iqentry_4_livetarget |
iqentry_5_livetarget |
iqentry_6_livetarget :
(missid==3'd7) ? iqentry_4_livetarget |
(missid==4'd7) ? iqentry_4_livetarget |
iqentry_5_livetarget |
iqentry_6_livetarget |
iqentry_7_livetarget :
(missid==3'd0) ? iqentry_4_livetarget |
(missid==4'd0) ? iqentry_4_livetarget |
iqentry_5_livetarget |
iqentry_6_livetarget |
iqentry_7_livetarget |
iqentry_0_livetarget :
(missid==3'd1) ? iqentry_4_livetarget |
(missid==4'd1) ? iqentry_4_livetarget |
iqentry_5_livetarget |
iqentry_6_livetarget |
iqentry_7_livetarget |
iqentry_0_livetarget |
iqentry_1_livetarget :
(missid==3'd2) ? iqentry_4_livetarget |
(missid==4'd2) ? iqentry_4_livetarget |
iqentry_5_livetarget |
iqentry_6_livetarget |
iqentry_7_livetarget |
3554,7 → 3531,7
iqentry_0_livetarget |
iqentry_1_livetarget |
iqentry_2_livetarget :
(missid==3'd3) ? iqentry_4_livetarget |
(missid==4'd3) ? iqentry_4_livetarget |
iqentry_5_livetarget |
iqentry_6_livetarget |
iqentry_7_livetarget |
3564,28 → 3541,28
iqentry_3_livetarget :
{PREGS{1'b0}};
 
assign iqentry_5_cumulative = (missid==3'd5) ? iqentry_5_livetarget :
(missid==3'd6) ? iqentry_5_livetarget |
assign iqentry_5_cumulative = (missid==4'd5) ? iqentry_5_livetarget :
(missid==4'd6) ? iqentry_5_livetarget |
iqentry_6_livetarget :
(missid==3'd7) ? iqentry_5_livetarget |
(missid==4'd7) ? iqentry_5_livetarget |
iqentry_6_livetarget |
iqentry_7_livetarget :
(missid==3'd0) ? iqentry_5_livetarget |
(missid==4'd0) ? iqentry_5_livetarget |
iqentry_6_livetarget |
iqentry_7_livetarget |
iqentry_0_livetarget :
(missid==3'd1) ? iqentry_5_livetarget |
(missid==4'd1) ? iqentry_5_livetarget |
iqentry_6_livetarget |
iqentry_7_livetarget |
iqentry_0_livetarget |
iqentry_1_livetarget :
(missid==3'd2) ? iqentry_5_livetarget |
(missid==4'd2) ? iqentry_5_livetarget |
iqentry_6_livetarget |
iqentry_7_livetarget |
iqentry_0_livetarget |
iqentry_1_livetarget |
iqentry_2_livetarget :
(missid==3'd3) ? iqentry_5_livetarget |
(missid==4'd3) ? iqentry_5_livetarget |
iqentry_6_livetarget |
iqentry_7_livetarget |
iqentry_0_livetarget |
3592,7 → 3569,7
iqentry_1_livetarget |
iqentry_2_livetarget |
iqentry_3_livetarget :
(missid==3'd4) ? iqentry_5_livetarget |
(missid==4'd4) ? iqentry_5_livetarget |
iqentry_6_livetarget |
iqentry_7_livetarget |
iqentry_0_livetarget |
3601,28 → 3578,28
iqentry_3_livetarget |
iqentry_4_livetarget :
{PREGS{1'b0}};
assign iqentry_6_cumulative = (missid==3'd6) ? iqentry_6_livetarget :
(missid==3'd7) ? iqentry_6_livetarget |
assign iqentry_6_cumulative = (missid==4'd6) ? iqentry_6_livetarget :
(missid==4'd7) ? iqentry_6_livetarget |
iqentry_7_livetarget :
(missid==3'd0) ? iqentry_6_livetarget |
(missid==4'd0) ? iqentry_6_livetarget |
iqentry_7_livetarget |
iqentry_0_livetarget :
(missid==3'd1) ? iqentry_6_livetarget |
(missid==4'd1) ? iqentry_6_livetarget |
iqentry_7_livetarget |
iqentry_0_livetarget |
iqentry_1_livetarget :
(missid==3'd2) ? iqentry_6_livetarget |
(missid==4'd2) ? iqentry_6_livetarget |
iqentry_7_livetarget |
iqentry_0_livetarget |
iqentry_1_livetarget |
iqentry_2_livetarget :
(missid==3'd3) ? iqentry_6_livetarget |
(missid==4'd3) ? iqentry_6_livetarget |
iqentry_7_livetarget |
iqentry_0_livetarget |
iqentry_1_livetarget |
iqentry_2_livetarget |
iqentry_3_livetarget :
(missid==3'd4) ? iqentry_6_livetarget |
(missid==4'd4) ? iqentry_6_livetarget |
iqentry_7_livetarget |
iqentry_0_livetarget |
iqentry_1_livetarget |
3629,7 → 3606,7
iqentry_2_livetarget |
iqentry_3_livetarget |
iqentry_4_livetarget :
(missid==3'd5) ? iqentry_6_livetarget |
(missid==4'd5) ? iqentry_6_livetarget |
iqentry_7_livetarget |
iqentry_0_livetarget |
iqentry_1_livetarget |
3639,28 → 3616,28
iqentry_5_livetarget :
{PREGS{1'b0}};
 
assign iqentry_7_cumulative = (missid==3'd7) ? iqentry_7_livetarget :
(missid==3'd0) ? iqentry_7_livetarget |
assign iqentry_7_cumulative = (missid==4'd7) ? iqentry_7_livetarget :
(missid==4'd0) ? iqentry_7_livetarget |
iqentry_0_livetarget :
(missid==3'd1) ? iqentry_7_livetarget |
(missid==4'd1) ? iqentry_7_livetarget |
iqentry_0_livetarget |
iqentry_1_livetarget :
(missid==3'd2) ? iqentry_7_livetarget |
(missid==4'd2) ? iqentry_7_livetarget |
iqentry_0_livetarget |
iqentry_1_livetarget |
iqentry_2_livetarget :
(missid==3'd3) ? iqentry_7_livetarget |
(missid==4'd3) ? iqentry_7_livetarget |
iqentry_0_livetarget |
iqentry_1_livetarget |
iqentry_2_livetarget |
iqentry_3_livetarget :
(missid==3'd4) ? iqentry_7_livetarget |
(missid==4'd4) ? iqentry_7_livetarget |
iqentry_0_livetarget |
iqentry_1_livetarget |
iqentry_2_livetarget |
iqentry_3_livetarget |
iqentry_4_livetarget :
(missid==3'd5) ? iqentry_7_livetarget |
(missid==4'd5) ? iqentry_7_livetarget |
iqentry_0_livetarget |
iqentry_1_livetarget |
iqentry_2_livetarget |
3667,7 → 3644,7
iqentry_3_livetarget |
iqentry_4_livetarget |
iqentry_5_livetarget :
(missid==3'd6) ? iqentry_7_livetarget |
(missid==4'd6) ? iqentry_7_livetarget |
iqentry_0_livetarget |
iqentry_1_livetarget |
iqentry_2_livetarget |
3676,40 → 3653,49
iqentry_5_livetarget |
iqentry_6_livetarget :
{PREGS{1'b0}};
*/
assign iqentry_0_latestID = (missid == 4'd0 || ((iqentry_livetarget[0] & iqentry_cumulative[1]) == {PREGS{1'b0}}))
? iqentry_livetarget[0]
: {PREGS{1'b0}};
 
assign iqentry_0_latestID = (missid == 3'd0 || ((iqentry_0_livetarget & iqentry_1_cumulative) == {PREGS{1'b0}}))
? iqentry_0_livetarget
assign iqentry_1_latestID = (missid == 4'd1 || ((iqentry_livetarget[1] & iqentry_cumulative[2]) == {PREGS{1'b0}}))
? iqentry_livetarget[1]
: {PREGS{1'b0}};
 
assign iqentry_1_latestID = (missid == 3'd1 || ((iqentry_1_livetarget & iqentry_2_cumulative) == {PREGS{1'b0}}))
? iqentry_1_livetarget
assign iqentry_2_latestID = (missid == 4'd2 || ((iqentry_livetarget[2] & iqentry_cumulative[3]) == {PREGS{1'b0}}))
? iqentry_livetarget[2]
: {PREGS{1'b0}};
 
assign iqentry_2_latestID = (missid == 3'd2 || ((iqentry_2_livetarget & iqentry_3_cumulative) == {PREGS{1'b0}}))
? iqentry_2_livetarget
assign iqentry_3_latestID = (missid == 4'd3 || ((iqentry_livetarget[3] & iqentry_cumulative[4]) == {PREGS{1'b0}}))
? iqentry_livetarget[3]
: {PREGS{1'b0}};
 
assign iqentry_3_latestID = (missid == 3'd3 || ((iqentry_3_livetarget & iqentry_4_cumulative) == {PREGS{1'b0}}))
? iqentry_3_livetarget
assign iqentry_4_latestID = (missid == 4'd4 || ((iqentry_livetarget[4] & iqentry_cumulative[5]) == {PREGS{1'b0}}))
? iqentry_livetarget[4]
: {PREGS{1'b0}};
 
assign iqentry_4_latestID = (missid == 3'd4 || ((iqentry_4_livetarget & iqentry_5_cumulative) == {PREGS{1'b0}}))
? iqentry_4_livetarget
assign iqentry_5_latestID = (missid == 4'd5 || ((iqentry_livetarget[5] & iqentry_cumulative[6]) == {PREGS{1'b0}}))
? iqentry_livetarget[5]
: {PREGS{1'b0}};
 
assign iqentry_5_latestID = (missid == 3'd5 || ((iqentry_5_livetarget & iqentry_6_cumulative) == {PREGS{1'b0}}))
? iqentry_5_livetarget
assign iqentry_6_latestID = (missid == 4'd6 || ((iqentry_livetarget[6] & iqentry_cumulative[7]) == {PREGS{1'b0}}))
? iqentry_livetarget[6]
: {PREGS{1'b0}};
 
assign iqentry_6_latestID = (missid == 3'd6 || ((iqentry_6_livetarget & iqentry_7_cumulative) == {PREGS{1'b0}}))
? iqentry_6_livetarget
assign iqentry_7_latestID = (missid == 4'd7 || ((iqentry_livetarget[7] & iqentry_cumulative[8]) == {PREGS{1'b0}}))
? iqentry_livetarget[7]
: {PREGS{1'b0}};
 
assign iqentry_7_latestID = (missid == 3'd7 || ((iqentry_7_livetarget & iqentry_0_cumulative) == {PREGS{1'b0}}))
? iqentry_7_livetarget
assign iqentry_8_latestID = (missid == 4'd8 || ((iqentry_livetarget[8] & iqentry_cumulative[9]) == {PREGS{1'b0}}))
? iqentry_livetarget[8]
: {PREGS{1'b0}};
 
assign iqentry_source[0] = | iqentry_0_latestID,
assign iqentry_9_latestID = (missid == 4'd9 || ((iqentry_livetarget[9] & iqentry_cumulative[0]) == {PREGS{1'b0}}))
? iqentry_livetarget[9]
: {PREGS{1'b0}};
 
assign
iqentry_source[0] = | iqentry_0_latestID,
iqentry_source[1] = | iqentry_1_latestID,
iqentry_source[2] = | iqentry_2_latestID,
iqentry_source[3] = | iqentry_3_latestID,
3716,7 → 3702,10
iqentry_source[4] = | iqentry_4_latestID,
iqentry_source[5] = | iqentry_5_latestID,
iqentry_source[6] = | iqentry_6_latestID,
iqentry_source[7] = | iqentry_7_latestID;
iqentry_source[7] = | iqentry_7_latestID,
iqentry_source[8] = | iqentry_8_latestID,
iqentry_source[9] = | iqentry_9_latestID
;
 
 
reg vqueued2;
3777,7 → 3766,8
&& iqentry_iv[g]
&& (iqentry_mem[g] ? !iqentry_agen[g] : 1'b1);
 
assign could_issueid[g] = iqentry_v[g] && !iqentry_iv[g];
assign could_issueid[g] = (iqentry_v[g])// || (g==tail0 && canq1))// || (g==tail1 && canq2))
&& !iqentry_iv[g];
// && (iqentry_a1_v[g]
// || (iqentry_a1_s[g] == alu0_sourceid && alu0_dataready)
// || (iqentry_a1_s[g] == alu1_sourceid && alu1_dataready));
3802,6 → 3792,8
assign heads[5] = head5;
assign heads[6] = head6;
assign heads[7] = head7;
assign heads[8] = head8;
assign heads[9] = head9;
 
always @*
begin
4368,19 → 4360,23
reg [`QBITS] nid0;
always @*
if (iqentry_thrd[1]==iqentry_thrd[0])
nid0 = 3'd1;
nid0 = 4'd1;
else if (iqentry_thrd[2]==iqentry_thrd[0])
nid0 = 3'd2;
nid0 = 4'd2;
else if (iqentry_thrd[3]==iqentry_thrd[0])
nid0 = 3'd3;
nid0 = 4'd3;
else if (iqentry_thrd[4]==iqentry_thrd[0])
nid0 = 3'd4;
nid0 = 4'd4;
else if (iqentry_thrd[5]==iqentry_thrd[0])
nid0 = 3'd5;
nid0 = 4'd5;
else if (iqentry_thrd[6]==iqentry_thrd[0])
nid0 = 3'd6;
nid0 = 4'd6;
else if (iqentry_thrd[7]==iqentry_thrd[0])
nid0 = 3'd7;
nid0 = 4'd7;
else if (iqentry_thrd[8]==iqentry_thrd[0])
nid0 = 4'd8;
else if (iqentry_thrd[9]==iqentry_thrd[0])
nid0 = 4'd9;
else
nid0 = 3'd0;
 
4387,136 → 4383,210
reg [`QBITS] nid1;
always @*
if (iqentry_thrd[2]==iqentry_thrd[1])
nid1 = 3'd2;
nid1 = 4'd2;
else if (iqentry_thrd[3]==iqentry_thrd[1])
nid1 = 3'd3;
nid1 = 4'd3;
else if (iqentry_thrd[4]==iqentry_thrd[1])
nid1 = 3'd4;
nid1 = 4'd4;
else if (iqentry_thrd[5]==iqentry_thrd[1])
nid1 = 3'd5;
nid1 = 4'd5;
else if (iqentry_thrd[6]==iqentry_thrd[1])
nid1 = 3'd6;
nid1 = 4'd6;
else if (iqentry_thrd[7]==iqentry_thrd[1])
nid1 = 3'd7;
nid1 = 4'd7;
else if (iqentry_thrd[8]==iqentry_thrd[1])
nid1 = 4'd8;
else if (iqentry_thrd[9]==iqentry_thrd[1])
nid1 = 4'd9;
else if (iqentry_thrd[0]==iqentry_thrd[1])
nid1 = 3'd0;
nid1 = 4'd0;
else
nid1 = 3'd1;
nid1 = 4'd1;
 
reg [`QBITS] nid2;
always @*
if (iqentry_thrd[3]==iqentry_thrd[2])
nid2 = 3'd3;
nid2 = 4'd3;
else if (iqentry_thrd[4]==iqentry_thrd[2])
nid2 = 3'd4;
nid2 = 4'd4;
else if (iqentry_thrd[5]==iqentry_thrd[2])
nid2 = 3'd5;
nid2 = 4'd5;
else if (iqentry_thrd[6]==iqentry_thrd[2])
nid2 = 3'd6;
nid2 = 4'd6;
else if (iqentry_thrd[7]==iqentry_thrd[2])
nid2 = 3'd7;
nid2 = 4'd7;
else if (iqentry_thrd[8]==iqentry_thrd[2])
nid2 = 4'd8;
else if (iqentry_thrd[9]==iqentry_thrd[2])
nid2 = 4'd9;
else if (iqentry_thrd[0]==iqentry_thrd[2])
nid2 = 3'd0;
nid2 = 4'd0;
else if (iqentry_thrd[1]==iqentry_thrd[2])
nid2 = 3'd1;
nid2 = 4'd1;
else
nid2 = 3'd2;
nid2 = 4'd2;
 
reg [`QBITS] nid3;
always @*
if (iqentry_thrd[4]==iqentry_thrd[3])
nid3 = 3'd4;
nid3 = 4'd4;
else if (iqentry_thrd[5]==iqentry_thrd[3])
nid3 = 3'd5;
nid3 = 4'd5;
else if (iqentry_thrd[6]==iqentry_thrd[3])
nid3 = 3'd6;
nid3 = 4'd6;
else if (iqentry_thrd[7]==iqentry_thrd[3])
nid3 = 3'd7;
nid3 = 4'd7;
else if (iqentry_thrd[8]==iqentry_thrd[3])
nid3 = 4'd8;
else if (iqentry_thrd[9]==iqentry_thrd[3])
nid3 = 4'd9;
else if (iqentry_thrd[0]==iqentry_thrd[3])
nid3 = 3'd0;
nid3 = 4'd0;
else if (iqentry_thrd[1]==iqentry_thrd[3])
nid3 = 3'd1;
nid3 = 4'd1;
else if (iqentry_thrd[2]==iqentry_thrd[3])
nid3 = 3'd2;
nid3 = 4'd2;
else
nid3 = 3'd3;
nid3 = 4'd3;
 
reg [`QBITS] nid4;
always @*
if (iqentry_thrd[5]==iqentry_thrd[4])
nid4 = 3'd5;
nid4 = 4'd5;
else if (iqentry_thrd[6]==iqentry_thrd[4])
nid4 = 3'd6;
nid4 = 4'd6;
else if (iqentry_thrd[7]==iqentry_thrd[4])
nid4 = 3'd7;
nid4 = 4'd7;
else if (iqentry_thrd[8]==iqentry_thrd[4])
nid4 = 4'd8;
else if (iqentry_thrd[9]==iqentry_thrd[4])
nid4 = 4'd9;
else if (iqentry_thrd[0]==iqentry_thrd[4])
nid4 = 3'd0;
nid4 = 4'd0;
else if (iqentry_thrd[1]==iqentry_thrd[4])
nid4 = 3'd1;
nid4 = 4'd1;
else if (iqentry_thrd[2]==iqentry_thrd[4])
nid4 = 3'd2;
nid4 = 4'd2;
else if (iqentry_thrd[3]==iqentry_thrd[4])
nid4 = 3'd3;
nid4 = 4'd3;
else
nid4 = 3'd4;
nid4 = 4'd4;
 
reg [`QBITS] nid5;
always @*
if (iqentry_thrd[6]==iqentry_thrd[5])
nid5 = 3'd6;
nid5 = 4'd6;
else if (iqentry_thrd[7]==iqentry_thrd[5])
nid5 = 3'd7;
nid5 = 4'd7;
else if (iqentry_thrd[8]==iqentry_thrd[5])
nid5 = 4'd8;
else if (iqentry_thrd[9]==iqentry_thrd[5])
nid5 = 4'd9;
else if (iqentry_thrd[0]==iqentry_thrd[5])
nid5 = 3'd0;
nid5 = 4'd0;
else if (iqentry_thrd[1]==iqentry_thrd[5])
nid5 = 3'd1;
nid5 = 4'd1;
else if (iqentry_thrd[2]==iqentry_thrd[5])
nid5 = 3'd2;
nid5 = 4'd2;
else if (iqentry_thrd[3]==iqentry_thrd[5])
nid5 = 3'd3;
nid5 = 4'd3;
else if (iqentry_thrd[4]==iqentry_thrd[5])
nid5 = 3'd4;
nid5 = 4'd4;
else
nid5 = 3'd5;
nid5 = 4'd5;
 
reg [`QBITS] nid6;
always @*
if (iqentry_thrd[7]==iqentry_thrd[6])
nid6 = 3'd7;
nid6 = 4'd7;
else if (iqentry_thrd[8]==iqentry_thrd[6])
nid6 = 4'd8;
else if (iqentry_thrd[9]==iqentry_thrd[6])
nid6 = 4'd9;
else if (iqentry_thrd[0]==iqentry_thrd[6])
nid6 = 3'd0;
nid6 = 4'd0;
else if (iqentry_thrd[1]==iqentry_thrd[6])
nid6 = 3'd1;
nid6 = 4'd1;
else if (iqentry_thrd[2]==iqentry_thrd[6])
nid6 = 3'd2;
nid6 = 4'd2;
else if (iqentry_thrd[3]==iqentry_thrd[6])
nid6 = 3'd3;
nid6 = 4'd3;
else if (iqentry_thrd[4]==iqentry_thrd[6])
nid6 = 3'd4;
nid6 = 4'd4;
else if (iqentry_thrd[5]==iqentry_thrd[6])
nid6 = 3'd5;
nid6 = 4'd5;
else
nid6 = 3'd6;
nid6 = 4'd6;
 
reg [`QBITS] nid7;
always @*
if (iqentry_thrd[0]==iqentry_thrd[7])
nid7 = 3'd0;
if (iqentry_thrd[8]==iqentry_thrd[7])
nid7 = 4'd8;
else if (iqentry_thrd[9]==iqentry_thrd[7])
nid7 = 4'd9;
else if (iqentry_thrd[0]==iqentry_thrd[7])
nid7 = 4'd0;
else if (iqentry_thrd[1]==iqentry_thrd[7])
nid7 = 3'd1;
nid7 = 4'd1;
else if (iqentry_thrd[2]==iqentry_thrd[7])
nid7 = 3'd2;
nid7 = 4'd2;
else if (iqentry_thrd[3]==iqentry_thrd[7])
nid7 = 3'd3;
nid7 = 4'd3;
else if (iqentry_thrd[4]==iqentry_thrd[7])
nid7 = 3'd4;
nid7 = 4'd4;
else if (iqentry_thrd[5]==iqentry_thrd[7])
nid7 = 3'd5;
nid7 = 4'd5;
else if (iqentry_thrd[6]==iqentry_thrd[7])
nid7 = 3'd6;
nid7 = 4'd6;
else
nid7 = 3'd7;
nid7 = 4'd7;
 
reg [`QBITS] nid8;
always @*
if (iqentry_thrd[9]==iqentry_thrd[8])
nid8 = 4'd9;
else if (iqentry_thrd[0]==iqentry_thrd[8])
nid8 = 4'd0;
else if (iqentry_thrd[1]==iqentry_thrd[8])
nid8 = 4'd1;
else if (iqentry_thrd[2]==iqentry_thrd[8])
nid8 = 4'd2;
else if (iqentry_thrd[3]==iqentry_thrd[8])
nid8 = 4'd3;
else if (iqentry_thrd[4]==iqentry_thrd[8])
nid8 = 4'd4;
else if (iqentry_thrd[5]==iqentry_thrd[8])
nid8 = 4'd5;
else if (iqentry_thrd[6]==iqentry_thrd[8])
nid8 = 4'd6;
else if (iqentry_thrd[7]==iqentry_thrd[8])
nid8 = 4'd7;
else
nid8 = 4'd8;
 
reg [`QBITS] nid9;
always @*
if (iqentry_thrd[0]==iqentry_thrd[9])
nid9 = 4'd0;
else if (iqentry_thrd[1]==iqentry_thrd[9])
nid9 = 4'd1;
else if (iqentry_thrd[2]==iqentry_thrd[9])
nid9 = 4'd2;
else if (iqentry_thrd[3]==iqentry_thrd[9])
nid9 = 4'd3;
else if (iqentry_thrd[4]==iqentry_thrd[9])
nid9 = 4'd4;
else if (iqentry_thrd[5]==iqentry_thrd[9])
nid9 = 4'd5;
else if (iqentry_thrd[6]==iqentry_thrd[9])
nid9 = 4'd6;
else if (iqentry_thrd[7]==iqentry_thrd[9])
nid9 = 4'd7;
else if (iqentry_thrd[8]==iqentry_thrd[9])
nid9 = 4'd8;
else
nid9 = 4'd9;
 
// Search the queue for the next entry on the same thread.
reg [`QBITS] nid;
always @*
4534,6 → 4604,10
nid = idp6(fcu_id);
else if (iqentry_thrd[idp7(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
nid = idp7(fcu_id);
else if (iqentry_thrd[idp8(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
nid = idp8(fcu_id);
else if (iqentry_thrd[idp9(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
nid = idp9(fcu_id);
else
nid = fcu_id;
 
4546,6 → 4620,8
assign nextqd[5] = iqentry_sn[nid5] > iqentry_sn[5] || iqentry_v[5];
assign nextqd[6] = iqentry_sn[nid6] > iqentry_sn[6] || iqentry_v[6];
assign nextqd[7] = iqentry_sn[nid7] > iqentry_sn[7] || iqentry_v[7];
assign nextqd[8] = iqentry_sn[nid8] > iqentry_sn[8] || iqentry_v[8];
assign nextqd[9] = iqentry_sn[nid9] > iqentry_sn[9] || iqentry_v[9];
 
//assign nextqd = 8'hFF;
 
4695,8 → 4771,8
// ... and no preceding instruction is ready to go
//&& ~iqentry_memready[head0]
// ... and there is no address-overlap with any preceding instruction
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|| (iqentry_a1_v[head0] && iqentry_a1[head1][AMSB:3] != iqentry_a1[head0][AMSB:3]))
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0]) || iqentry_done[head0]
|| (iqentry_a1_v[head0] && (iqentry_a1[head1][AMSB:3] != iqentry_a1[head0][AMSB:3] || iqentry_out[head0] || iqentry_done[head0])))
// ... if a release, any prior memory ops must be done before this one
&& (iqentry_rl[head1] ? iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0] : 1'b1)
// ... if a preivous op has the aquire bit set
4713,10 → 4789,10
//&& ~iqentry_memready[head0]
//&& ~iqentry_memready[head1]
// ... and there is no address-overlap with any preceding instruction
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|| (iqentry_a1_v[head0] && iqentry_a1[head2][AMSB:3] != iqentry_a1[head0][AMSB:3]))
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|| (iqentry_a1_v[head1] && iqentry_a1[head2][AMSB:3] != iqentry_a1[head1][AMSB:3]))
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0]) || iqentry_done[head0]
|| (iqentry_a1_v[head0] && (iqentry_a1[head2][AMSB:3] != iqentry_a1[head0][AMSB:3] || iqentry_out[head0] || iqentry_done[head0])))
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1]) || iqentry_done[head1]
|| (iqentry_a1_v[head1] && (iqentry_a1[head2][AMSB:3] != iqentry_a1[head1][AMSB:3] || iqentry_out[head1] || iqentry_done[head1])))
// ... if a release, any prior memory ops must be done before this one
&& (iqentry_rl[head2] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
4741,12 → 4817,12
//&& ~iqentry_memready[head1]
//&& ~iqentry_memready[head2]
// ... and there is no address-overlap with any preceding instruction
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|| (iqentry_a1_v[head0] && iqentry_a1[head3][AMSB:3] != iqentry_a1[head0][AMSB:3]))
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|| (iqentry_a1_v[head1] && iqentry_a1[head3][AMSB:3] != iqentry_a1[head1][AMSB:3]))
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2])
|| (iqentry_a1_v[head2] && iqentry_a1[head3][AMSB:3] != iqentry_a1[head2][AMSB:3]))
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0]) || iqentry_done[head0]
|| (iqentry_a1_v[head0] && (iqentry_a1[head3][AMSB:3] != iqentry_a1[head0][AMSB:3] || iqentry_out[head0] || iqentry_done[head0])))
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1]) || iqentry_done[head1]
|| (iqentry_a1_v[head1] && (iqentry_a1[head3][AMSB:3] != iqentry_a1[head1][AMSB:3] || iqentry_out[head1] || iqentry_done[head1])))
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2]) || iqentry_done[head2]
|| (iqentry_a1_v[head2] && (iqentry_a1[head3][AMSB:3] != iqentry_a1[head2][AMSB:3] || iqentry_out[head2] || iqentry_done[head2])))
// ... if a release, any prior memory ops must be done before this one
&& (iqentry_rl[head3] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
4783,14 → 4859,14
//&& ~iqentry_memready[head2]
//&& ~iqentry_memready[head3]
// ... and there is no address-overlap with any preceding instruction
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|| (iqentry_a1_v[head0] && iqentry_a1[head4][AMSB:3] != iqentry_a1[head0][AMSB:3]))
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|| (iqentry_a1_v[head1] && iqentry_a1[head4][AMSB:3] != iqentry_a1[head1][AMSB:3]))
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2])
|| (iqentry_a1_v[head2] && iqentry_a1[head4][AMSB:3] != iqentry_a1[head2][AMSB:3]))
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3])
|| (iqentry_a1_v[head3] && iqentry_a1[head4][AMSB:3] != iqentry_a1[head3][AMSB:3]))
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0]) || iqentry_done[head0]
|| (iqentry_a1_v[head0] && (iqentry_a1[head4][AMSB:3] != iqentry_a1[head0][AMSB:3] || iqentry_out[head0] || iqentry_done[head0])))
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1]) || iqentry_done[head1]
|| (iqentry_a1_v[head1] && (iqentry_a1[head4][AMSB:3] != iqentry_a1[head1][AMSB:3] || iqentry_out[head1] || iqentry_done[head1])))
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2]) || iqentry_done[head2]
|| (iqentry_a1_v[head2] && (iqentry_a1[head4][AMSB:3] != iqentry_a1[head2][AMSB:3] || iqentry_out[head2] || iqentry_done[head2])))
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3]) || iqentry_done[head3]
|| (iqentry_a1_v[head3] && (iqentry_a1[head4][AMSB:3] != iqentry_a1[head3][AMSB:3] || iqentry_out[head3] || iqentry_done[head3])))
// ... if a release, any prior memory ops must be done before this one
&& (iqentry_rl[head4] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
4841,16 → 4917,16
//&& ~iqentry_memready[head3]
//&& ~iqentry_memready[head4]
// ... and there is no address-overlap with any preceding instruction
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|| (iqentry_a1_v[head0] && iqentry_a1[head5][AMSB:3] != iqentry_a1[head0][AMSB:3]))
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|| (iqentry_a1_v[head1] && iqentry_a1[head5][AMSB:3] != iqentry_a1[head1][AMSB:3]))
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2])
|| (iqentry_a1_v[head2] && iqentry_a1[head5][AMSB:3] != iqentry_a1[head2][AMSB:3]))
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3])
|| (iqentry_a1_v[head3] && iqentry_a1[head5][AMSB:3] != iqentry_a1[head3][AMSB:3]))
&& (!iqentry_mem[head4] || (iqentry_agen[head4] & iqentry_out[head4])
|| (iqentry_a1_v[head4] && iqentry_a1[head5][AMSB:3] != iqentry_a1[head4][AMSB:3]))
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0]) || iqentry_done[head0]
|| (iqentry_a1_v[head0] && (iqentry_a1[head5][AMSB:3] != iqentry_a1[head0][AMSB:3] || iqentry_out[head0] || iqentry_done[head0])))
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1]) || iqentry_done[head1]
|| (iqentry_a1_v[head1] && (iqentry_a1[head5][AMSB:3] != iqentry_a1[head1][AMSB:3] || iqentry_out[head1] || iqentry_done[head1])))
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2]) || iqentry_done[head2]
|| (iqentry_a1_v[head2] && (iqentry_a1[head5][AMSB:3] != iqentry_a1[head2][AMSB:3] || iqentry_out[head2] || iqentry_done[head2])))
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3]) || iqentry_done[head3]
|| (iqentry_a1_v[head3] && (iqentry_a1[head5][AMSB:3] != iqentry_a1[head3][AMSB:3] || iqentry_out[head3] || iqentry_done[head3])))
&& (!iqentry_mem[head4] || (iqentry_agen[head4] & iqentry_out[head4]) || iqentry_done[head4]
|| (iqentry_a1_v[head4] && (iqentry_a1[head5][AMSB:3] != iqentry_a1[head4][AMSB:3] || iqentry_out[head4] || iqentry_done[head4])))
// ... if a release, any prior memory ops must be done before this one
&& (iqentry_rl[head5] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
4918,18 → 4994,18
//&& ~iqentry_memready[head4]
//&& ~iqentry_memready[head5]
// ... and there is no address-overlap with any preceding instruction
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|| (iqentry_a1_v[head0] && iqentry_a1[head6][AMSB:3] != iqentry_a1[head0][AMSB:3]))
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|| (iqentry_a1_v[head1] && iqentry_a1[head6][AMSB:3] != iqentry_a1[head1][AMSB:3]))
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2])
|| (iqentry_a1_v[head2] && iqentry_a1[head6][AMSB:3] != iqentry_a1[head2][AMSB:3]))
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3])
|| (iqentry_a1_v[head3] && iqentry_a1[head6][AMSB:3] != iqentry_a1[head3][AMSB:3]))
&& (!iqentry_mem[head4] || (iqentry_agen[head4] & iqentry_out[head4])
|| (iqentry_a1_v[head4] && iqentry_a1[head6][AMSB:3] != iqentry_a1[head4][AMSB:3]))
&& (!iqentry_mem[head5] || (iqentry_agen[head5] & iqentry_out[head5])
|| (iqentry_a1_v[head5] && iqentry_a1[head6][AMSB:3] != iqentry_a1[head5][AMSB:3]))
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0]) || iqentry_done[head0]
|| (iqentry_a1_v[head0] && (iqentry_a1[head6][AMSB:3] != iqentry_a1[head0][AMSB:3] || iqentry_out[head0] || iqentry_done[head0])))
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1]) || iqentry_done[head1]
|| (iqentry_a1_v[head1] && (iqentry_a1[head6][AMSB:3] != iqentry_a1[head1][AMSB:3] || iqentry_out[head1] || iqentry_done[head1])))
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2]) || iqentry_done[head2]
|| (iqentry_a1_v[head2] && (iqentry_a1[head6][AMSB:3] != iqentry_a1[head2][AMSB:3] || iqentry_out[head2] || iqentry_done[head2])))
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3]) || iqentry_done[head3]
|| (iqentry_a1_v[head3] && (iqentry_a1[head6][AMSB:3] != iqentry_a1[head3][AMSB:3] || iqentry_out[head3] || iqentry_done[head3])))
&& (!iqentry_mem[head4] || (iqentry_agen[head4] & iqentry_out[head4]) || iqentry_done[head4]
|| (iqentry_a1_v[head4] && (iqentry_a1[head6][AMSB:3] != iqentry_a1[head4][AMSB:3] || iqentry_out[head4] || iqentry_done[head4])))
&& (!iqentry_mem[head5] || (iqentry_agen[head5] & iqentry_out[head5]) || iqentry_done[head5]
|| (iqentry_a1_v[head5] && (iqentry_a1[head6][AMSB:3] != iqentry_a1[head5][AMSB:3] || iqentry_out[head5] || iqentry_done[head5])))
&& (iqentry_rl[head6] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
5013,20 → 5089,20
//&& ~iqentry_memready[head5]
//&& ~iqentry_memready[head6]
// ... and there is no address-overlap with any preceding instruction
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0])
|| (iqentry_a1_v[head0] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head0][AMSB:3]))
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1])
|| (iqentry_a1_v[head1] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head1][AMSB:3]))
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2])
|| (iqentry_a1_v[head2] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head2][AMSB:3]))
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3])
|| (iqentry_a1_v[head3] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head3][AMSB:3]))
&& (!iqentry_mem[head4] || (iqentry_agen[head4] & iqentry_out[head4])
|| (iqentry_a1_v[head4] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head4][AMSB:3]))
&& (!iqentry_mem[head5] || (iqentry_agen[head5] & iqentry_out[head5])
|| (iqentry_a1_v[head5] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head5][AMSB:3]))
&& (!iqentry_mem[head6] || (iqentry_agen[head6] & iqentry_out[head6])
|| (iqentry_a1_v[head6] && iqentry_a1[head7][AMSB:3] != iqentry_a1[head6][AMSB:3]))
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0]) || iqentry_done[head0]
|| (iqentry_a1_v[head0] && (iqentry_a1[head7][AMSB:3] != iqentry_a1[head0][AMSB:3] || iqentry_out[head0] || iqentry_done[head0])))
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1]) || iqentry_done[head1]
|| (iqentry_a1_v[head1] && (iqentry_a1[head7][AMSB:3] != iqentry_a1[head1][AMSB:3] || iqentry_out[head1] || iqentry_done[head1])))
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2]) || iqentry_done[head2]
|| (iqentry_a1_v[head2] && (iqentry_a1[head7][AMSB:3] != iqentry_a1[head2][AMSB:3] || iqentry_out[head2] || iqentry_done[head2])))
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3]) || iqentry_done[head3]
|| (iqentry_a1_v[head3] && (iqentry_a1[head7][AMSB:3] != iqentry_a1[head3][AMSB:3] || iqentry_out[head3] || iqentry_done[head3])))
&& (!iqentry_mem[head4] || (iqentry_agen[head4] & iqentry_out[head4]) || iqentry_done[head4]
|| (iqentry_a1_v[head4] && (iqentry_a1[head7][AMSB:3] != iqentry_a1[head4][AMSB:3] || iqentry_out[head4] || iqentry_done[head4])))
&& (!iqentry_mem[head5] || (iqentry_agen[head5] & iqentry_out[head5]) || iqentry_done[head5]
|| (iqentry_a1_v[head5] && (iqentry_a1[head7][AMSB:3] != iqentry_a1[head5][AMSB:3] || iqentry_out[head5] || iqentry_done[head5])))
&& (!iqentry_mem[head6] || (iqentry_agen[head6] & iqentry_out[head6]) || iqentry_done[head6]
|| (iqentry_a1_v[head6] && (iqentry_a1[head7][AMSB:3] != iqentry_a1[head6][AMSB:3] || iqentry_out[head6] || iqentry_done[head6])))
&& (iqentry_rl[head7] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0])
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1])
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2])
5180,6 → 5256,10
stompedOnRets = stompedOnRets + 4'd1;
if (iqentry_stomp[7] && iqentry_ret[7])
stompedOnRets = stompedOnRets + 4'd1;
if (iqentry_stomp[8] && iqentry_ret[8])
stompedOnRets = stompedOnRets + 4'd1;
if (iqentry_stomp[9] && iqentry_ret[9])
stompedOnRets = stompedOnRets + 4'd1;
end
 
reg id1_vi, id2_vi, id3_vi;
5356,7 → 5436,7
.imm(fpu1_argI),
.o(fpu1_bus),
.csr_i(),
.status(fpu_status),
.status(fpu1_status),
.exception(),
.done(fpu1_done)
);
5383,7 → 5463,7
.imm(fpu2_argI),
.o(fpu2_bus),
.csr_i(),
.status(fpu_status),
.status(fpu2_status),
.exception(),
.done(fpu2_done)
);
5391,8 → 5471,10
end
endgenerate
 
assign fpu_exc = (fpu1_available|fpu2_available) ?
((|fpu1_status[15:0] || |fpu2_status[15:0]) ? `FLT_FLT : `FLT_NONE) : `FLT_UNIMP;
assign fpu1_exc = (fpu1_available) ?
((|fpu1_status[15:0]) ? `FLT_FLT : `FLT_NONE) : `FLT_UNIMP;
assign fpu2_exc = (fpu2_available) ?
((|fpu2_status[15:0]) ? `FLT_FLT : `FLT_NONE) : `FLT_UNIMP;
 
assign alu0_v = alu0_dataready,
alu1_v = alu1_dataready;
5501,8 → 5583,8
fcu_branchmiss = TRUE & ~fcu_clearbm;
else if (fcu_ret_miss)
fcu_branchmiss = TRUE & ~fcu_clearbm;
else if (fcu_branch && fcu_v && (((fcu_takb && (~fcu_bt || (fcu_misspc != iqentry_pc[nid]))) ||
(~fcu_takb && ( fcu_bt || (fcu_pc + 32'd4 != iqentry_pc[nid])))) || iqentry_v[nid]))
else if (fcu_branch && fcu_v && (((fcu_takb && (fcu_misspc != iqentry_pc[nid])) ||
(~fcu_takb && (fcu_pc + fcu_insln != iqentry_pc[nid])))))// || iqentry_v[nid]))
fcu_branchmiss = TRUE & ~fcu_clearbm;
else if (fcu_jal_miss)
fcu_branchmiss = TRUE & ~fcu_clearbm;
5572,7 → 5654,10
iqentry_memopsvalid[4] = (iqentry_mem[4] & iqentry_a2_v[4] & iqentry_agen[4]),
iqentry_memopsvalid[5] = (iqentry_mem[5] & iqentry_a2_v[5] & iqentry_agen[5]),
iqentry_memopsvalid[6] = (iqentry_mem[6] & iqentry_a2_v[6] & iqentry_agen[6]),
iqentry_memopsvalid[7] = (iqentry_mem[7] & iqentry_a2_v[7] & iqentry_agen[7]);
iqentry_memopsvalid[7] = (iqentry_mem[7] & iqentry_a2_v[7] & iqentry_agen[7]),
iqentry_memopsvalid[8] = (iqentry_mem[8] & iqentry_a2_v[8] & iqentry_agen[8]),
iqentry_memopsvalid[9] = (iqentry_mem[9] & iqentry_a2_v[9] & iqentry_agen[9])
;
 
assign iqentry_memready[0] = (iqentry_v[0] & iqentry_memopsvalid[0] & ~iqentry_memissue[0] & ~iqentry_done[0] & ~iqentry_out[0] & ~iqentry_stomp[0]),
iqentry_memready[1] = (iqentry_v[1] & iqentry_memopsvalid[1] & ~iqentry_memissue[1] & ~iqentry_done[1] & ~iqentry_out[1] & ~iqentry_stomp[1]),
5581,7 → 5666,10
iqentry_memready[4] = (iqentry_v[4] & iqentry_memopsvalid[4] & ~iqentry_memissue[4] & ~iqentry_done[4] & ~iqentry_out[4] & ~iqentry_stomp[4]),
iqentry_memready[5] = (iqentry_v[5] & iqentry_memopsvalid[5] & ~iqentry_memissue[5] & ~iqentry_done[5] & ~iqentry_out[5] & ~iqentry_stomp[5]),
iqentry_memready[6] = (iqentry_v[6] & iqentry_memopsvalid[6] & ~iqentry_memissue[6] & ~iqentry_done[6] & ~iqentry_out[6] & ~iqentry_stomp[6]),
iqentry_memready[7] = (iqentry_v[7] & iqentry_memopsvalid[7] & ~iqentry_memissue[7] & ~iqentry_done[7] & ~iqentry_out[7] & ~iqentry_stomp[7]);
iqentry_memready[7] = (iqentry_v[7] & iqentry_memopsvalid[7] & ~iqentry_memissue[7] & ~iqentry_done[7] & ~iqentry_out[7] & ~iqentry_stomp[7]),
iqentry_memready[8] = (iqentry_v[8] & iqentry_memopsvalid[8] & ~iqentry_memissue[8] & ~iqentry_done[8] & ~iqentry_out[8] & ~iqentry_stomp[8]),
iqentry_memready[9] = (iqentry_v[9] & iqentry_memopsvalid[9] & ~iqentry_memissue[9] & ~iqentry_done[9] & ~iqentry_out[9] & ~iqentry_stomp[9])
;
 
assign outstanding_stores = (dram0 && dram0_store) ||
(dram1 && dram1_store) ||
5712,7 → 5800,7
// If an irq is active during a vector instruction fetch, claim the vector instruction
// is finished queueing even though it may not be. It'll pick up where it left off after
// the exception is processed.
if (hirq) begin
if (freezePC) begin
if (IsVector(fetchbuf0_instr) && IsVector(fetchbuf1_instr) && vechain) begin
queued1 <= TRUE;
queued2 <= TRUE;
5740,7 → 5828,7
canq2 <= IsVector(fetchbuf0_instr) && vqe0 < vl-2 && SUP_VECTOR;
vqueued2 <= IsVector(fetchbuf0_instr) && vqe0 < vl-2 && !vechain;
end
if (hirq) begin
if (freezePC) begin
if (IsVector(fetchbuf0_instr)) begin
queued1 <= TRUE;
if (vqe0 < vl-2)
5762,7 → 5850,7
canq2 <= IsVector(fetchbuf1_instr) && vqe1 < vl-2 && SUP_VECTOR;
vqueued2 <= IsVector(fetchbuf1_instr) && vqe1 < vl-2;
end
if (hirq) begin
if (freezePC) begin
if (IsVector(fetchbuf1_instr)) begin
queued1 <= TRUE;
if (vqe1 < vl-2)
5883,6 → 5971,7
iqentry_fsync[n] <= FALSE;
iqentry_fc[n] <= FALSE;
iqentry_fcu_issue[n] <= FALSE;
iqentry_takb[n] <= FALSE;
iqentry_jmp[n] <= FALSE;
iqentry_jal[n] <= FALSE;
iqentry_ret[n] <= FALSE;
5946,6 → 6035,8
head5 <= 5;
head6 <= 6;
head7 <= 7;
head8 <= 8;
head9 <= 9;
panic = `PANIC_NONE;
alu0_dataready <= 0;
alu1_dataready <= 0;
6002,6 → 6093,7
cr0[32] <= TRUE; // enable branch predictor
cr0[16] <= 1'b0; // disable SMT
cr0[17] <= 1'b0; // sequence number reset = 1
cr0[34] <= FALSE; // write buffer merging enable
pcr <= 32'd0;
pcr2 <= 64'd0;
for (n = 0; n < PREGS; n = n + 1)
6072,6 → 6164,7
id3_vi <= `INV;
if (iqentry_v[nid] && iqentry_sn[nid] > iqentry_sn[fcu_id[`QBITS]])
fcu_dataready <= `INV;
wb_shift <= FALSE;
ld_time <= {ld_time[4:0],1'b0};
wc_times <= wc_time;
rf_vra0 <= regIsValid[Ra0s];
6125,14 → 6218,16
end
end
 
if (|iqentry_0_latestID) if (iqentry_thrd[0]==branchmiss_thrd) rf_source[ {iqentry_tgt[0][7:0]} ] <= { 1'b0, iqentry_mem[0], 3'd0 };
if (|iqentry_1_latestID) if (iqentry_thrd[1]==branchmiss_thrd) rf_source[ {iqentry_tgt[1][7:0]} ] <= { 1'b0, iqentry_mem[1], 3'd1 };
if (|iqentry_2_latestID) if (iqentry_thrd[2]==branchmiss_thrd) rf_source[ {iqentry_tgt[2][7:0]} ] <= { 1'b0, iqentry_mem[2], 3'd2 };
if (|iqentry_3_latestID) if (iqentry_thrd[3]==branchmiss_thrd) rf_source[ {iqentry_tgt[3][7:0]} ] <= { 1'b0, iqentry_mem[3], 3'd3 };
if (|iqentry_4_latestID) if (iqentry_thrd[4]==branchmiss_thrd) rf_source[ {iqentry_tgt[4][7:0]} ] <= { 1'b0, iqentry_mem[4], 3'd4 };
if (|iqentry_5_latestID) if (iqentry_thrd[5]==branchmiss_thrd) rf_source[ {iqentry_tgt[5][7:0]} ] <= { 1'b0, iqentry_mem[5], 3'd5 };
if (|iqentry_6_latestID) if (iqentry_thrd[6]==branchmiss_thrd) rf_source[ {iqentry_tgt[6][7:0]} ] <= { 1'b0, iqentry_mem[6], 3'd6 };
if (|iqentry_7_latestID) if (iqentry_thrd[7]==branchmiss_thrd) rf_source[ {iqentry_tgt[7][7:0]} ] <= { 1'b0, iqentry_mem[7], 3'd7 };
if (|iqentry_0_latestID) if (iqentry_thrd[0]==branchmiss_thrd) rf_source[ {iqentry_tgt[0][7:0]} ] <= { 1'b0, iqentry_mem[0], 4'd0 };
if (|iqentry_1_latestID) if (iqentry_thrd[1]==branchmiss_thrd) rf_source[ {iqentry_tgt[1][7:0]} ] <= { 1'b0, iqentry_mem[1], 4'd1 };
if (|iqentry_2_latestID) if (iqentry_thrd[2]==branchmiss_thrd) rf_source[ {iqentry_tgt[2][7:0]} ] <= { 1'b0, iqentry_mem[2], 4'd2 };
if (|iqentry_3_latestID) if (iqentry_thrd[3]==branchmiss_thrd) rf_source[ {iqentry_tgt[3][7:0]} ] <= { 1'b0, iqentry_mem[3], 4'd3 };
if (|iqentry_4_latestID) if (iqentry_thrd[4]==branchmiss_thrd) rf_source[ {iqentry_tgt[4][7:0]} ] <= { 1'b0, iqentry_mem[4], 4'd4 };
if (|iqentry_5_latestID) if (iqentry_thrd[5]==branchmiss_thrd) rf_source[ {iqentry_tgt[5][7:0]} ] <= { 1'b0, iqentry_mem[5], 4'd5 };
if (|iqentry_6_latestID) if (iqentry_thrd[6]==branchmiss_thrd) rf_source[ {iqentry_tgt[6][7:0]} ] <= { 1'b0, iqentry_mem[6], 4'd6 };
if (|iqentry_7_latestID) if (iqentry_thrd[7]==branchmiss_thrd) rf_source[ {iqentry_tgt[7][7:0]} ] <= { 1'b0, iqentry_mem[7], 4'd7 };
if (|iqentry_8_latestID) if (iqentry_thrd[8]==branchmiss_thrd) rf_source[ {iqentry_tgt[8][7:0]} ] <= { 1'b0, iqentry_mem[8], 4'd8 };
if (|iqentry_9_latestID) if (iqentry_thrd[9]==branchmiss_thrd) rf_source[ {iqentry_tgt[9][7:0]} ] <= { 1'b0, iqentry_mem[9], 4'd9 };
end
 
6805,9 → 6900,9
iqentry_bt[ fcu_id[`QBITS] ] <= `VAL;
end
// Branch target is only updated for branch-to-register
// else if (fcu_branch) begin
// iqentry_bt[ fcu_id[`QBITS] ] <= fcu_takb;
// end
else if (fcu_branch) begin
iqentry_takb[ fcu_id[`QBITS] ] <= fcu_takb;
end
iqentry_out [ fcu_id[`QBITS] ] <= `INV;
//iqentry_agen[ fcu_id[`QBITS] ] <= `VAL;//!IsRet(fcu_instr);
fcu_dataready <= `VAL;
7743,9 → 7838,6
wb_rmw[`WB_DEPTH-1] <= `FALSE;
end
 
// if (|wb_v)
// ;
// else
`endif
if (~|wb_v && mem1_available && dram0==`DRAMSLOT_BUSY && dram0_rmw) begin
`ifdef SUPPORT_DBG
8429,43 → 8521,49
end
endcase
end
`ifndef SUPPORT_SMT
else begin // if branchmiss
else if (!thread_en) begin // if branchmiss
if (iqentry_stomp[0] & ~iqentry_stomp[7]) begin
tail0 <= 3'd0;
tail1 <= 3'd1;
tail0 <= 4'd0;
tail1 <= 4'd1;
end
else if (iqentry_stomp[1] & ~iqentry_stomp[0]) begin
tail0 <= 3'd1;
tail1 <= 3'd2;
tail0 <= 4'd1;
tail1 <= 4'd2;
end
else if (iqentry_stomp[2] & ~iqentry_stomp[1]) begin
tail0 <= 3'd2;
tail1 <= 3'd3;
tail0 <= 4'd2;
tail1 <= 4'd3;
end
else if (iqentry_stomp[3] & ~iqentry_stomp[2]) begin
tail0 <= 3'd3;
tail1 <= 3'd4;
tail0 <= 4'd3;
tail1 <= 4'd4;
end
else if (iqentry_stomp[4] & ~iqentry_stomp[3]) begin
tail0 <= 3'd4;
tail1 <= 3'd5;
tail0 <= 4'd4;
tail1 <= 4'd5;
end
else if (iqentry_stomp[5] & ~iqentry_stomp[4]) begin
tail0 <= 3'd5;
tail1 <= 3'd6;
tail0 <= 4'd5;
tail1 <= 4'd6;
end
else if (iqentry_stomp[6] & ~iqentry_stomp[5]) begin
tail0 <= 3'd6;
tail1 <= 3'd7;
tail0 <= 4'd6;
tail1 <= 4'd7;
end
else if (iqentry_stomp[7] & ~iqentry_stomp[6]) begin
tail0 <= 3'd7;
tail1 <= 3'd0;
tail0 <= 4'd7;
tail1 <= 4'd8;
end
else if (iqentry_stomp[8] & ~iqentry_stomp[7]) begin
tail0 <= 4'd8;
tail1 <= 4'd9;
end
else if (iqentry_stomp[9] & ~iqentry_stomp[8]) begin
tail0 <= 4'd9;
tail1 <= 4'd0;
end
// otherwise, it is the last instruction in the queue that has been mispredicted ... do nothing
end
`endif
 
/*
if (pebm)
8816,8 → 8914,19
input [`ABITS] addr;
input [63:0] data;
begin
if (wbptr > 0 && wb_addr[wbptr-1][AMSB:3]==addr[AMSB:3] && wb_ol[wbptr-1]==ol && wb_rmw[wbptr-1]==rmw) begin
if (wbm && wbptr > 1 && wb_addr[wbptr-1][AMSB:3]==addr[AMSB:3]
&& wb_ol[wbptr-1]==ol && wb_rmw[wbptr-1]==rmw && wb_v[wbptr-1]) begin
// The write buffer is always shifted during the bus IDLE state. That means
// the data is out of place by a slot. The slot the data is moved from is
// invalidated.
wb_v[wbptr-2] <= `INV;
wb_v[wbptr-1] <= wb_en;
wb_id[wbptr-1] <= wb_id[wbptr-1] | (16'd1 << id);
wb_rmw[wbptr-1] <= rmw;
wb_ol[wbptr-1] <= ol;
wb_sel[wbptr-1] <= wb_sel[wbptr-1] | sel;
wb_addr[wbptr-1] <= wb_addr[wbptr-1];
wb_data[wbptr-1] <= wb_data[wbptr-1];
if (sel[0]) wb_data[wbptr-1][ 7: 0] <= data[ 7: 0];
if (sel[1]) wb_data[wbptr-1][15: 8] <= data[15: 8];
if (sel[2]) wb_data[wbptr-1][23:16] <= data[23:16];
8826,7 → 8935,6
if (sel[5]) wb_data[wbptr-1][47:40] <= data[47:40];
if (sel[6]) wb_data[wbptr-1][55:48] <= data[55:48];
if (sel[7]) wb_data[wbptr-1][63:56] <= data[63:56];
wb_id[wbptr-1] <= wb_id[wbptr-1] | (16'd1 << id);
wb_merges <= wb_merges + 32'd1;
end
else begin
8840,6 → 8948,7
end
end
endtask
 
// Increment the head pointers
// Also increments the instruction counter
// Used when instructions are committed.
8848,14 → 8957,16
task head_inc;
input [`QBITS] amt;
begin
head0 <= head0 + amt;
head1 <= head1 + amt;
head2 <= head2 + amt;
head3 <= head3 + amt;
head4 <= head4 + amt;
head5 <= head5 + amt;
head6 <= head6 + amt;
head7 <= head7 + amt;
head0 <= (head0 + amt) % QENTRIES;
head1 <= (head1 + amt) % QENTRIES;
head2 <= (head2 + amt) % QENTRIES;
head3 <= (head3 + amt) % QENTRIES;
head4 <= (head4 + amt) % QENTRIES;
head5 <= (head5 + amt) % QENTRIES;
head6 <= (head6 + amt) % QENTRIES;
head7 <= (head7 + amt) % QENTRIES;
head8 <= (head8 + amt) % QENTRIES;
head9 <= (head9 + amt) % QENTRIES;
I <= I + amt;
if (amt==3'd3) begin
iqentry_agen[head0] <= `INV;
9444,8 → 9555,8
`endif
`CSR_CAS: dat <= cas;
`CSR_TVEC: dat <= tvec[csrno[2:0]];
`CSR_BADADR: dat <= badaddr[{thread,csrno[13:11]}];
`CSR_CAUSE: dat <= {48'd0,cause[{thread,csrno[13:11]}]};
`CSR_BADADR: dat <= badaddr[{thread,csrno[11:10]}];
`CSR_CAUSE: dat <= {48'd0,cause[{thread,csrno[11:10]}]};
`ifdef SUPPORT_SMT
`CSR_IM_STACK: dat <= im_stack[thread];
`CSR_OL_STACK: dat <= ol_stack[thread];
9543,8 → 9654,8
`CSR_SBU: sbu <= dat[31:0];
`CSR_TCB: tcb <= dat;
`CSR_FSTAT: fpu_csr[37:32] <= dat[37:32];
`CSR_BADADR: badaddr[{thread,csrno[13:11]}] <= dat;
`CSR_CAUSE: cause[{thread,csrno[13:11]}] <= dat[15:0];
`CSR_BADADR: badaddr[{thread,csrno[11:10]}] <= dat;
`CSR_CAUSE: cause[{thread,csrno[11:10]}] <= dat[15:0];
`ifdef SUPPORT_DBG
`CSR_DBAD0: dbg_adr0 <= dat[AMSB:0];
`CSR_DBAD1: dbg_adr1 <= dat[AMSB:0];
/FT64v5/rtl/twoway/FT64_BranchPredicator.v
115,18 → 115,22
// commit1 if commit0 is not taken.
reg [1:0] xbits_new;
always @*
if (takb & wrhist) begin
if (bht_xbits != 2'd1)
xbits_new <= bht_xbits + 2'd1;
else
xbits_new <= bht_xbits;
if (wrhist) begin
if (takb) begin
if (bht_xbits != 2'd1)
xbits_new <= bht_xbits + 2'd1;
else
xbits_new <= bht_xbits;
end
else begin
if (bht_xbits != 2'd2)
xbits_new <= bht_xbits - 2'd1;
else
xbits_new <= bht_xbits;
end
end
else begin
if (bht_xbits != 2'd2)
xbits_new <= bht_xbits - {1'b0,wrhist};
else
xbits_new <= bht_xbits;
end
else
xbits_new <= bht_xbits;
 
always @(posedge clk)
if (rst)
/FT64v5/rtl/twoway/FT64_fetchbuf.v
34,7 → 34,7
//
module FT64_fetchbuf(rst, clk4x, clk, fcu_clk,
cs_i, cyc_i, stb_i, ack_o, we_i, adr_i, dat_i,
hirq, thread_en,
freezePC, thread_en,
regLR,
insn0, insn1, phit,
threadx,
72,7 → 72,7
input we_i;
input [15:0] adr_i;
input [31:0] dat_i;
input hirq;
input freezePC;
input thread_en;
input [4:0] regLR;
input [47:0] insn0;
329,9 → 329,7
always @(posedge clk)
if (rst) begin
pc0 <= RSTPC;
`ifdef SUPPORT_SMT
pc1 <= RSTPC;
`endif
fetchbufA_v <= 0;
fetchbufB_v <= 0;
fetchbufC_v <= 0;
473,8 → 471,8
// cycle 2 - where we are now ... fetch the two instructions & update fetchbufX_v appropriately
// if fbA has the branchback, then it is scenario 1.
// if fbB has it: if pc0 == fbB_pc, then it is the former scenario, else it is the latter
4'b1100 : begin
`ifdef SUPPORT_SMT
4'b1100:
if (thread_en) begin
if (take_branchA && take_branchB) begin
pc0 <= branch_pcA;
pc1 <= branch_pcB;
482,20 → 480,12
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
end
else
`endif
if (take_branchA) begin
else if (take_branchA) begin
pc0 <= branch_pcA;
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
`ifdef SUPPORT_SMT
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
`else
fetchbufB_v <= `INV;
if ((queued1|queuedNop)) fetchbuf <= 1'b1;
`endif
end
`ifdef SUPPORT_SMT
else if (take_branchB) begin
pc1 <= branch_pcB;
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
502,17 → 492,20
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
end
`else
end
else begin
if (take_branchA) begin
pc0 <= branch_pcA;
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
fetchbufB_v <= `INV;
if ((queued1|queuedNop)) fetchbuf <= 1'b1;
end
else begin
if (did_branchback0) begin
FetchCD();
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
`ifdef SUPPORT_SMT
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
`else
fetchbuf <= fetchbuf + ((queued2|queuedNop));
`endif
end
else begin
pc0 <= branch_pcB;
520,9 → 513,8
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
end
end
`endif
end
end
 
// 4'b1101 : panic <= `PANIC_INVALIDFBSTATE;
// 4'b1110 : panic <= `PANIC_INVALIDFBSTATE;
621,8 → 613,8
// cycle 2 - where we are now ... fetch the two instructions & update fetchbufX_v appropriately
// if fbC has the branchback, then it is scenario 1.
// if fbD has it: if pc0 == fbB_pc, then it is the former scenario, else it is the latter
4'b1100 : begin
`ifdef SUPPORT_SMT
4'b1100:
if (thread_en) begin
if (take_branchC && take_branchD) begin
pc0 <= branch_pcC;
pc1 <= branch_pcD;
630,20 → 622,12
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
end
else
`endif
if (take_branchC) begin
else if (take_branchC) begin
pc0 <= branch_pcC;
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
`ifdef SUPPORT_SMT
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
`else
fetchbufD_v <= `INV;
if ((queued1|queuedNop)) fetchbuf <= 1'b1;
`endif
end
`ifdef SUPPORT_SMT
else if (take_branchD) begin
pc1 <= branch_pcD;
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
650,17 → 634,20
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
end
`else
end
else begin
if (take_branchC) begin
pc0 <= branch_pcC;
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
fetchbufD_v <= `INV;
if ((queued1|queuedNop)) fetchbuf <= 1'b1;
end
else begin
if (did_branchback1) begin
FetchAB();
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
`ifdef SUPPORT_SMT
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
`else
fetchbuf <= fetchbuf + ((queued2|queuedNop));
`endif
end
else begin
pc0 <= branch_pcD;
669,7 → 656,6
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
end
end
`endif
end
 
// 4'b1101 : panic <= `PANIC_INVALIDFBSTATE;
808,18 → 794,9
assign fetchbuf1_v = (fetchbuf == 1'b0) ? fetchbufB_v : fetchbufD_v ;
assign fetchbuf1_pc = (fetchbuf == 1'b0) ? fetchbufB_pc : fetchbufD_pc ;
assign fetchbuf0_thrd = 1'b0;
`ifdef SUPPORT_SMT
assign fetchbuf1_thrd = 1'b1;
`else
assign fetchbuf1_thrd = 1'b0;
`endif
assign fetchbuf1_thrd = thread_en;
 
`ifndef SUPPORT_SMT
always @*
pc1 <= pc0 + fetchbuf0_insln;
`endif
 
always @*
begin
if (insn0[7:6]==2'b00 && insn0[`INSTRUCTION_OP]==`EXEC)
fetchbuf0_insln <= fnInsLength(codebuf0);
862,15 → 839,14
fetchbufA_instr <= cinsn0;
fetchbufA_v <= `VAL;
fetchbufA_pc <= pc0;
if (phit && ~hirq)
`ifdef SUPPORT_SMT
pc0 <= pc0 + fetchbuf0_insln;
`else
if (`WAYS > 1)
pc0 <= pc0 + fetchbuf0_insln + fetchbuf1_insln;
else
pc0 <= pc0 + fetchbuf0_insln;
`endif
if (phit && ~freezePC) begin
if (thread_en)
pc0 <= pc0 + fetchbuf0_insln;
else if (`WAYS > 1)
pc0 <= pc0 + fetchbuf0_insln + fetchbuf1_insln;
else
pc0 <= pc0 + fetchbuf0_insln;
end
end
endtask
 
878,11 → 854,12
begin
fetchbufB_instr <= cinsn1;
fetchbufB_v <= `WAYS > 1;
fetchbufB_pc <= pc1;
`ifdef SUPPORT_SMT
if (phit)
if (thread_en)
fetchbufB_pc <= pc1;
else
fetchbufB_pc <= pc0 + fetchbuf0_insln;
if (phit & thread_en)
pc1 <= pc1 + fetchbuf1_insln;
`endif
end
endtask
 
899,15 → 876,14
fetchbufC_instr <= cinsn0;
fetchbufC_v <= `VAL;
fetchbufC_pc <= pc0;
if (phit && ~hirq)
`ifdef SUPPORT_SMT
pc0 <= pc0 + fetchbuf0_insln;
`else
if (`WAYS > 1)
pc0 <= pc0 + fetchbuf0_insln + fetchbuf1_insln;
else
pc0 <= pc0 + fetchbuf0_insln;
`endif
if (phit && ~freezePC) begin
if (thread_en)
pc0 <= pc0 + fetchbuf0_insln;
else if (`WAYS > 1)
pc0 <= pc0 + fetchbuf0_insln + fetchbuf1_insln;
else
pc0 <= pc0 + fetchbuf0_insln;
end
end
endtask
 
915,11 → 891,12
begin
fetchbufD_instr <= cinsn1;
fetchbufD_v <= `WAYS > 1;
fetchbufD_pc <= pc1;
`ifdef SUPPORT_SMT
if (phit)
if (thread_en)
fetchbufD_pc <= pc1;
else
fetchbufD_pc <= pc0 + fetchbuf0_insln;
if (phit & thread_en)
pc1 <= pc1 + fetchbuf1_insln;
`endif
end
endtask
 
/FT64v5/rtl/twoway/FT64_stomp.v
22,10 → 22,10
//
// ============================================================================
//
`define QBITS 2:0
`include "FT64_config.vh"
 
module FT64_stomp(branchmiss,branchmiss_thrd,missid,head0,thrd,iqentry_v,stomp);
parameter QENTRIES = 8;
parameter QENTRIES = `QENTRIES;
input branchmiss;
input branchmiss_thrd;
input [`QBITS] missid;
41,7 → 41,7
reg [`QBITS] contid;
always @*
if (branchmiss) begin
stomp2 = 8'h00;
stomp2 = {QENTRIES{1'b0}};
 
// If missed at the head, all queue entries but the head are stomped on.
if (head0==missid) begin

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