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    from Rev 40 to Rev 41
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Rev 40 → Rev 41

/tinycpu/trunk/testbench/top_tb.vhd
70,6 → 70,7
stim_proc: process
variable err_cnt: integer :=0;
begin
Port0 <= "ZZZZZZZZ";
-- hold reset state for 100 ns.
Reset <= '0';
wait for 10 ns;
78,11 → 79,11
Reset <= '0';
wait for 50 ns;
Port0(1) <= '1';
wait for 100 ns;
wait for 200 ns;
assert(Port0(0)='1') report "Toggle app not working" severity error;
wait for 10 ns;
Port0(0) <= '0';
wait for 100 ns;
Port0(1) <= '0';
wait for 200 ns;
assert(Port0(0)='0') report "Toggle app not working 2" severity error;
 
 
/tinycpu/trunk/testbench/memory_tb.vhd
118,7 → 118,28
WriteEnable <= '0';
wait for 10 ns;
assert (DataOut = x"5678") report "aligned 8-bit memory write is wrong" severity error;
Address <= x"0001";
Port0 <= "ZZZZZZ1Z";
WriteWord<='0';
WriteEnable <= '1';
DataIn <= x"0001";
wait for 10 ns;
WriteEnable <= '0';
Address <= x"1234";
wait for 20 ns;
WriteEnable <= '1';
Address <= x"0000";
DataIn <= x"0001";
wait for 10 ns;
WriteEnable <= '0';
assert(Port0(0)='1') report "port0 not right 1" severity error;
wait for 10 ns;
assert(DataOut(1)='1') report "port0 not right 2" severity error;
 
 
wait for 10 ns;
Address <= x"0001";
WriteWord <= '0';
WriteEnable <= '1';
/tinycpu/trunk/src/bootrom.vhd
13,8 → 13,8
architecture syn of bootrom is
constant ROMSIZE: integer := 64;
type ROM_TYPE is array(0 to ROMSIZE/2-1) of std_logic_vector(15 downto 0);
signal ROM: ROM_TYPE := (x"0801", x"0a01", x"5853", x"0600", x"0402", x"5033", x"4020", x"3007", x"1701", x"3006", x"1700", x"0e16",
x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000");
signal ROM: ROM_TYPE := (x"0801", x"0afd", x"5853", x"0600", x"1600", x"0402", x"5032", x"4020", x"3007", x"1701", x"3006", x"1700", x"0e0c",
x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000");
signal rdata : std_logic_vector(15 downto 0);
begin
 
/tinycpu/trunk/src/memory.vhd
81,7 → 81,7
end if;
end process;
assignram: process (we, datawrite, addr, r1out, port0, WriteEnable, Address, Clock)
assignram: process (we, datawrite, addr, r1out, port0, WriteEnable, Address, Clock, port0temp, port0we, DataIn)
variable tmp: integer;
variable tmp2: integer;
variable found: boolean := false;
92,28 → 92,38
if rising_edge(Clock) then
if WriteWord='0' then
if tmp2=0 then
dataread <= x"0000";
--dataread <= x"0000";
gen: for I in 0 to 7 loop
if WriteEnable='1' then
if port0we(I)='1' then --1-bit port set to WRITE mode
port0(I) <= DataIn(I);
Port0(I) <= DataIn(I);
if I=0 then
-- report string(DataIn(I));
--assert(DataIn(I)='1') report "XXXXX" severity note;
--port0(I) <= '1';
end if;
port0temp(I) <= DataIn(I);
--dataread(I) <= DataIn(I);
else
port0(I) <= 'Z';
port0temp(I) <= '0';
--dataread(I) <= port0(I);
end if;
else --not WE
if port0we(I)='0' then --1-bit-port set to READ mode
dataread(I) <= port0(I);
--dataread(I) <= port0(I);
else
dataread(I) <= port0temp(I);
--dataread(I) <= port0temp(I);
end if;
end if;
end loop gen;
elsif tmp2=1 then
dataread <= x"00" & port0we;
--dataread <= x"00" & port0we;
if WriteEnable='1' then
port0we <= DataIn(7 downto 0);
--dataread<=x"00" & DataIn(7 downto 0);
setwe: for I in 0 to 7 loop
if DataIn(I)='0' then
port0(I) <= 'Z';
120,7 → 130,7
end if;
end loop setwe;
else
dataread <= x"00" & port0we;
--dataread <= x"00" & port0we;
end if;
else
--synthesis off
134,6 → 144,28
--synthesis on
end if;
end if;
dataread <= x"0000";
outgen: for I in 0 to 7 loop
if tmp2=0 then
if port0we(I)='1' then
if WriteEnable='1' then
dataread(I) <= DataIn(I);
else
dataread(I) <= port0temp(I);
end if;
else
dataread(I) <= port0(I);
end if;
elsif tmp2=0 then
if WriteEnable='1' then
dataread(I) <= DataIn(I);
else
dataread(I) <= port0we(I);
end if;
else
dataread(I) <= '0';
end if;
end loop outgen;
R1en <= '0';
R1we <= "00";
R1in <= x"0000";
157,10 → 189,14
 
readdata: process(Address, dataread)
begin
if Address(0) = '0' then
DataOut <= dataread;
if to_integer(unsigned(Address))>15 then
if Address(0) = '0' then
DataOut <= dataread;
else
DataOut <= x"00" & dataread(15 downto 8);
end if;
else
DataOut <= x"00" & dataread(15 downto 8);
DataOut <= x"00" & dataread(7 downto 0);
end if;
end process;
end Behavioral;
/tinycpu/trunk/Makefile
12,7 → 12,7
SIMDIR = simulation
# Simulation break condition
#GHDL_SIM_OPT = --assert-level=error
GHDL_SIM_OPT = --stop-time=500ns
GHDL_SIM_OPT = --stop-time=1000ns
WAVEFORM_VIEWER = gtkwave
/tinycpu/trunk/assembler/asm.rb
195,7 → 195,7
if arg2.length>1 or arg2.length<1 or not arg2[0].kind_of? Register8 then
raise "memory reference is not correct. Only a register is allowed";
end
mov_mreg_reg arg1,arg2[0]
mov_reg_mreg arg1,arg2[0]
elsif arg1.kind_of? Register8 and arg2.kind_of? Register8 then
mov_reg_reg arg1, arg2
else
314,11 → 314,11
end
end
$labellist={}
def label(name)
def new_label(name)
$labellist[name.to_s]=$position;
end
def lbl(name)
$labellist[name.to_s]=$position;
$labellist[name.to_s];
end
345,12 → 345,14
#port0(0) is LED port0(1) is a button
 
mov r4, 1
mov r5, 0x01 #the port bitmask
mov r5, 0xFD
#mov r5, 0x01 #the port bitmask
mov [r4],r5
mov r3, 0
mov [r3], 0
mov r2, 0x02
#poll for button
label :loop
new_label :loop
mov r0, [r3]
and_ r0, r2 #isolate just the button at pin 2
cmpneq r0, 0

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