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URL https://opencores.org/ocsvn/tinyvliw8/tinyvliw8/trunk

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    /tinyvliw8
    from Rev 8 to Rev 9
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Rev 8 → Rev 9

/trunk/testbench/sysArch_tb.vhd
1,3 → 1,37
-------------------------------------------------------------------------------
--
-- Design: tinyVLIW8 soft-core processor
-- Author: Oliver Stecklina <stecklina@ihp-microelectronics.com>
-- Date: 24.10.2013
-- File: sysArch_tb.vhd
--
-------------------------------------------------------------------------------
--
-- Description : System architecture testbench. Using a ROM initialized by
-- ihex file to simplify system tests.
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2015 IHP GmbH, Frankfurt (Oder), Germany
--
-- This code is free software. It is licensed under the EUPL, Version 1.1
-- or - as soon they will be approved by the European Commission - subsequent
-- versions of the EUPL (the "License").
-- You may redistribute this code and/or modify it under the terms of this
-- License.
-- You may not use this work except in compliance with the License.
-- You may obtain a copy of the License at:
--
-- http://joinup.ec.europa.eu/software/page/eupl/licence-eupl
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" basis,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
 
51,27 → 85,6
);
end component;
 
component symDecoder
port (
clk : in std_logic;
 
codeA : in std_logic;
codeB : in std_logic;
ioAddr : in std_logic_vector(3 downto 0); -- register address
ioWriteEn_n : in std_logic; -- write enable, low active
ioReadEn_n : in std_logic; -- read enable, low active
 
ioDataOut : out std_logic_vector(7 downto 0); -- data bus for writing register
ioDataIn : in std_logic_vector(7 downto 0); -- data bus for reading register
 
irq : out std_logic;
irq_ack : in std_logic;
 
rst_n : in std_logic
);
end component;
 
component lib_tb_clock32kHz is
port (
signal clk : out std_logic;
99,22 → 112,6
);
end component;
 
component wurCodeGen_tb is
port (
clk : in std_logic;
 
pattern : in std_logic_vector(31 downto 0);
mask : in std_logic_vector(31 downto 0);
 
codeA : out std_logic;
codeB : out std_logic;
 
finished : out std_logic;
 
rst_n : in std_logic
);
end component;
 
component gendelay
generic (n: integer := 1);
port (
161,16 → 158,6
signal dataInClk_s : std_logic;
signal dataOutClk_s : std_logic;
 
signal ioSymRdEn_n_s : std_logic;
 
signal wurPattern_s : std_Logic_vector(31 downto 0);
signal wurMsk_s : std_Logic_vector(31 downto 0);
signal codeA_s : std_logic;
signal codeB_s : std_logic;
 
signal wurCodeEn_n_s : std_logic;
signal wurCodeFin_s : std_logic;
 
signal rst_n_s : std_logic := '1';
 
begin
216,40 → 203,6
rst_n => rst_n_s
);
 
symDecoder_i: symDecoder
port map (
clk => clk_s,
 
codeA => codeA_s,
codeB => codeB_s,
ioAddr => ioAddr_s(3 downto 0),
ioWriteEn_n => ioWrEn_n_s,
ioReadEn_n => ioSymRdEn_n_s,
 
ioDataOut => ioDataIn_s,
ioDataIn => ioDataOut_s,
 
irq => irqLine_s,
irq_ack => irqLineAck_s,
 
rst_n => rst_n_s
);
 
ioSymRdEn_n_s <= ioRdEn_n_s when ioAddr_s(7 downto 4) = "0100" else
'1';
 
tb_wurCodeGen_i: wurCodeGen_tb
port map (
clk => clk_s,
pattern => wurPattern_s,
mask => wurMsk_s,
codeA => codeA_s,
codeB => codeB_s,
finished => wurCodeFin_s,
rst_n => wurCodeEn_n_s
);
 
tb_clock32kHz_i: lib_tb_clock32kHz
port map (
clk => clk_s,
257,7 → 210,7
);
 
tb_rom32bit_i: lib_tb_rom32bit
generic map ( fileName => "../programs/sha1Test.ihex" )
generic map ( fileName => "../opencores/tinyvliw8/tinyvliw8/trunk/programs/timerIrq.ihex" )
port map (
addr => instAddr_s,
dataOut => instData_s,
288,31 → 241,5
'0';
dataOutClk_s <= not(dataInClk_s);
 
 
wurGen_p : process
begin
wurMsk_s <= x"ffffffff";
wurPattern_s <= x"abababab";
wurCodeEn_n_s <= '0';
loop
wait on rst_n_s;
exit when rst_n_s = '1';
end loop;
 
loop
wait for 100 ms;
 
wurCodeEn_n_s <= '1';
 
loop
wait on wurCodeFin_s;
exit when wurCodeFin_s = '1';
end loop;
 
wurCodeEn_n_s <= '0';
end loop;
end process;
 
end beh;
 
/trunk/src/vhdl/timer.vhd
1,17 → 1,17
-----------------------------------------------------------------
--
-- Design: tinyVLIW8 soft-core processor
--
-- Design: tinyVLIW8 soft-core processor
-- Author: Oliver Stecklina <stecklina@ihp-microelectronics.com>
-- Date: 27.05.2015
-- File: timer.vhd
--
--
-----------------------------------------------------------------
--
-- Description : 16-bit timer module. The timer provides two
--
-- Description : 16-bit timer module. The timer provides two
-- internal timer modules.
--
--
-----------------------------------------------------------------
--
--
-- Copyright (C) 2015 IHP GmbH, Frankfurt (Oder), Germany
--
-- This code is free software. It is licensed under the EUPL, Version 1.1
29,10 → 29,10
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-----------------------------------------------------------------
--
-----------------------------------------------------------------
 
LIBRARY IEEE;
LIBRARY IEEE;
 
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
57,18 → 57,18
END timer;
 
ARCHITECTURE behav OF timer IS
 
component clock_divider
 
component clock_divider
generic (n: integer := 2);
PORT (
inclk : in std_logic;
outclk : out std_logic;
div : in std_logic_vector((n - 1) downto 0);
en : IN std_logic
inclk : in std_logic;
outclk : out std_logic;
div : in std_logic_vector((n - 1) downto 0);
en : IN std_logic
);
END component;
 
 
component gendelay
generic (n: integer := 1);
port (
76,146 → 76,155
a_out : out std_logic
);
end component;
 
signal clk_s : std_logic;
signal rst_n_s : std_logic;
 
-- signal clk_s : std_logic;
signal rst_n_s : std_logic;
signal cnt_reg : std_logic_vector(15 downto 0); -- state counter
signal ifg_reg : std_logic_vector(1 downto 0);
 
signal ccr0 : std_logic_vector(15 downto 0);
signal ccr1 : std_logic_vector(15 downto 0);
-- | clr(7) | mode(6) | ie1(5) | ie0(4) | .. | div(2 .. 1) | en(0) |
signal ctl_reg : std_logic_vector(6 downto 0);
 
signal irq_s : std_logic;
signal ifgEn_s : std_logic;
signal divclk_s : std_logic;
 
signal clrBit_s : std_logic;
signal clr_s : std_logic;
 
 
signal ccr0 : std_logic_vector(15 downto 0);
signal ccr1 : std_logic_vector(15 downto 0);
-- | clr(7) | mode(6) | ie1(5) | ie0(4) | .. | div(2 .. 1) | en(0) |
signal ctl_reg : std_logic_vector(6 downto 0);
 
signal irq_s : std_logic;
signal ifgEn_s : std_logic;
signal divclk_s : std_logic;
 
signal clrBit_s : std_logic;
signal clr_s : std_logic;
signal rst_tar_cnt : std_logic;
 
BEGIN
 
delay_i: gendelay
generic map (n => 2)
port map (
a_in => clrBit_s,
a_out => clr_s
);
 
rst_n_s <= rst_n;
clk_s <= clk;
clk_div_i : clock_divider
generic map (n => 2)
port map (
inclk => clk_s,
outclk => divclk_s,
 
div => ctl_reg(2 downto 1),
en => ctl_reg(0)
);
tar_cnt : process (divclk_s, rst_n_s, clr_s) -- state counter
 
-- delay_i: gendelay
-- generic map (n => 2)
-- port map (
-- a_in => clrBit_s,
-- a_out => clr_s
-- );
clr_s <= clrBit_s;
rst_n_s <= rst_n;
-- clk_s <= clk;
clk_div_i : clock_divider
generic map (n => 2)
port map (
inclk => clk,
outclk => divclk_s,
 
div => ctl_reg(2 downto 1),
en => ctl_reg(0)
);
 
clrBit_s <= '1' when dataIn(7) = '1' and readEn_n = '0' and addr = "000" and writeEn_n = '0' else
'0';
rst_tar_cnt <='0' when rst_n_s='0' else
'0' when clrBit_s='1' else
'1';
 
tar_cnt : process (divclk_s, rst_tar_cnt) -- state counter
variable cnt: unsigned (15 downto 0);
BEGIN
IF (rst_n_s = '0' or clr_s = '1') THEN
--IF (rst_n_s = '0' or clr_s = '1') THEN
IF (rst_tar_cnt='0') THEN
cnt := (others => '0');
ELSE
if (divclk_s'EVENT AND divclk_s = '1') THEN -- rising SCKL edge
ELSE
if (divclk_s'EVENT AND divclk_s = '1') THEN -- rising SCKL edge
IF (ctl_reg(6) = '0' and cnt = cnt'high) or (ctl_reg(6) = '1' and cnt = unsigned(ccr0)) THEN
cnt := (others => '0');
ELSE
cnt := cnt + 1;
END IF;
END IF;
END if;
END IF;
END IF;
cnt_reg <= std_logic_vector(cnt);
END PROCESS;
 
irq_en : process(rst_n_s, clk_s)
begin
 
irq_en : process(rst_n_s, clk)
begin
IF (rst_n_s = '0') THEN
irq_s <= '0';
ELSE
if (clk_s'EVENT AND clk_s = '0') THEN -- falling SCKL edge
if (irq_ack = '1') then
irq_s <= '0';
else
if ((ctl_reg(4) = '1' and cnt_reg = ccr0 and ifg_reg(0) = '0') or (ctl_reg(5) = '1' and cnt_reg = ccr1 and ifg_reg(1) = '0')) then
irq_s <= '1';
end if;
end if;
end if;
end if;
end process;
 
ifgEn_s <= irq_s or not(writeEn_n);
ifg : process(rst_n_s, ifgEn_s)
ELSE
if (clk'EVENT AND clk = '0') THEN -- falling SCKL edge
if (irq_ack = '1') then
irq_s <= '0';
else
if ((ctl_reg(4) = '1' and cnt_reg = ccr0 and ifg_reg(0) = '0') or (ctl_reg(5) = '1' and cnt_reg = ccr1 and ifg_reg(1) = '0')) then
irq_s <= '1';
end if;
end if;
end if;
end if;
end process;
 
ifgEn_s <= irq_s or not(writeEn_n);
ifg : process(rst_n_s, ifgEn_s)
BEGIN
IF (rst_n_s = '0') THEN
ifg_reg <= (others => '0');
ELSE
if (ifgEn_s'event and ifgEn_s = '1') then
if (irq_s = '1') then
if (ctl_reg(4) = '1' and cnt_reg = ccr0) then
ifg_reg(0) <= '1';
end if;
if (ctl_reg(5) = '1' and cnt_reg = ccr1) then
ifg_reg(1) <= '1';
end if;
else
if (readEn_n = '0' and writeEn_n = '0' and addr = "001") then
ifg_reg <= ifg_reg and not(dataIn(1 downto 0));
end if;
end if;
end if;
end if;
end process;
wr_reg : process(rst_n_s, readEn_n, writeEn_n) -- state counter
ELSE
if (ifgEn_s'event and ifgEn_s = '1') then
if (irq_s = '1') then
if (ctl_reg(4) = '1' and cnt_reg = ccr0) then
ifg_reg(0) <= '1';
end if;
if (ctl_reg(5) = '1' and cnt_reg = ccr1) then
ifg_reg(1) <= '1';
end if;
else
if (readEn_n = '0' and writeEn_n = '0' and addr = "001") then
ifg_reg <= ifg_reg and not(dataIn(1 downto 0));
end if;
end if;
end if;
end if;
end process;
wr_reg : process(rst_n_s, readEn_n, writeEn_n) -- state counter
BEGIN
IF (rst_n_s = '0') THEN
ctl_reg <= (others => '0');
ctl_reg <= (others => '0');
ccr0 <= (others => '0');
ccr1 <= (others => '0');
ELSE
if (readEn_n = '0') then
if (writeEn_n'event and writeEn_n = '0') then
CASE addr IS
when "000" => ctl_reg <= dataIn(6 downto 0);
when "100" => ccr0(7 downto 0) <= dataIn;
when "101" => ccr0(15 downto 8) <= dataIn;
when "110" => ccr1(7 downto 0) <= dataIn;
when "111" => ccr1(15 downto 8) <= dataIn;
WHEN others => null;
END CASE;
end if;
end if;
end if;
ELSE
if (readEn_n = '0') then
if (writeEn_n'event and writeEn_n = '0') then
CASE addr IS
when "000" => ctl_reg <= dataIn(6 downto 0);
when "100" => ccr0(7 downto 0) <= dataIn;
when "101" => ccr0(15 downto 8) <= dataIn;
when "110" => ccr1(7 downto 0) <= dataIn;
when "111" => ccr1(15 downto 8) <= dataIn;
WHEN others => null;
END CASE;
end if;
end if;
end if;
END PROCESS;
 
clrBit_s <= '1' when dataIn(7) = '1' and readEn_n = '0' and addr = "000" and writeEn_n = '0' else
'0';
 
dataOut <= '0' & ctl_reg when rst_n_s = '1' and readEn_n = '0' and addr = "000" else
"000000" & ifg_reg(1 downto 0) when rst_n_s = '1' and readEn_n = '0' and addr = "001" else
cnt_reg(7 downto 0) when rst_n_s = '1' and readEn_n = '0' and addr = "010" else
cnt_reg(15 downto 8) when rst_n_s = '1' and readEn_n = '0' and addr = "011" else
ccr0(7 downto 0) when rst_n_s = '1' and readEn_n = '0' and addr = "100" else
ccr0(15 downto 8) when rst_n_s = '1' and readEn_n = '0' and addr = "101" else
ccr1(7 downto 0) when rst_n_s = '1' and readEn_n = '0' and addr = "110" else
ccr1(15 downto 8) when rst_n_s = '1' and readEn_n = '0' and addr = "111" else
(others => '0');
irq <= irq_s when rst_n_s = '1' else
'0';
 
 
dataOut <= '0' & ctl_reg when rst_n_s = '1' and readEn_n = '0' and addr = "000" else
"000000" & ifg_reg(1 downto 0) when rst_n_s = '1' and readEn_n = '0' and addr = "001" else
cnt_reg(7 downto 0) when rst_n_s = '1' and readEn_n = '0' and addr = "010" else
cnt_reg(15 downto 8) when rst_n_s = '1' and readEn_n = '0' and addr = "011" else
ccr0(7 downto 0) when rst_n_s = '1' and readEn_n = '0' and addr = "100" else
ccr0(15 downto 8) when rst_n_s = '1' and readEn_n = '0' and addr = "101" else
ccr1(7 downto 0) when rst_n_s = '1' and readEn_n = '0' and addr = "110" else
ccr1(15 downto 8) when rst_n_s = '1' and readEn_n = '0' and addr = "111" else
(others => '0');
irq <= irq_s when rst_n_s = '1' else
'0';
END behav;
 
/trunk/src/vhdl/proc/pcReg.vhd
142,16 → 142,23
end if;
end if;
 
if (irq = '1') then
pcIrq_s <= pcReg_v;
pcReg_s <= "111111111" & irqAddr;
else
pcReg_s <= pcReg_v;
end if;
pcReg_s <= pcReg_v;
 
end if;
end if;
end process;
irq_Assign: process(rst_n, irq)
begin
if (rst_n = '0') then
pcIrq_s <= (others => '0');
else
if (irq'event and irq = '1') then
pcIrq_s <= pcReg_s;
end if;
end if;
end process;
 
pcLoad_n <= pcLoad_n_s when rst_n = '1' and delayedState3_s = '1' else
'1';
pcRegUpd_s <= state3_s when rst_n = '1' and stalled_n = '1' else
158,7 → 165,8
'1' when rst_n = '1' and irq = '1' else
'0';
 
addrOut <= pcReg_s;
addrOut <= pcReg_s when irq = '0' else
"111111111" & irqAddr;
ioOut <= pcInt_s(7 downto 0) when (rst_n = '1' and ioInEn_n = '0' and ioAddr = "00") else
"00000" & pcInt_s(10 downto 8) when (rst_n = '1' and ioInEn_n = '0' and ioAddr = "01") else
/trunk/src/vhdl/proc/instDecoder.vhd
1,54 → 1,75
-----------------------------------------------------------------
-- Project: Aeternitas
-------------------------------------------------------------------------------
--
-- Design: tinyVLIW8 soft-core processor
-- Author: Oliver Stecklina <stecklina@ihp-microelectronics.com>
-- Date: 03.02.2014
-- File: instDecoder.vhd
-- Design: AeternitasSWUR
-----------------------------------------------------------------
-- Description : This unit is the instruction set decoder of the
--
-------------------------------------------------------------------------------
--
-- Description : This unit is the instruction set decoder of the
-- embedded 8-bit VLIW processor.
-----------------------------------------------------------------
-- $Log$
-----------------------------------------------------------------
 
library ieee;
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2015 IHP GmbH, Frankfurt (Oder), Germany
--
-- This code is free software. It is licensed under the EUPL, Version 1.1
-- or - as soon they will be approved by the European Commission - subsequent
-- versions of the EUPL (the "License").
-- You may redistribute this code and/or modify it under the terms of this
-- License.
-- You may not use this work except in compliance with the License.
-- You may obtain a copy of the License at:
--
-- http://joinup.ec.europa.eu/software/page/eupl/licence-eupl
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" basis,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-------------------------------------------------------------------------------
 
library ieee;
 
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity vliwProc_instDecoder is
port (
clk : in std_logic;
 
instData : in std_logic_vector(31 downto 0);
ldstOpCode : out std_logic;
ldstAs : out std_logic_vector(1 downto 0);
ldstDstReg : out std_logic_vector(2 downto 0);
ldstSrc : out std_logic_vector(7 downto 0);
ldstEn_n : out std_logic;
 
aluOpCode : out std_logic_vector(2 downto 0);
aluAs : out std_logic_vector(1 downto 0);
aluDstReg : out std_logic_vector(2 downto 0);
aluSrc : out std_logic_vector(7 downto 0);
aluEn_n : out std_logic;
 
jmpAs : out std_logic_vector(1 downto 0);
jmpDstReg : out std_logic_vector(10 downto 0);
jmpEn_n : out std_logic;
 
esb : out std_logic_vector(3 downto 0);
stalled_n : out std_logic;
stall_n : in std_logic;
port (
clk : in std_logic;
 
rst_n : in std_logic
instData : in std_logic_vector(31 downto 0);
ldstOpCode : out std_logic;
ldstAs : out std_logic_vector(1 downto 0);
ldstDstReg : out std_logic_vector(2 downto 0);
ldstSrc : out std_logic_vector(7 downto 0);
ldstEn_n : out std_logic;
 
aluOpCode : out std_logic_vector(2 downto 0);
aluAs : out std_logic_vector(1 downto 0);
aluDstReg : out std_logic_vector(2 downto 0);
aluSrc : out std_logic_vector(7 downto 0);
aluEn_n : out std_logic;
 
jmpAs : out std_logic_vector(1 downto 0);
jmpDstReg : out std_logic_vector(10 downto 0);
jmpEn_n : out std_logic;
 
esb : out std_logic_vector(3 downto 0);
stalled_n : out std_logic;
stall_n : in std_logic;
 
rst_n : in std_logic
);
end vliwProc_instDecoder;
architecture behavior of vliwProc_instDecoder is
 
architecture behavior of vliwProc_instDecoder is
 
component gendelay
generic (n: integer := 1);
port (
56,35 → 77,35
a_out : out std_logic
);
end component;
 
signal instWord0_s : std_logic_vector(15 downto 0);
signal instWord1_s : std_logic_vector(15 downto 0);
signal clk_s : std_logic;
 
signal esb_s : std_logic_vector(3 downto 0);
signal untSel0_n_s : std_logic_vector(2 downto 0);
signal untSel1_n_s : std_logic_vector(2 downto 0);
signal stalled_n_s : std_logic;
 
signal ldstEn_n_s : std_logic;
signal aluEn_n_s : std_logic;
signal jmpEn_n_s : std_logic;
 
signal instWord0_s : std_logic_vector(15 downto 0);
signal instWord1_s : std_logic_vector(15 downto 0);
signal clk_s : std_logic;
 
signal esb_s : std_logic_vector(3 downto 0);
signal untSel0_n_s : std_logic_vector(2 downto 0);
signal untSel1_n_s : std_logic_vector(2 downto 0);
signal stalled_n_s : std_logic;
 
signal ldstEn_n_s : std_logic;
signal aluEn_n_s : std_logic;
signal jmpEn_n_s : std_logic;
signal cnt_s : std_logic_vector(1 downto 0);
begin
 
clk_s <= clk;
begin
 
clk_s <= clk;
stalled_n <= stalled_n_s;
 
 
-- Note! use cnt_s instead of esb to be faster than esb
-- otherwise we get a glitch on esb(0) in case of stall
sync_Stall: process(rst_n, cnt_s(0))
begin
if (rst_n = '0') then
stalled_n_s <= '1';
begin
if (rst_n = '0') then
stalled_n_s <= '1';
else
if (cnt_s(0)'event and cnt_s(0) = '1') then
stalled_n_s <= stall_n;
95,7 → 116,7
ldstEn_n <= ldstEn_n_s;
jmpEn_n <= jmpEn_n_s;
aluEn_n <= aluEn_n_s;
 
 
genState_p : process(rst_n, clk_s)
begin
if (rst_n = '0') then
110,7 → 131,7
end if;
end if;
end process;
 
 
-- execution state bus
esb_s <= "0001" when rst_n = '1' and cnt_s = "01" else
"0010" when rst_n = '1' and cnt_s = "11" else
117,10 → 138,10
"0100" when rst_n = '1' and cnt_s = "10" else
"1000" when rst_n = '1' and cnt_s = "00" else
"0000";
 
esb <= esb_s when stalled_n_s = '1' else
(others => '0');
 
 
esb <= esb_s when stalled_n_s = '1' else
(others => '0');
 
untSel1_n_s <= "111" when instWord0_s(15 downto 13) = instWord1_s(15 downto 13) else
"110" when instWord1_s(15 downto 13) = "111" else
"101" when instWord1_s(15 downto 13) = "000" or instWord1_s(15 downto 13) = "001" else
130,48 → 151,48
"101" when instWord0_s(15 downto 13) = "000" or instWord0_s(15 downto 13) = "001" else
"011";
 
 
jmpEn_n_s <= '0' when (untSel0_n_s(0) = '0' or untSel1_n_s(0) = '0') and cnt_s(1) = '1' else
'1';
ldstEn_n_s <= '0' when (untSel0_n_s(1) = '0' or untSel1_n_s(1) = '0') and cnt_s(1) = '1' else
'1';
aluEn_n_s <= '0' when (untSel0_n_s(2) = '0' or untSel1_n_s(2) = '0') and cnt_s(1) = '1' else
'1';
 
instWord0_s <= instData(31 downto 16);
instWord1_s <= instData(15 downto 0);
aluOpCode <= instWord0_s(15 downto 13) when untSel0_n_s(2) = '0' else
instWord1_s(15 downto 13) when untSel1_n_s(2) = '0' else
(others => '0');
aluAs <= instWord0_s(12 downto 11) when untSel0_n_s(2) = '0' else
instWord1_s(12 downto 11) when untSel1_n_s(2) = '0' else
(others => '0');
aluDstReg <= instWord0_s(10 downto 8) when untSel0_n_s(2) = '0' else
instWord1_s(10 downto 8) when untSel1_n_s(2) = '0' else
(others => '0');
aluSrc <= instWord0_s(7 downto 0) when untSel0_n_s(2) = '0' else
instWord1_s(7 downto 0) when untSel1_n_s(2) = '0' else
(others => '0');
 
ldstOpCode <= instWord0_s(13) when untSel0_n_s(1) = '0' else
instWord1_s(13) when untSel1_n_s(1) = '0' else
'0';
ldstAs <= instWord0_s(12 downto 11) when untSel0_n_s(1) = '0' else
instWord1_s(12 downto 11) when untSel1_n_s(1) = '0' else
(others => '0');
ldstDstReg <= instWord0_s(10 downto 8) when untSel0_n_s(1) = '0' else
instWord1_s(10 downto 8) when untSel1_n_s(1) = '0' else
(others => '0');
ldstSrc <= instWord0_s(7 downto 0) when untSel0_n_s(1) = '0' else
instWord1_s(7 downto 0) when untSel1_n_s(1) = '0' else
(others => '0');
 
jmpAs <= instWord0_s(12 downto 11) when untSel0_n_s(0) = '0' else
instWord1_s(12 downto 11) when untSel1_n_s(0) = '0' else
(others => '0');
jmpDstReg <= instWord0_s(10 downto 0) when untSel0_n_s(0) = '0' else
instWord1_s(10 downto 0) when untSel1_n_s(0) = '0' else
(others => '0');
end behavior;
 
jmpEn_n_s <= '0' when (untSel0_n_s(0) = '0' or untSel1_n_s(0) = '0') and cnt_s(1) = '1' else
'1';
ldstEn_n_s <= '0' when (untSel0_n_s(1) = '0' or untSel1_n_s(1) = '0') and cnt_s(1) = '1' else
'1';
aluEn_n_s <= '0' when (untSel0_n_s(2) = '0' or untSel1_n_s(2) = '0') and cnt_s(1) = '1' else
'1';
 
instWord0_s <= instData(31 downto 16);
instWord1_s <= instData(15 downto 0);
aluOpCode <= instWord0_s(15 downto 13) when untSel0_n_s(2) = '0' else
instWord1_s(15 downto 13) when untSel1_n_s(2) = '0' else
(others => '0');
aluAs <= instWord0_s(12 downto 11) when untSel0_n_s(2) = '0' else
instWord1_s(12 downto 11) when untSel1_n_s(2) = '0' else
(others => '0');
aluDstReg <= instWord0_s(10 downto 8) when untSel0_n_s(2) = '0' else
instWord1_s(10 downto 8) when untSel1_n_s(2) = '0' else
(others => '0');
aluSrc <= instWord0_s(7 downto 0) when untSel0_n_s(2) = '0' else
instWord1_s(7 downto 0) when untSel1_n_s(2) = '0' else
(others => '0');
 
ldstOpCode <= instWord0_s(13) when untSel0_n_s(1) = '0' else
instWord1_s(13) when untSel1_n_s(1) = '0' else
'0';
ldstAs <= instWord0_s(12 downto 11) when untSel0_n_s(1) = '0' else
instWord1_s(12 downto 11) when untSel1_n_s(1) = '0' else
(others => '0');
ldstDstReg <= instWord0_s(10 downto 8) when untSel0_n_s(1) = '0' else
instWord1_s(10 downto 8) when untSel1_n_s(1) = '0' else
(others => '0');
ldstSrc <= instWord0_s(7 downto 0) when untSel0_n_s(1) = '0' else
instWord1_s(7 downto 0) when untSel1_n_s(1) = '0' else
(others => '0');
 
jmpAs <= instWord0_s(12 downto 11) when untSel0_n_s(0) = '0' else
instWord1_s(12 downto 11) when untSel1_n_s(0) = '0' else
(others => '0');
jmpDstReg <= instWord0_s(10 downto 0) when untSel0_n_s(0) = '0' else
instWord1_s(10 downto 0) when untSel1_n_s(0) = '0' else
(others => '0');
end behavior;
/trunk/src/vhdl/proc/vliwProc.vhd
1,16 → 1,16
-----------------------------------------------------------------
--
-- Design: tinyVLIW8 soft-core processor
-------------------------------------------------------------------------------
--
-- Design: tinyVLIW8 soft-core processor
-- Author: Oliver Stecklina <stecklina@ihp-microelectronics.com>
-- Date: 24.10.2013
-- File: vliwProc.vhd
--
-----------------------------------------------------------------
--
--
-------------------------------------------------------------------------------
--
-- Description : This unit is the VLIW processor core.
--
-----------------------------------------------------------------
--
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2015 IHP GmbH, Frankfurt (Oder), Germany
--
-- This code is free software. It is licensed under the EUPL, Version 1.1
28,144 → 28,144
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-----------------------------------------------------------------
 
library ieee;
--
-------------------------------------------------------------------------------
 
library ieee;
 
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity vliwProc is
port (
-- clock input
clk : in std_logic;
 
-- instruction bus
instMemAddr : out std_logic_vector(10 downto 0);
instMemDataIn : in std_logic_vector(31 downto 0);
instMemEn_n : out std_logic;
-- IO bus
ioMemAddr : out std_logic_vector(7 downto 0);
ioMemDataOut : out std_logic_vector(7 downto 0);
ioMemDataIn : in std_logic_vector(7 downto 0);
ioMemWr_n : out std_logic;
ioMemEn_n : out std_logic;
 
-- IO bus
dataMemAddr : out std_logic_vector(7 downto 0);
dataMemDataOut : out std_logic_vector(7 downto 0);
dataMemDataIn : in std_logic_vector(7 downto 0);
dataMemWr_n : out std_logic;
dataMemEn_n : out std_logic;
 
-- interrupt handling
irqLine : in std_logic_vector(4 downto 0);
irqLineAck : out std_logic_vector(4 downto 0);
-- irqEn : out std_logic;
-- process stall signals and stall acknowledgment
stall_n : in std_logic;
stalled_n : out std_logic;
-- reset input
rst_n : in std_logic
port (
-- clock input
clk : in std_logic;
 
-- instruction bus
instMemAddr : out std_logic_vector(10 downto 0);
instMemDataIn : in std_logic_vector(31 downto 0);
instMemEn_n : out std_logic;
-- IO bus
ioMemAddr : out std_logic_vector(7 downto 0);
ioMemDataOut : out std_logic_vector(7 downto 0);
ioMemDataIn : in std_logic_vector(7 downto 0);
ioMemWr_n : out std_logic;
ioMemEn_n : out std_logic;
 
-- IO bus
dataMemAddr : out std_logic_vector(7 downto 0);
dataMemDataOut : out std_logic_vector(7 downto 0);
dataMemDataIn : in std_logic_vector(7 downto 0);
dataMemWr_n : out std_logic;
dataMemEn_n : out std_logic;
 
-- interrupt handling
irqLine : in std_logic_vector(4 downto 0);
irqLineAck : out std_logic_vector(4 downto 0);
-- irqEn : out std_logic;
-- process stall signals and stall acknowledgment
stall_n : in std_logic;
stalled_n : out std_logic;
-- reset input
rst_n : in std_logic
);
end vliwProc;
architecture behavior of vliwProc is
 
component vliwProc_instDecoder
port (
clk : in std_logic;
instData : in std_logic_vector(31 downto 0);
 
ldstOpCode : out std_logic;
ldstAs : out std_logic_vector(1 downto 0);
ldstDstReg : out std_logic_vector(2 downto 0);
ldstSrc : out std_logic_vector(7 downto 0);
ldstEn_n : out std_logic;
 
aluOpCode : out std_logic_vector(2 downto 0);
aluAs : out std_logic_vector(1 downto 0);
aluDstReg : out std_logic_vector(2 downto 0);
aluSrc : out std_logic_vector(7 downto 0);
aluEn_n : out std_logic;
 
jmpAs : out std_logic_vector(1 downto 0);
jmpDstReg : out std_logic_vector(10 downto 0);
jmpEn_n : out std_logic;
 
esb : out std_logic_vector(3 downto 0);
stall_n : in std_logic;
stalled_n : out std_logic;
rst_n : in std_logic
);
end component;
 
architecture behavior of vliwProc is
 
component vliwProc_instDecoder
port (
clk : in std_logic;
instData : in std_logic_vector(31 downto 0);
 
ldstOpCode : out std_logic;
ldstAs : out std_logic_vector(1 downto 0);
ldstDstReg : out std_logic_vector(2 downto 0);
ldstSrc : out std_logic_vector(7 downto 0);
ldstEn_n : out std_logic;
 
aluOpCode : out std_logic_vector(2 downto 0);
aluAs : out std_logic_vector(1 downto 0);
aluDstReg : out std_logic_vector(2 downto 0);
aluSrc : out std_logic_vector(7 downto 0);
aluEn_n : out std_logic;
 
jmpAs : out std_logic_vector(1 downto 0);
jmpDstReg : out std_logic_vector(10 downto 0);
jmpEn_n : out std_logic;
 
esb : out std_logic_vector(3 downto 0);
stall_n : in std_logic;
stalled_n : out std_logic;
rst_n : in std_logic
);
end component;
 
component vliwProc_statusReg
port (
state : in std_logic_vector(3 downto 0);
 
iretEn_n : in std_logic;
ioEn_n : in std_logic;
irqEn : in std_logic;
flagsEn_n : in std_logic;
flagsIn : in std_logic_vector(1 downto 0); -- carry | zero
dataIn : in std_logic_vector(7 downto 0);
dataOut : out std_logic_vector(7 downto 0);
rst_n : in std_logic
port (
state : in std_logic_vector(3 downto 0);
 
iretEn_n : in std_logic;
ioEn_n : in std_logic;
irqEn : in std_logic;
flagsEn_n : in std_logic;
flagsIn : in std_logic_vector(1 downto 0); -- carry | zero
dataIn : in std_logic_vector(7 downto 0);
dataOut : out std_logic_vector(7 downto 0);
rst_n : in std_logic
);
end component;
 
component vliwProc_pcReg
port (
addrOut : out std_logic_vector(10 downto 0);
state : in std_logic_vector(3 downto 0);
stalled_n : in std_logic;
ioAddr : in std_logic_vector(1 downto 0);
ioIn : in std_logic_vector(7 downto 0);
ioOut : out std_logic_vector(7 downto 0);
ioInEn_n : in std_logic;
ioInWr_n : in std_logic;
 
pcLoad_n : out std_logic;
jmpIn : in std_logic_vector(10 downto 0);
jmpInEn_n : in std_logic;
 
irq : in std_logic;
irqAddr : in std_logic_vector(1 downto 0);
 
rst_n : in std_logic
end component;
 
component vliwProc_pcReg
port (
addrOut : out std_logic_vector(10 downto 0);
state : in std_logic_vector(3 downto 0);
stalled_n : in std_logic;
ioAddr : in std_logic_vector(1 downto 0);
ioIn : in std_logic_vector(7 downto 0);
ioOut : out std_logic_vector(7 downto 0);
ioInEn_n : in std_logic;
ioInWr_n : in std_logic;
 
pcLoad_n : out std_logic;
jmpIn : in std_logic_vector(10 downto 0);
jmpInEn_n : in std_logic;
 
irq : in std_logic;
irqAddr : in std_logic_vector(1 downto 0);
 
rst_n : in std_logic
);
end component;
 
end component;
 
component vliwProc_regSet
port (
state : in std_logic_vector(3 downto 0);
port (
state : in std_logic_vector(3 downto 0);
 
reg0 : out std_logic_vector(7 downto 0);
reg1 : out std_logic_vector(7 downto 0);
reg2 : out std_logic_vector(7 downto 0);
reg3 : out std_logic_vector(7 downto 0);
reg4 : out std_logic_vector(7 downto 0);
reg5 : out std_logic_vector(7 downto 0);
reg6 : out std_logic_vector(7 downto 0);
reg7 : out std_logic_vector(7 downto 0);
 
irqEn : in std_logic;
reg0 : out std_logic_vector(7 downto 0);
reg1 : out std_logic_vector(7 downto 0);
reg2 : out std_logic_vector(7 downto 0);
reg3 : out std_logic_vector(7 downto 0);
reg4 : out std_logic_vector(7 downto 0);
reg5 : out std_logic_vector(7 downto 0);
reg6 : out std_logic_vector(7 downto 0);
reg7 : out std_logic_vector(7 downto 0);
 
irqEn : in std_logic;
aluDataIn : in std_logic_vector(7 downto 0);
aluRegSel : in std_logic_vector(2 downto 0);
aluRegEn_n : in std_logic;
174,251 → 174,237
ldstRegSel : in std_logic_vector(2 downto 0);
ldstRegEn_n : in std_logic;
rst_n : in std_logic
rst_n : in std_logic
);
end component;
 
component vliwProc_loadStore
port (
addr : out std_logic_vector(7 downto 0);
dataOut : out std_logic_vector(7 downto 0);
 
ioWr_n : out std_logic;
ioEn_n : out std_logic;
dataWr_n : out std_logic;
dataEn_n : out std_logic;
dataIn : in std_logic_vector(7 downto 0);
ioIn : in std_logic_vector(7 downto 0);
opCode : in std_logic;
as : in std_logic_vector(1 downto 0);
dstReg : in std_logic_vector(2 downto 0);
src : in std_logic_vector(7 downto 0);
cs_n : in std_logic;
state : in std_logic_vector(3 downto 0);
regOut : out std_logic_vector(7 downto 0);
 
reg0 : in std_logic_vector(7 downto 0);
reg1 : in std_logic_vector(7 downto 0);
reg2 : in std_logic_vector(7 downto 0);
reg3 : in std_logic_vector(7 downto 0);
reg4 : in std_logic_vector(7 downto 0);
reg5 : in std_logic_vector(7 downto 0);
reg6 : in std_logic_vector(7 downto 0);
reg7 : in std_logic_vector(7 downto 0);
 
regSel : out std_logic_vector(2 downto 0);
regEn_n : out std_logic;
 
rst_n : in std_logic
);
end component;
 
end component;
 
component vliwProc_loadStore
port (
addr : out std_logic_vector(7 downto 0);
dataOut : out std_logic_vector(7 downto 0);
 
ioWr_n : out std_logic;
ioEn_n : out std_logic;
dataWr_n : out std_logic;
dataEn_n : out std_logic;
dataIn : in std_logic_vector(7 downto 0);
ioIn : in std_logic_vector(7 downto 0);
opCode : in std_logic;
as : in std_logic_vector(1 downto 0);
dstReg : in std_logic_vector(2 downto 0);
src : in std_logic_vector(7 downto 0);
cs_n : in std_logic;
state : in std_logic_vector(3 downto 0);
regOut : out std_logic_vector(7 downto 0);
 
reg0 : in std_logic_vector(7 downto 0);
reg1 : in std_logic_vector(7 downto 0);
reg2 : in std_logic_vector(7 downto 0);
reg3 : in std_logic_vector(7 downto 0);
reg4 : in std_logic_vector(7 downto 0);
reg5 : in std_logic_vector(7 downto 0);
reg6 : in std_logic_vector(7 downto 0);
reg7 : in std_logic_vector(7 downto 0);
 
regSel : out std_logic_vector(2 downto 0);
regEn_n : out std_logic;
 
rst_n : in std_logic
);
end component;
 
component vliwProc_jmpExec
port (
en_n : in std_logic;
esb : in std_logic_vector(3 downto 0);
dst : in std_logic_vector(10 downto 0);
as : in std_logic_vector(1 downto 0);
 
jmpDst : out std_logic_vector(10 downto 0);
jmpEn_n : out std_logic;
 
cz : in std_logic_vector(1 downto 0);
rst_n : in std_logic
);
end component;
 
port (
en_n : in std_logic;
esb : in std_logic_vector(3 downto 0);
dst : in std_logic_vector(10 downto 0);
as : in std_logic_vector(1 downto 0);
 
jmpDst : out std_logic_vector(10 downto 0);
jmpEn_n : out std_logic;
 
cz : in std_logic_vector(1 downto 0);
rst_n : in std_logic
);
end component;
 
component vliwProc_alu
port (
state : in std_logic_vector(3 downto 0);
 
enable_n : in std_logic;
opcode : in std_logic_vector(2 downto 0);
as : in std_logic_vector(1 downto 0);
dstRegIn : in std_logic_vector(2 downto 0);
dataIn : in std_logic_vector(7 downto 0);
 
reg0 : in std_logic_vector(7 downto 0);
reg1 : in std_logic_vector(7 downto 0);
reg2 : in std_logic_vector(7 downto 0);
reg3 : in std_logic_vector(7 downto 0);
reg4 : in std_logic_vector(7 downto 0);
reg5 : in std_logic_vector(7 downto 0);
reg6 : in std_logic_vector(7 downto 0);
reg7 : in std_logic_vector(7 downto 0);
cIn : in std_logic;
cOut : out std_logic;
zOut : out std_logic;
dstRegEn_n : out std_logic;
dstRegOut : out std_logic_vector(2 downto 0);
dataOut : out std_logic_vector(7 downto 0);
rst_n : in std_logic
port (
state : in std_logic_vector(3 downto 0);
 
enable_n : in std_logic;
opcode : in std_logic_vector(2 downto 0);
as : in std_logic_vector(1 downto 0);
dstRegIn : in std_logic_vector(2 downto 0);
dataIn : in std_logic_vector(7 downto 0);
 
reg0 : in std_logic_vector(7 downto 0);
reg1 : in std_logic_vector(7 downto 0);
reg2 : in std_logic_vector(7 downto 0);
reg3 : in std_logic_vector(7 downto 0);
reg4 : in std_logic_vector(7 downto 0);
reg5 : in std_logic_vector(7 downto 0);
reg6 : in std_logic_vector(7 downto 0);
reg7 : in std_logic_vector(7 downto 0);
cIn : in std_logic;
cOut : out std_logic;
zOut : out std_logic;
dstRegEn_n : out std_logic;
dstRegOut : out std_logic_vector(2 downto 0);
dataOut : out std_logic_vector(7 downto 0);
rst_n : in std_logic
);
end component;
 
end component;
 
component vliwProc_irqCntl
port (
state : in std_logic_vector(3 downto 0);
stalled_n : in std_logic;
 
irqLineIn : in std_logic_vector(5 downto 0);
irqLineOut : out std_logic_vector(5 downto 0);
irqAck : out std_logic;
 
irqAddr : out std_logic_vector(1 downto 0);
 
ioDataIn : in std_logic_vector(7 downto 0);
ioDataOut : out std_logic_vector(7 downto 0);
ioInEn_n : in std_logic;
ioInWr_n : in std_logic;
 
enable : in std_logic;
-- reset input
rst_n : in std_logic
port (
state : in std_logic_vector(3 downto 0);
stalled_n : in std_logic;
 
irqLineIn : in std_logic_vector(5 downto 0);
irqLineOut : out std_logic_vector(5 downto 0);
irqAck : out std_logic;
 
irqAddr : out std_logic_vector(1 downto 0);
 
ioDataIn : in std_logic_vector(7 downto 0);
ioDataOut : out std_logic_vector(7 downto 0);
ioInEn_n : in std_logic;
ioInWr_n : in std_logic;
 
enable : in std_logic;
-- reset input
rst_n : in std_logic
);
end component;
signal rst_n_s : std_logic;
signal stall_n_s : std_logic;
signal stalled_n_s : std_logic;
 
signal instAddr_s : std_logic_vector(10 downto 0);
signal instDataIn_s : std_logic_vector(31 downto 0);
signal pcReg_ioOut_s : std_logic_vector(7 downto 0);
signal pcReg_ioInEn_n_s : std_logic;
signal pcReg_ioInWr_n_s : std_logic;
signal dataAddr_s : std_logic_vector(7 downto 0);
 
signal ioDataIn_s : std_logic_vector(7 downto 0);
signal ioWr_n_s : std_logic;
signal ioEn_n_s : std_logic;
signal dataOut_s : std_logic_vector(7 downto 0);
signal dataIn_s : std_logic_vector(7 downto 0);
signal dataWr_n_s : std_logic;
signal dataEn_n_s : std_logic;
 
signal ldstOpCode_s : std_logic;
signal ldstAs_s : std_logic_vector(1 downto 0);
signal ldstDstReg_s : std_logic_vector(2 downto 0);
signal ldstSrc_s : std_logic_vector(7 downto 0);
signal ldstEn_n_s : std_logic;
 
signal aluOpCode_s : std_logic_vector(2 downto 0);
signal aluAs_s : std_logic_vector(1 downto 0);
signal aluDstReg_s : std_logic_vector(2 downto 0);
signal aluSrc_s : std_logic_vector(7 downto 0);
signal aluEn_n_s : std_logic;
 
signal jmpAs_s : std_logic_vector(1 downto 0);
signal jmpDstReg_s : std_logic_vector(10 downto 0);
signal jmpEn_n_s : std_logic;
signal state_s : std_logic_vector(3 downto 0);
signal reg0_s : std_logic_vector(7 downto 0);
signal reg1_s : std_logic_vector(7 downto 0);
signal reg2_s : std_logic_vector(7 downto 0);
signal reg3_s : std_logic_vector(7 downto 0);
signal reg4_s : std_logic_vector(7 downto 0);
signal reg5_s : std_logic_vector(7 downto 0);
signal reg6_s : std_logic_vector(7 downto 0);
signal reg7_s : std_logic_vector(7 downto 0);
 
signal ldStRegSel_s : std_logic_vector(2 downto 0);
signal ldStRegOut_s : std_logic_vector(7 downto 0);
signal ldStRegEn_n_s : std_logic;
signal ldstIoEnOut_n_s : std_logic;
signal ldstIoWrOut_n_s : std_logic;
signal ldstRst_n_s : std_logic;
signal aluRegEn_n_s : std_logic;
signal aluFlags_s : std_logic_vector(1 downto 0);
signal aluRegSel_s : std_logic_vector(2 downto 0);
signal aluRegOut_s : std_logic_vector(7 downto 0);
 
signal pcLoad_n_s : std_logic;
signal jmpOutEn_n_s : std_logic;
signal jmpAddr_s : std_logic_vector(10 downto 0);
signal irqAck_s : std_logic;
signal irqAddr_s : std_logic_vector(1 downto 0);
signal irqLine_s : std_logic_vector(5 downto 0);
signal irqLineAck_s : std_logic_vector(5 downto 0);
signal irq_ioOut_s : std_logic_vector(7 downto 0);
signal irq_ioInEn_n_s : std_logic;
signal irq_ioInWr_n_s : std_logic;
 
signal statusRegData_s : std_logic_vector(7 downto 0);
signal statusRegIoEn_n_s : std_logic;
signal instMemEn_n_s : std_logic;
signal instMemClk_s : std_logic;
begin
 
rst_n_s <= rst_n;
stall_n_s <= stall_n and not(statusRegData_s(7));
stalled_n <= stalled_n_s;
instMemAddr <= instAddr_s;
instMemEn_n <= instMemEn_n_s;
instDataIn_s <= instMemDataIn;
 
-- irqEn <= statusRegData_s(0);
instMemEn_n_s <= '1' when rst_n = '0' or state_s(3) = '1' or
(stall_n_s = '0') else
signal rst_n_s : std_logic;
signal stall_n_s : std_logic;
signal stalled_n_s : std_logic;
 
signal instAddr_s : std_logic_vector(10 downto 0);
signal instDataIn_s : std_logic_vector(31 downto 0);
signal pcReg_ioOut_s : std_logic_vector(7 downto 0);
signal pcReg_ioInEn_n_s : std_logic;
signal pcReg_ioInWr_n_s : std_logic;
signal dataAddr_s : std_logic_vector(7 downto 0);
 
signal ioDataIn_s : std_logic_vector(7 downto 0);
signal ioWr_n_s : std_logic;
signal ioEn_n_s : std_logic;
signal dataOut_s : std_logic_vector(7 downto 0);
signal dataIn_s : std_logic_vector(7 downto 0);
signal dataWr_n_s : std_logic;
signal dataEn_n_s : std_logic;
 
signal ldstOpCode_s : std_logic;
signal ldstAs_s : std_logic_vector(1 downto 0);
signal ldstDstReg_s : std_logic_vector(2 downto 0);
signal ldstSrc_s : std_logic_vector(7 downto 0);
signal ldstEn_n_s : std_logic;
 
signal aluOpCode_s : std_logic_vector(2 downto 0);
signal aluAs_s : std_logic_vector(1 downto 0);
signal aluDstReg_s : std_logic_vector(2 downto 0);
signal aluSrc_s : std_logic_vector(7 downto 0);
signal aluEn_n_s : std_logic;
 
signal jmpAs_s : std_logic_vector(1 downto 0);
signal jmpDstReg_s : std_logic_vector(10 downto 0);
signal jmpEn_n_s : std_logic;
signal state_s : std_logic_vector(3 downto 0);
signal reg0_s : std_logic_vector(7 downto 0);
signal reg1_s : std_logic_vector(7 downto 0);
signal reg2_s : std_logic_vector(7 downto 0);
signal reg3_s : std_logic_vector(7 downto 0);
signal reg4_s : std_logic_vector(7 downto 0);
signal reg5_s : std_logic_vector(7 downto 0);
signal reg6_s : std_logic_vector(7 downto 0);
signal reg7_s : std_logic_vector(7 downto 0);
 
signal ldStRegSel_s : std_logic_vector(2 downto 0);
signal ldStRegOut_s : std_logic_vector(7 downto 0);
signal ldStRegEn_n_s : std_logic;
signal ldstIoEnOut_n_s : std_logic;
signal ldstIoWrOut_n_s : std_logic;
signal ldstRst_n_s : std_logic;
signal aluRegEn_n_s : std_logic;
signal aluFlags_s : std_logic_vector(1 downto 0);
signal aluRegSel_s : std_logic_vector(2 downto 0);
signal aluRegOut_s : std_logic_vector(7 downto 0);
 
signal pcLoad_n_s : std_logic;
signal jmpOutEn_n_s : std_logic;
signal jmpAddr_s : std_logic_vector(10 downto 0);
signal irqAck_s : std_logic;
signal irqAddr_s : std_logic_vector(1 downto 0);
signal irqLine_s : std_logic_vector(5 downto 0);
signal irqLineAck_s : std_logic_vector(5 downto 0);
signal irq_ioOut_s : std_logic_vector(7 downto 0);
signal irq_ioInEn_n_s : std_logic;
signal irq_ioInWr_n_s : std_logic;
 
signal statusRegData_s : std_logic_vector(7 downto 0);
signal statusRegIoEn_n_s : std_logic;
signal instMemEn_n_s : std_logic;
signal instMemClk_s : std_logic;
begin
 
rst_n_s <= rst_n;
stall_n_s <= stall_n and not(statusRegData_s(7));
stalled_n <= stalled_n_s;
instMemAddr <= instAddr_s;
instMemEn_n <= instMemEn_n_s;
instDataIn_s <= instMemDataIn;
 
-- irqEn <= statusRegData_s(0);
instMemEn_n_s <= '1' when rst_n = '0' or state_s(3) = '1' or (stall_n_s = '0') else
'0';
-- instMemClk_s <= '1' when state_s(0) = '1' or state_s(2) = '1' else
-- '0';
-- stateGen_proc : process(rst_n, instMemClk_s)
-- begin
-- if (rst_n = '0') then
-- instMemEn_n_s <= '1';
-- else
-- if (instMemClk_s'event and instMemClk_s = '1') then
-- instMemEn_n_s <= not(instMemEn_n_s);
-- end if;
-- end if;
-- end process;
------------------------------------------------------------------------------------------
--
 
------------------------------------------------------------------------------------------
--
-- register Set
--
------------------------------------------------------------------------------------------
--
------------------------------------------------------------------------------------------
vliwProc_regSet_i : vliwProc_regSet
port map (
state => state_s,
reg0 => reg0_s,
reg1 => reg1_s,
reg2 => reg2_s,
reg3 => reg3_s,
reg4 => reg4_s,
reg5 => reg5_s,
reg6 => reg6_s,
reg7 => reg7_s,
port map (
state => state_s,
reg0 => reg0_s,
reg1 => reg1_s,
reg2 => reg2_s,
reg3 => reg3_s,
reg4 => reg4_s,
reg5 => reg5_s,
reg6 => reg6_s,
reg7 => reg7_s,
aluDataIn => aluRegOut_s,
aluRegSel => aluRegSel_s,
aluRegEn_n => aluRegEn_n_s,
427,235 → 413,235
ldstRegSel => ldStRegSel_s,
ldstRegEn_n => ldstRegEn_n_s,
irqEn => statusRegData_s(0),
irqEn => statusRegData_s(0),
rst_n => rst_n_s
);
rst_n => rst_n_s
);
 
statusRegIoEn_n_s <= '0' when state_s(3) = '1' and ioWr_n_s = '0' and ioEn_n_s = '0' and dataAddr_s(7 downto 0) = "00000000" else
'1';
statusRegIoEn_n_s <= '0' when state_s(3) = '1' and ioWr_n_s = '0' and ioEn_n_s = '0' and dataAddr_s(7 downto 0) = "00000000" else
'1';
vliwProc_statusReg_i : vliwProc_statusReg
port map (
state => state_s,
iretEn_n => pcLoad_n_s,
ioEn_n => statusRegIoEn_n_s,
irqEn => irqAck_s,
flagsEn_n => aluRegEn_n_s,
flagsIn => aluFlags_s,
dataIn => dataOut_s,
dataOut => statusRegData_s,
port map (
state => state_s,
rst_n => rst_n_s
);
 
pcReg_ioInEn_n_s <= '0' when ioEn_n_s = '0' and dataAddr_s(7 downto 2) = "000100" else
'1';
pcReg_ioInWr_n_s <= '0' when ioWr_n_s = '0' and pcReg_ioInEn_n_s = '0' else
'1';
vliwProc_pcReg_i : vliwProc_pcReg
port map (
addrOut => instAddr_s,
state => state_s,
stalled_n => stalled_n_s,
ioAddr => dataAddr_s(1 downto 0),
ioIn => dataOut_s,
ioOut => pcReg_ioOut_s,
ioInEn_n => pcReg_ioInEn_n_s,
ioInWr_n => pcReg_ioInWr_n_s,
pcLoad_n => pcLoad_n_s,
jmpIn => jmpAddr_s,
jmpInEn_n => jmpOutEn_n_s,
 
irq => irqAck_s,
irqAddr => irqAddr_s,
rst_n => rst_n_s
);
iretEn_n => pcLoad_n_s,
ioEn_n => statusRegIoEn_n_s,
irqEn => irqAck_s,
flagsEn_n => aluRegEn_n_s,
flagsIn => aluFlags_s,
dataIn => dataOut_s,
dataOut => statusRegData_s,
rst_n => rst_n_s
);
 
pcReg_ioInEn_n_s <= '0' when ioEn_n_s = '0' and dataAddr_s(7 downto 2) = "000100" else
'1';
pcReg_ioInWr_n_s <= '0' when ioWr_n_s = '0' and pcReg_ioInEn_n_s = '0' else
'1';
vliwProc_pcReg_i : vliwProc_pcReg
port map (
addrOut => instAddr_s,
state => state_s,
stalled_n => stalled_n_s,
ioAddr => dataAddr_s(1 downto 0),
ioIn => dataOut_s,
ioOut => pcReg_ioOut_s,
ioInEn_n => pcReg_ioInEn_n_s,
ioInWr_n => pcReg_ioInWr_n_s,
pcLoad_n => pcLoad_n_s,
jmpIn => jmpAddr_s,
jmpInEn_n => jmpOutEn_n_s,
 
irq => irqAck_s,
irqAddr => irqAddr_s,
rst_n => rst_n_s
);
vliwProc_jmpExec_i : vliwProc_jmpExec
port map (
en_n => jmpEn_n_s,
esb => state_s,
dst => jmpDstReg_s,
as => jmpAs_s,
 
jmpDst => jmpAddr_s,
jmpEn_n => jmpOutEn_n_s,
 
cz => statusRegData_s(5 downto 4),
rst_n => rst_n_s
);
 
vliwProc_instDecoder_i : vliwProc_instDecoder
port map (
clk => clk,
esb => state_s,
instData => instDataIn_s,
 
ldstOpCode => ldstOpCode_s,
ldstAs => ldstAs_s,
ldstDstReg => ldstDstReg_s,
ldstSrc => ldstSrc_s,
ldstEn_n => ldstEn_n_s,
 
aluOpCode => aluOpCode_s,
aluAs => aluAs_s,
aluDstReg => aluDstReg_s,
aluSrc => aluSrc_s,
aluEn_n => aluEn_n_s,
 
jmpAs => jmpAs_s,
jmpDstReg => jmpDstReg_s,
jmpEn_n => jmpEn_n_s,
 
stall_n => stall_n_s,
stalled_n => stalled_n_s,
 
rst_n => rst_n_s
);
 
ioMemAddr <= dataAddr_s;
ioMemDataOut <= dataOut_s;
ioDataIn_s <= statusRegData_s when dataAddr_s(7 downto 0) = "00000000" else
irq_ioOut_s when irq_ioInEn_n_s = '0' else
pcReg_ioOut_s when pcReg_ioInEn_n_s = '0' else
ioMemDataIn;
ioMemWr_n <= ioWr_n_s when state_s(3) = '1' else
'1';
ioMemEn_n <= ioEn_n_s;
 
dataMemAddr <= dataAddr_s;
dataMemDataOut <= dataOut_s;
dataIn_s <= dataMemDataIn;
dataMemWr_n <= dataWr_n_s when state_s(3) = '1' else
'1';
dataMemEn_n <= dataEn_n_s;
ioWr_n_s <= ldstIoWrOut_n_s when rst_n_s = '1' and stalled_n_s = '1' else
'1';
ioEn_n_s <= ldstIoEnOut_n_s when rst_n_s = '1' and stalled_n_s = '1' else
'1';
port map (
en_n => jmpEn_n_s,
esb => state_s,
dst => jmpDstReg_s,
as => jmpAs_s,
 
jmpDst => jmpAddr_s,
jmpEn_n => jmpOutEn_n_s,
 
cz => statusRegData_s(5 downto 4),
rst_n => rst_n_s
);
 
vliwProc_instDecoder_i : vliwProc_instDecoder
port map (
clk => clk,
esb => state_s,
instData => instDataIn_s,
 
ldstOpCode => ldstOpCode_s,
ldstAs => ldstAs_s,
ldstDstReg => ldstDstReg_s,
ldstSrc => ldstSrc_s,
ldstEn_n => ldstEn_n_s,
 
aluOpCode => aluOpCode_s,
aluAs => aluAs_s,
aluDstReg => aluDstReg_s,
aluSrc => aluSrc_s,
aluEn_n => aluEn_n_s,
 
jmpAs => jmpAs_s,
jmpDstReg => jmpDstReg_s,
jmpEn_n => jmpEn_n_s,
 
stall_n => stall_n_s,
stalled_n => stalled_n_s,
 
rst_n => rst_n_s
);
 
ioMemAddr <= dataAddr_s;
ioMemDataOut <= dataOut_s;
ioDataIn_s <= statusRegData_s when dataAddr_s(7 downto 0) = "00000000" else
irq_ioOut_s when irq_ioInEn_n_s = '0' else
pcReg_ioOut_s when pcReg_ioInEn_n_s = '0' else
ioMemDataIn;
ioMemWr_n <= ioWr_n_s when state_s(3) = '1' else
'1';
ioMemEn_n <= ioEn_n_s;
 
dataMemAddr <= dataAddr_s;
dataMemDataOut <= dataOut_s;
dataIn_s <= dataMemDataIn;
dataMemWr_n <= dataWr_n_s when state_s(3) = '1' else
'1';
dataMemEn_n <= dataEn_n_s;
ioWr_n_s <= ldstIoWrOut_n_s when rst_n_s = '1' and stalled_n_s = '1' else
'1';
ioEn_n_s <= ldstIoEnOut_n_s when rst_n_s = '1' and stalled_n_s = '1' else
'1';
 
ldstRst_n_s <= rst_n_s and stalled_n_s;
 
vliwProc_loadStore_i : vliwProc_loadStore
vliwProc_loadStore_i : vliwProc_loadStore
port map (
addr => dataAddr_s,
dataIn => dataIn_s,
ioIn => ioDataIn_s,
dataOut => dataOut_s,
 
ioWr_n => ldstIoWrOut_n_s,
ioEn_n => ldstIoEnOut_n_s,
dataWr_n => dataWr_n_s,
dataEn_n => dataEn_n_s,
opCode => ldstOpCode_s,
as => ldstAs_s,
dstReg => ldstDstReg_s,
src => ldstSrc_s,
 
cs_n => ldstEn_n_s,
state => state_s,
regOut => ldStRegOut_s,
 
reg0 => reg0_s,
reg1 => reg1_s,
reg2 => reg2_s,
reg3 => reg3_s,
reg4 => reg4_s,
reg5 => reg5_s,
reg6 => reg6_s,
reg7 => reg7_s,
 
regSel => ldStRegSel_s,
regEn_n => ldStRegEn_n_s,
 
rst_n => ldstRst_n_s
);
 
vliwProc_alu_i : vliwProc_alu
port map (
state => state_s,
 
enable_n => aluEn_n_s,
opcode => aluOpCode_s,
as => aluAs_s,
dstRegIn => aluDstReg_s,
dataIn => aluSrc_s,
 
reg0 => reg0_s,
reg1 => reg1_s,
reg2 => reg2_s,
reg3 => reg3_s,
reg4 => reg4_s,
reg5 => reg5_s,
reg6 => reg6_s,
reg7 => reg7_s,
cIn => statusRegData_s(5),
cOut => aluFlags_s(1),
zOut => aluFlags_s(0),
dstRegEn_n => aluRegEn_n_s,
dstRegOut => aluRegSel_s,
dataOut => aluRegOut_s,
rst_n => rst_n_s
);
 
------------------------------------------------------------------------------------------
--
-- Interrupt handler
--
------------------------------------------------------------------------------------------
irqLine_s <= '0' & irqLine;
irqLineAck <= irqLineAck_s(4 downto 0);
irq_ioInEn_n_s <= '0' when ioEn_n_s = '0' and dataAddr_s(7 downto 0) = "00000001" else
'1';
irq_ioInWr_n_s <= '0' when ioWr_n_s = '0' and irq_ioInEn_n_s = '0' else
'1';
 
addr => dataAddr_s,
dataIn => dataIn_s,
ioIn => ioDataIn_s,
dataOut => dataOut_s,
 
ioWr_n => ldstIoWrOut_n_s,
ioEn_n => ldstIoEnOut_n_s,
dataWr_n => dataWr_n_s,
dataEn_n => dataEn_n_s,
opCode => ldstOpCode_s,
as => ldstAs_s,
dstReg => ldstDstReg_s,
src => ldstSrc_s,
 
cs_n => ldstEn_n_s,
state => state_s,
regOut => ldStRegOut_s,
 
reg0 => reg0_s,
reg1 => reg1_s,
reg2 => reg2_s,
reg3 => reg3_s,
reg4 => reg4_s,
reg5 => reg5_s,
reg6 => reg6_s,
reg7 => reg7_s,
 
regSel => ldStRegSel_s,
regEn_n => ldStRegEn_n_s,
 
rst_n => ldstRst_n_s
);
 
vliwProc_alu_i : vliwProc_alu
port map (
state => state_s,
 
enable_n => aluEn_n_s,
opcode => aluOpCode_s,
as => aluAs_s,
dstRegIn => aluDstReg_s,
dataIn => aluSrc_s,
 
reg0 => reg0_s,
reg1 => reg1_s,
reg2 => reg2_s,
reg3 => reg3_s,
reg4 => reg4_s,
reg5 => reg5_s,
reg6 => reg6_s,
reg7 => reg7_s,
cIn => statusRegData_s(5),
cOut => aluFlags_s(1),
zOut => aluFlags_s(0),
dstRegEn_n => aluRegEn_n_s,
dstRegOut => aluRegSel_s,
dataOut => aluRegOut_s,
rst_n => rst_n_s
);
 
------------------------------------------------------------------------------------------
--
-- Interrupt handler
--
------------------------------------------------------------------------------------------
irqLine_s <= '0' & irqLine;
irqLineAck <= irqLineAck_s(4 downto 0);
irq_ioInEn_n_s <= '0' when ioEn_n_s = '0' and dataAddr_s(7 downto 0) = "00000001" else
'1';
irq_ioInWr_n_s <= '0' when ioWr_n_s = '0' and irq_ioInEn_n_s = '0' else
'1';
 
vliwProc_irqCntl_i : vliwProc_irqCntl
port map (
state => state_s,
stalled_n => stalled_n_s,
 
irqLineIn => irqLine_s,
irqLineOut => irqLineAck_s,
irqAck => irqAck_s,
irqAddr => irqAddr_s,
ioDataIn => dataOut_s,
ioDataOut => irq_ioOut_s,
ioInEn_n => irq_ioInEn_n_s,
ioInWr_n => irq_ioInWr_n_s,
 
enable => statusRegData_s(3),
 
rst_n => rst_n_s
port map (
state => state_s,
stalled_n => stalled_n_s,
 
irqLineIn => irqLine_s,
irqLineOut => irqLineAck_s,
irqAck => irqAck_s,
irqAddr => irqAddr_s,
ioDataIn => dataOut_s,
ioDataOut => irq_ioOut_s,
ioInEn_n => irq_ioInEn_n_s,
ioInWr_n => irq_ioInWr_n_s,
 
enable => statusRegData_s(3),
 
rst_n => rst_n_s
);
end behavior;
end behavior;
/trunk/src/vhdl/proc/regSet.vhd
1,3 → 1,37
-------------------------------------------------------------------------------
--
-- Design: tinyVLIW8 soft-core processor
-- Author: Oliver Stecklina <stecklina@ihp-microelectronics.com>
-- Date: 24.10.2013
-- File: regSet.vhd
--
-------------------------------------------------------------------------------
--
-- Description : This unit is the register set unit of the 8-bit tinyVLIW8
-- vliw processor.
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2015 IHP GmbH, Frankfurt (Oder), Germany
--
-- This code is free software. It is licensed under the EUPL, Version 1.1
-- or - as soon they will be approved by the European Commission - subsequent
-- versions of the EUPL (the "License").
-- You may redistribute this code and/or modify it under the terms of this
-- License.
-- You may not use this work except in compliance with the License.
-- You may obtain a copy of the License at:
--
-- http://joinup.ec.europa.eu/software/page/eupl/licence-eupl
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" basis,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
35,6 → 69,8
signal irqReg1_s : std_logic_vector(7 downto 0);
signal irqReg2_s : std_logic_vector(7 downto 0);
signal irqReg3_s : std_logic_vector(7 downto 0);
signal irqReg4_s : std_logic_vector(7 downto 0);
signal irqReg5_s : std_logic_vector(7 downto 0);
 
signal reg0_s : std_logic_vector(7 downto 0);
signal reg1_s : std_logic_vector(7 downto 0);
105,6 → 141,8
irqReg1_s <= (others => '0');
irqReg2_s <= (others => '0');
irqReg3_s <= (others => '0');
irqReg4_s <= (others => '0');
irqReg5_s <= (others => '0');
 
reg0_s <= (others => '0');
reg1_s <= (others => '0');
141,9 → 179,17
reg3_s <= aluRegData_s;
end if;
elsif (aluRegSel_s = "100") then
reg4_s <= aluRegData_s;
if (irqEn_s = '1') then
irqReg4_s <= aluRegData_s;
else
reg4_s <= aluRegData_s;
end if;
elsif (aluRegSel_s = "101") then
reg5_s <= aluRegData_s;
if (irqEn_s = '1') then
irqReg5_s <= aluRegData_s;
else
reg5_s <= aluRegData_s;
end if;
elsif (aluRegSel_s = "110") then
reg6_s <= aluRegData_s;
elsif (aluRegSel_s = "111") then
177,9 → 223,17
reg3_s <= ldstRegData_s;
end if;
elsif (ldstRegSel_s = "100") then
reg4_s <= ldstRegData_s;
if (irqEn_s = '1') then
irqReg4_s <= ldstRegData_s;
else
reg4_s <= ldstRegData_s;
end if;
elsif (ldstRegSel_s = "101") then
reg5_s <= ldstRegData_s;
if (irqEn_s = '1') then
irqReg5_s <= ldstRegData_s;
else
reg5_s <= ldstRegData_s;
end if;
elsif (ldstRegSel_s = "110") then
reg6_s <= ldstRegData_s;
elsif (ldstRegSel_s = "111") then
211,8 → 265,10
reg2_s;
reg3 <= irqReg3_s when irqEn_s = '1' else
reg3_s;
reg4 <= reg4_s;
reg5 <= reg5_s;
reg4 <= irqReg4_s when irqEn_s = '1' else
reg4_s;
reg5 <= irqReg5_s when irqEn_s = '1' else
reg5_s;
reg6 <= reg6_s;
reg7 <= reg7_s;
 
/trunk/src/vhdl/proc/irqCntl.vhd
12,11 → 12,11
irqAck : out std_logic;
 
irqAddr : out std_logic_vector(1 downto 0);
ioDataIn : in std_logic_vector(7 downto 0);
ioDataOut : out std_logic_vector(7 downto 0);
ioInEn_n : in std_logic;
ioInWr_n : in std_logic;
ioDataIn : in std_logic_vector(7 downto 0);
ioDataOut : out std_logic_vector(7 downto 0);
ioInEn_n : in std_logic;
ioInWr_n : in std_logic;
 
enable : in std_logic;
29,96 → 29,96
 
signal irq_s : std_logic;
signal irqAck_s : std_logic;
signal irqAddr_s : std_logic_vector(1 downto 0);
signal irqAddr_s : std_logic_vector(1 downto 0);
signal irqLineOut_s : std_logic_vector(3 downto 0);
signal irqLineOut_s : std_logic_vector(3 downto 0);
signal irqLineIn_s : std_logic_vector(3 downto 0);
signal irqLine_s : std_logic;
signal irqUpd_s : std_logic;
signal irqCtrl_r : std_logic_vector(7 downto 0);
signal irqCtrl_r : std_logic_vector(7 downto 0);
begin
 
------------------------------------------------------------------------------------------
--
-- IRQ line multiplexer
--
------------------------------------------------------------------------------------------
 
irqLineIn_s(0) <= '1' when rst_n = '1' and ((irqCtrl_r(1 downto 0) = "01" and irqLineIn(0) = '1') or
(irqCtrl_r(1 downto 0) = "10" and irqLineIn(2) = '1') or
(irqCtrl_r(1 downto 0) = "11" and irqLineIn(5) = '1')) else
'0';
irqLineIn_s(1) <= '1' when rst_n = '1' and ((irqCtrl_r(3 downto 2) = "01" and irqLineIn(4) = '1') or
(irqCtrl_r(3 downto 2) = "10" and irqLineIn(0) = '1') or
(irqCtrl_r(3 downto 2) = "11" and irqLineIn(3) = '1')) else
'0';
irqLineIn_s(2) <= '1' when rst_n = '1' and ((irqCtrl_r(5 downto 4) = "01" and irqLineIn(1) = '1') or
(irqCtrl_r(5 downto 4) = "10" and irqLineIn(4) = '1') or
(irqCtrl_r(5 downto 4) = "11" and irqLineIn(5) = '1')) else
'0';
irqLineIn_s(3) <= '1' when rst_n = '1' and ((irqCtrl_r(7 downto 6) = "01" and irqLineIn(1) = '1') or
(irqCtrl_r(7 downto 6) = "10" and irqLineIn(2) = '1') or
(irqCtrl_r(7 downto 6) = "11" and irqLineIn(3) = '1')) else
'0';
irqLineOut(0) <= '1' when rst_n = '1' and enable = '1' and irq_s = '1' and
((irqCtrl_r(1 downto 0) = "01" and irqLineOut_s(0) = '1') or
(irqCtrl_r(3 downto 2) = "10" and irqLineOut_s(1) = '1')) else
'0';
irqLineOut(1) <= '1' when rst_n = '1' and enable = '1' and irq_s = '1' and
((irqCtrl_r(5 downto 4) = "01" and irqLineOut_s(2) = '1') or
(irqCtrl_r(7 downto 6) = "01" and irqLineOut_s(3) = '1')) else
'0';
irqLineOut(2) <= '1' when rst_n = '1' and enable = '1' and irq_s = '1' and
((irqCtrl_r(1 downto 0) = "10" and irqLineOut_s(0) = '1') or
(irqCtrl_r(7 downto 6) = "10" and irqLineOut_s(3) = '1')) else
'0';
irqLineOut(3) <= '1' when rst_n = '1' and enable = '1' and irq_s = '1' and
((irqCtrl_r(3 downto 2) = "11" and irqLineOut_s(1) = '1') or
(irqCtrl_r(7 downto 6) = "11" and irqLineOut_s(3) = '1')) else
'0';
irqLineOut(4) <= '1' when rst_n = '1' and enable = '1' and irq_s = '1' and
((irqCtrl_r(3 downto 2) = "01" and irqLineOut_s(1) = '1') or
(irqCtrl_r(5 downto 4) = "10" and irqLineOut_s(2) = '1')) else
'0';
irqLineOut(5) <= '1' when rst_n = '1' and enable = '1' and irq_s = '1' and
((irqCtrl_r(1 downto 0) = "11" and irqLineOut_s(0) = '1') or
(irqCtrl_r(5 downto 4) = "11" and irqLineOut_s(2) = '1')) else
'0';
------------------------------------------------------------------------------------------
--
-- Control register
--
------------------------------------------------------------------------------------------
 
ioDataOut <= irqCtrl_r when rst_n = '1' and ioInEn_n = '0' else
(others => '0');
------------------------------------------------------------------------------------------
--
-- IRQ line multiplexer
--
------------------------------------------------------------------------------------------
 
irqLineIn_s(0) <= '1' when rst_n = '1' and ((irqCtrl_r(1 downto 0) = "01" and irqLineIn(0) = '1') or
(irqCtrl_r(1 downto 0) = "10" and irqLineIn(2) = '1') or
(irqCtrl_r(1 downto 0) = "11" and irqLineIn(5) = '1')) else
'0';
irqLineIn_s(1) <= '1' when rst_n = '1' and ((irqCtrl_r(3 downto 2) = "01" and irqLineIn(4) = '1') or
(irqCtrl_r(3 downto 2) = "10" and irqLineIn(0) = '1') or
(irqCtrl_r(3 downto 2) = "11" and irqLineIn(3) = '1')) else
'0';
irqLineIn_s(2) <= '1' when rst_n = '1' and ((irqCtrl_r(5 downto 4) = "01" and irqLineIn(1) = '1') or
(irqCtrl_r(5 downto 4) = "10" and irqLineIn(4) = '1') or
(irqCtrl_r(5 downto 4) = "11" and irqLineIn(5) = '1')) else
'0';
irqLineIn_s(3) <= '1' when rst_n = '1' and ((irqCtrl_r(7 downto 6) = "01" and irqLineIn(1) = '1') or
(irqCtrl_r(7 downto 6) = "10" and irqLineIn(2) = '1') or
(irqCtrl_r(7 downto 6) = "11" and irqLineIn(3) = '1')) else
'0';
irqLineOut(0) <= '1' when rst_n = '1' and enable = '1' and irq_s = '1' and
((irqCtrl_r(1 downto 0) = "01" and irqLineOut_s(0) = '1') or
(irqCtrl_r(3 downto 2) = "10" and irqLineOut_s(1) = '1')) else
'0';
irqLineOut(1) <= '1' when rst_n = '1' and enable = '1' and irq_s = '1' and
((irqCtrl_r(5 downto 4) = "01" and irqLineOut_s(2) = '1') or
(irqCtrl_r(7 downto 6) = "01" and irqLineOut_s(3) = '1')) else
'0';
irqLineOut(2) <= '1' when rst_n = '1' and enable = '1' and irq_s = '1' and
((irqCtrl_r(1 downto 0) = "10" and irqLineOut_s(0) = '1') or
(irqCtrl_r(7 downto 6) = "10" and irqLineOut_s(3) = '1')) else
'0';
irqLineOut(3) <= '1' when rst_n = '1' and enable = '1' and irq_s = '1' and
((irqCtrl_r(3 downto 2) = "11" and irqLineOut_s(1) = '1') or
(irqCtrl_r(7 downto 6) = "11" and irqLineOut_s(3) = '1')) else
'0';
irqLineOut(4) <= '1' when rst_n = '1' and enable = '1' and irq_s = '1' and
((irqCtrl_r(3 downto 2) = "01" and irqLineOut_s(1) = '1') or
(irqCtrl_r(5 downto 4) = "10" and irqLineOut_s(2) = '1')) else
'0';
irqLineOut(5) <= '1' when rst_n = '1' and enable = '1' and irq_s = '1' and
((irqCtrl_r(1 downto 0) = "11" and irqLineOut_s(0) = '1') or
(irqCtrl_r(5 downto 4) = "11" and irqLineOut_s(2) = '1')) else
'0';
------------------------------------------------------------------------------------------
--
-- Control register
--
------------------------------------------------------------------------------------------
 
ioDataOut <= irqCtrl_r when rst_n = '1' and ioInEn_n = '0' else
(others => '0');
update_irqCtrlReg: process(rst_n, ioInWr_n)
begin
if (rst_n = '0') then
if (rst_n = '0') then
irqCtrl_r <= (others => '0');
else
if (ioInWr_n'event and ioInWr_n = '0') then
if (ioInEn_n = '0') then
irqCtrl_r <= ioDataIn;
end if;
end if;
end if;
else
if (ioInWr_n'event and ioInWr_n = '0') then
if (ioInEn_n = '0') then
irqCtrl_r <= ioDataIn;
end if;
end if;
end if;
end process;
 
------------------------------------------------------------------------------------------
--
-- IRQ address generation
--
------------------------------------------------------------------------------------------
 
------------------------------------------------------------------------------------------
--
-- IRQ address generation
--
------------------------------------------------------------------------------------------
 
irqAddr <= irqAddr_s;
irq_proc : process(rst_n, irqUpd_s)
begin
if (rst_n = '0') then
127,7 → 127,7
irqAddr_s <= (others => '0');
irqLineOut_s <= (others => '0');
else
if (irqUpd_s'event and irqUpd_s = '1') then
if (irqUpd_s'event and irqUpd_s = '0') then
if (irqLine_s = '1') then
irq_s <= '1';
154,9 → 154,9
irqLine_s <= irqLineIn_s(0) or irqLineIn_s(1) or irqLineIn_s(2) or irqLineIn_s(3);
irqUpd_s <= state(2) when enable = '1' and stalled_n = '1' else
'1' when enable = '1' and irqLine_s = '1' else
'0';
irqUpd_s <= state(3) when enable = '1' and stalled_n = '1' else
'0' when enable = '1' and irqLine_s = '1' else
'1';
irqAck <= irq_s;
 
/trunk/src/vhdl/sysArch.vhd
1,3 → 1,37
-------------------------------------------------------------------------------
--
-- Design: tinyVLIW8 soft-core processor
-- Author: Oliver Stecklina <stecklina@ihp-microelectronics.com>
-- Date: 24.10.2013
-- File: sysArch.vhd
--
-------------------------------------------------------------------------------
--
-- Description : TinyVLIW8 system architecture includes processor core and
-- GPIO, timer, and SPI periperals
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2015 IHP GmbH, Frankfurt (Oder), Germany
--
-- This code is free software. It is licensed under the EUPL, Version 1.1
-- or - as soon they will be approved by the European Commission - subsequent
-- versions of the EUPL (the "License").
-- You may redistribute this code and/or modify it under the terms of this
-- License.
-- You may not use this work except in compliance with the License.
-- You may obtain a copy of the License at:
--
-- http://joinup.ec.europa.eu/software/page/eupl/licence-eupl
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" basis,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
25,7 → 59,7
ioWrEn_n : out std_logic;
ioRdEn_n : out std_logic;
-- interrupt handling
-- external interrupt handling
irqLine : in std_logic;
irqLineAck : out std_logic;
 
50,39 → 84,25
architecture behavior of sysArch is
 
component SPImaster IS
PORT (
inclk : IN STD_LOGIC; -- system clock
rst_n : IN STD_LOGIC; -- synchr. system reset, high active
-- processor interface
we_n : IN STD_LOGIC; -- write enable, high active
re_n : IN STD_LOGIC; -- read enable, high active
addr : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- address from processor
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);-- data from processor
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-- async. data to processor
intr : OUT STD_LOGIC; -- interrupt to processor, high active
intra : IN STD_LOGIC; -- interrupt to processor, high active
-- SPI interface
SCK : OUT STD_LOGIC; -- SPI clock
SS : OUT STD_LOGIC; -- SPI slave select, active level configurable
MOSI : OUT STD_LOGIC; -- SPI master output, slave input
MISO : IN STD_LOGIC -- SPI master input, slave output
);
PORT (
inclk : IN STD_LOGIC; -- system clock
rst_n : IN STD_LOGIC; -- synchr. system reset, high active
-- processor interface
we_n : IN STD_LOGIC; -- write enable, high active
re_n : IN STD_LOGIC; -- read enable, high active
addr : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- address from processor
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);-- data from processor
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-- async. data to processor
intr : OUT STD_LOGIC; -- interrupt to processor, high active
intra : IN STD_LOGIC; -- interrupt to processor, high active
-- SPI interface
SCK : OUT STD_LOGIC; -- SPI clock
SS : OUT STD_LOGIC; -- SPI slave select, active level configurable
MOSI : OUT STD_LOGIC; -- SPI master output, slave input
MISO : IN STD_LOGIC -- SPI master input, slave output
);
END component;
 
component sha1_ex
PORT(
resetn : IN STD_LOGIC; -- reset the module (low active)
clk : IN STD_LOGIC; -- clock of the sha1
cen : IN STD_LOGIC; -- IO select low active
wen : in std_logic; --- write enable low active
addr : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- address signal
d_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data
intr : OUT STD_LOGIC; -- signalizes if generation finished
intra : IN STD_LOGIC; -- signalizes if generation finished
d_out : out STD_LOGIC_VECTOR(7 DOWNTO 0) -- data
);
end component;
 
component vliwProc
port (
clk : in std_logic;
116,26 → 136,26
 
component ioport
port (
cs_n : IN STD_LOGIC; -- chip select signal
cs_n : IN STD_LOGIC; -- chip select signal
 
clk : IN STD_LOGIC;
clk : IN STD_LOGIC;
 
-- memory interface
mdbwr_n : IN STD_LOGIC; -- write enable signal
mdb_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from data bus
mdb_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to data bus
mab : IN STD_LOGIC_VECTOR(2 downto 0); -- address registers
irq : out std_logic;
irqAck : in std_logic;
-- port interface
PnIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from pad (gpio in)
PnOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to pad (gpio out)
PnOEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- port direction (low active)
-- memory interface
mdbwr_n : IN STD_LOGIC; -- write enable signal
mdb_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from data bus
mdb_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to data bus
mab : IN STD_LOGIC_VECTOR(2 downto 0); -- address registers
 
rst_n : IN STD_LOGIC
);
irq : out std_logic;
irqAck : in std_logic;
 
-- port interface
PnIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from pad (gpio in)
PnOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data to pad (gpio out)
PnOEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- port direction (low active)
rst_n : IN STD_LOGIC
);
end component;
 
component timer
200,16 → 220,10
signal spiIrq_s : std_logic;
signal ioDataSpi_s : std_logic_vector(7 downto 0);
 
-- sha1 signals
signal ioSha1En_n_s : std_logic;
signal sha1Irq_s : std_logic;
signal ioDataSha1_s : std_logic_vector(7 downto 0);
 
-- external io interface
signal ioDataExt_s : std_logic_vector(7 downto 0);
signal ioExtEn_n_s : std_logic;
 
 
begin
 
clk_s <= clk;
221,7 → 235,7
irqLineAck <= irqLineAck_s(0); -- export IRQ 0
irqLine_s <= ioPortIrq_s & timer_irq_s & sha1Irq_s & spiIrq_s & irqLine;
irqLine_s <= ioPortIrq_s & timer_irq_s & '0' & spiIrq_s & irqLine;
instMemAddr <= instAddr_s;
instDataIn_s <= instMemDataIn;
235,9 → 249,8
ioDataIn_s <= ioDataGpio_s when ioPortEn_n_s = '0' else
ioTimerDataOut_s when ioTimerEn_n_s = '0' else
ioDataSpi_s when ioSpiEn_n_s = '0' else
ioDataSha1_s when ioSha1En_n_s = '0' else
ioDataExt_s;
ioDataSpi_s when ioSpiEn_n_s = '0' else
ioDataExt_s;
vliwProc_i : vliwProc
port map (
274,7 → 287,7
spiMaster_i : SPImaster
port map (
inclk => clk_s,
rst_n => rst_n_s,
rst_n => rst_n_s,
 
we_n => ioWr_n_s,
re_n => ioSpiEn_n_s,
282,7 → 295,7
din => ioDataOut_s,
dout => ioDataSpi_s,
intr => spiIrq_s,
intr => spiIrq_s,
intra => irqLineAck_s(1),
 
SCK => spi_clk,
291,44 → 304,28
MISO => spi_miso
);
ioSha1En_n_s <= ioEn_n_s when ioAddr_s(7 downto 2) = "000111" else
'1';
 
sha1_i : sha1_ex
port map (
resetn => rst_n_s,
clk => clk_s,
cen => ioSha1En_n_s,
wen => ioWr_n_s,
addr => ioAddr_s(1 downto 0),
d_in => ioDataOut_s,
intr => sha1Irq_s,
intra => irqLineAck_s(2),
d_out => ioDataSha1_s
);
 
ioPortEn_n_s <= ioEn_n_s when ioAddr_s(7 downto 3) = "00100" else
'1';
 
ioport_i : ioport
port map (
cs_n => ioPortEn_n_s,
clk => clk_s,
cs_n => ioPortEn_n_s,
clk => clk_s,
 
mdbwr_n => ioWr_n_s,
mdb_i => ioDataOut_s,
mdb_o => ioDataGpio_s,
mdbwr_n => ioWr_n_s,
mdb_i => ioDataOut_s,
mdb_o => ioDataGpio_s,
mab => ioAddr_s(2 downto 0),
irq => ioPortIrq_s,
irqAck => irqLineAck_s(4),
irq => ioPortIrq_s,
irqAck => irqLineAck_s(4),
-- port interface
PnIN => gpio_in,
PnOUT => gpio_out,
PnOEN => gpio_dir,
PnIN => gpio_in,
PnOUT => gpio_out,
PnOEN => gpio_dir,
 
rst_n => rst_n_s
rst_n => rst_n_s
);
 
ioTimerEn_n_s <= ioEn_n_s when ioAddr_s(7 downto 3) = "00101" else
353,10 → 350,10
);
 
-- external io interface
ioAddr <= ioAddr_s;
ioDataOut <= ioDataOut_s;
ioAddr <= ioAddr_s;
ioDataOut <= ioDataOut_s;
ioDataExt_s <= ioDataIn;
ioRdEn_n <= ioEn_n_s;
ioWrEn_n <= ioWr_n_s;
ioRdEn_n <= ioEn_n_s;
ioWrEn_n <= ioWr_n_s;
 
end behavior;
/trunk/design/AlteraDK1/AlteraDK1.qsf
41,7 → 41,7
set_global_assignment -name TOP_LEVEL_ENTITY AlteraDK1
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "11.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:41:59 FEBRUARY 24, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION "11.0 SP1"
set_global_assignment -name LAST_QUARTUS_VERSION "11.1 SP2"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
186,26 → 186,32
set_location_assignment PIN_L22 -to sw[0]
set_location_assignment PIN_F14 -to uart0_rxd
set_location_assignment PIN_G12 -to uart0_txd
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VHDL_FILE ../../source/vhdl/vliwProc/vliwProc.vhd
set_global_assignment -name VHDL_FILE ../../source/vhdl/vliwProc/statusReg.vhd
set_global_assignment -name VHDL_FILE ../../source/vhdl/vliwProc/regSet.vhd
set_global_assignment -name VHDL_FILE ../../source/vhdl/vliwProc/pcReg.vhd
set_global_assignment -name VHDL_FILE ../../source/vhdl/vliwProc/loadStore.vhd
set_global_assignment -name VHDL_FILE ../../source/vhdl/vliwProc/jmpExec.vhd
set_global_assignment -name VHDL_FILE ../../source/vhdl/vliwProc/irqCntl.vhd
set_global_assignment -name VHDL_FILE ../../source/vhdl/vliwProc/instDecoder.vhd
set_global_assignment -name VHDL_FILE ../../source/vhdl/vliwProc/alu.vhd
set_global_assignment -name VHDL_FILE ../../source/vhdl/timer.vhd
set_global_assignment -name VHDL_FILE ../../source/vhdl/spiSlave.vhd
set_global_assignment -name VHDL_FILE ../../source/vhdl/ioport.vhd
set_global_assignment -name VHDL_FILE ../../source/vhdl/gendelay.vhd
set_global_assignment -name VHDL_FILE ../../source/vhdl/clock_divider.vhd
set_global_assignment -name VHDL_FILE AlteraDK1.vhd
set_global_assignment -name QIP_FILE dataMem.qip
set_global_assignment -name QIP_FILE instMem.qip
set_global_assignment -name SDC_FILE AlteraDK1.sdc
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name VHDL_FILE AlteraDK1.vhd
set_global_assignment -name QIP_FILE dataMem.qip
set_global_assignment -name QIP_FILE instMem.qip
set_global_assignment -name SDC_FILE AlteraDK1.sdc
set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/vliwProc.vhd
set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/statusReg.vhd
set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/regSet.vhd
set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/pcReg.vhd
set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/loadStore.vhd
set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/jmpExec.vhd
set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/irqCntl.vhd
set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/instDecoder.vhd
set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/alu.vhd
set_global_assignment -name VHDL_FILE ../../src/vhdl/library/latch.vhd
set_global_assignment -name VHDL_FILE ../../src/vhdl/timer.vhd
set_global_assignment -name VHDL_FILE ../../src/vhdl/spiSlave.vhd
set_global_assignment -name VHDL_FILE ../../src/vhdl/spiMaster.vhd
set_global_assignment -name VHDL_FILE ../../src/vhdl/rstCtrl.vhd
set_global_assignment -name VHDL_FILE ../../src/vhdl/ioport.vhd
set_global_assignment -name VHDL_FILE ../../src/vhdl/gendelay.vhd
set_global_assignment -name VHDL_FILE ../../src/vhdl/clock_divider.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
/trunk/design/AlteraDK1/dataMem.qip
1,5 → 1,5
set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "11.0"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dataMem.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dataMem_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dataMem.cmp"]
set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "11.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dataMem.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dataMem_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dataMem.cmp"]
/trunk/design/AlteraDK1/instMem.qip
1,5 → 1,5
set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "11.0"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "instMem.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "instMem_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "instMem.cmp"]
set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "11.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "instMem.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "instMem_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "instMem.cmp"]
/trunk/design/AlteraDK1/dataMem_inst.vhd
1,8 → 1,8
dataMem_inst : dataMem PORT MAP (
address => address_sig,
data => data_sig,
inclock => inclock_sig,
outclock => outclock_sig,
wren => wren_sig,
q => q_sig
);
dataMem_inst : dataMem PORT MAP (
address => address_sig,
data => data_sig,
inclock => inclock_sig,
outclock => outclock_sig,
wren => wren_sig,
q => q_sig
);
/trunk/design/AlteraDK1/dataMem.cmp
1,26 → 1,26
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
component dataMem
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
inclock : IN STD_LOGIC := '1';
outclock : IN STD_LOGIC ;
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component;
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
component dataMem
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
inclock : IN STD_LOGIC := '1';
outclock : IN STD_LOGIC ;
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component;
/trunk/design/AlteraDK1/dataMem.vhd
1,183 → 1,183
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
 
-- ============================================================
-- File Name: dataMem.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.0 Build 208 07/03/2011 SP 1 SJ Web Edition
-- ************************************************************
 
 
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.all;
 
ENTITY dataMem IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
inclock : IN STD_LOGIC := '1';
outclock : IN STD_LOGIC ;
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END dataMem;
 
 
ARCHITECTURE SYN OF datamem IS
 
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
 
 
 
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
 
BEGIN
q <= sub_wire0(7 DOWNTO 0);
 
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK1",
power_up_uninitialized => "FALSE",
widthad_a => 8,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => inclock,
data_a => data,
wren_a => wren,
clock1 => outclock,
q_a => sub_wire0
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "0"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK1"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT VCC "inclock"
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT NODEFVAL "outclock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 inclock 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 outclock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL dataMem.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dataMem.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dataMem.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dataMem.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dataMem_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
 
-- ============================================================
-- File Name: dataMem.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
 
 
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.all;
 
ENTITY dataMem IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
inclock : IN STD_LOGIC := '1';
outclock : IN STD_LOGIC ;
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END dataMem;
 
 
ARCHITECTURE SYN OF datamem IS
 
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
 
 
 
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
 
BEGIN
q <= sub_wire0(7 DOWNTO 0);
 
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK1",
power_up_uninitialized => "FALSE",
widthad_a => 8,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => inclock,
data_a => data,
wren_a => wren,
clock1 => outclock,
q_a => sub_wire0
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "0"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK1"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT VCC "inclock"
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT NODEFVAL "outclock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 inclock 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 outclock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL dataMem.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dataMem.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dataMem.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dataMem.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dataMem_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
/trunk/design/AlteraDK1/instMem_inst.vhd
1,8 → 1,8
instMem_inst : instMem PORT MAP (
address => address_sig,
data => data_sig,
inclock => inclock_sig,
outclock => outclock_sig,
wren => wren_sig,
q => q_sig
);
instMem_inst : instMem PORT MAP (
address => address_sig,
data => data_sig,
inclock => inclock_sig,
outclock => outclock_sig,
wren => wren_sig,
q => q_sig
);
/trunk/design/AlteraDK1/instMem.cmp
1,26 → 1,26
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
component instMem
PORT
(
address : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
inclock : IN STD_LOGIC := '1';
outclock : IN STD_LOGIC ;
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
component instMem
PORT
(
address : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
inclock : IN STD_LOGIC := '1';
outclock : IN STD_LOGIC ;
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
/trunk/design/AlteraDK1/instMem.vhd
1,183 → 1,183
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
 
-- ============================================================
-- File Name: instMem.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.0 Build 208 07/03/2011 SP 1 SJ Web Edition
-- ************************************************************
 
 
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.all;
 
ENTITY instMem IS
PORT
(
address : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
inclock : IN STD_LOGIC := '1';
outclock : IN STD_LOGIC ;
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END instMem;
 
 
ARCHITECTURE SYN OF instmem IS
 
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
 
 
 
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
 
BEGIN
q <= sub_wire0(31 DOWNTO 0);
 
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => 2048,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK1",
power_up_uninitialized => "FALSE",
widthad_a => 11,
width_a => 32,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => inclock,
data_a => data,
wren_a => wren,
clock1 => outclock,
q_a => sub_wire0
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "0"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
-- Retrieval info: PRIVATE: WidthData NUMERIC "32"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK1"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT VCC "inclock"
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT NODEFVAL "outclock"
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 inclock 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 outclock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL instMem.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL instMem.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL instMem.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL instMem.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL instMem_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
 
-- ============================================================
-- File Name: instMem.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
 
 
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.all;
 
ENTITY instMem IS
PORT
(
address : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
inclock : IN STD_LOGIC := '1';
outclock : IN STD_LOGIC ;
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END instMem;
 
 
ARCHITECTURE SYN OF instmem IS
 
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
 
 
 
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
 
BEGIN
q <= sub_wire0(31 DOWNTO 0);
 
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => 2048,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK1",
power_up_uninitialized => "FALSE",
widthad_a => 11,
width_a => 32,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => inclock,
data_a => data,
wren_a => wren,
clock1 => outclock,
q_a => sub_wire0
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "0"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
-- Retrieval info: PRIVATE: WidthData NUMERIC "32"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK1"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT VCC "inclock"
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT NODEFVAL "outclock"
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 inclock 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 outclock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL instMem.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL instMem.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL instMem.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL instMem.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL instMem_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf

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