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doc/LICENSE.txt
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: doc/turbo.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: doc/turbo.pdf
===================================================================
--- doc/turbo.pdf (nonexistent)
+++ doc/turbo.pdf (revision 7)
doc/turbo.pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: doc/README.txt
===================================================================
--- doc/README.txt (nonexistent)
+++ doc/README.txt (revision 7)
@@ -0,0 +1,76 @@
+######################################################################
+#### ####
+#### README.txt ####
+#### ####
+#### This file is part of the turbo decoder IP core project ####
+#### http://www.opencores.org/projects/turbocodes/ ####
+#### ####
+#### Author(s): ####
+#### - David Brochart(dbrochart@opencores.org) ####
+#### ####
+######################################################################
+#### ####
+#### Copyright (C) 2005 Authors ####
+#### ####
+#### This source file may be used and distributed without ####
+#### restriction provided that this copyright statement is not ####
+#### removed from the file and that any derivative work contains ####
+#### the original copyright notice and the associated disclaimer. ####
+#### ####
+#### This source file is free software; you can redistribute it ####
+#### and/or modify it under the terms of the GNU Lesser General ####
+#### Public License as published by the Free Software Foundation; ####
+#### either version 2.1 of the License, or (at your option) any ####
+#### later version. ####
+#### ####
+#### This source is distributed in the hope that it will be ####
+#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
+#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
+#### PURPOSE. See the GNU Lesser General Public License for more ####
+#### details. ####
+#### ####
+#### You should have received a copy of the GNU Lesser General ####
+#### Public License along with this source; if not, download it ####
+#### from http://www.opencores.org/lgpl.shtml ####
+#### ####
+######################################################################
+
+
+
+Turbo Decoder Release 0.3
+=========================
+
+MAIN FEATURES
+-------------
+
+* Double binary, DVB-RCS code
+* Soft Output Viterbi Algorithm
+* MyHDL cycle/bit accurate model
+* Synthesizable VHDL model
+
+MyHDL MODEL
+-----------
+For help : python launchTurbo.py -help
+For default execution : python launchTurbo.py
+It writes the Bit Error Rate for each iteration into a file:
+ turbo0.txt <- BER before decoding
+ turbo1.txt <- BER for iteration #1
+ turbo2.txt <- BER for iteration #2
+ turbo3.txt <- BER for iteration #3
+
+VHDL MODEL
+----------
+The top-level entity is "turboDec".
+All the turbo decoder parameters are stored in the "turbopack.vhd" file.
+You can modify:
+ - the code rate (RATE)
+ - the number of decoding iterations (IT)
+ - the interleaver frame size (FRSIZE)
+ - the trellis' length (TREL1_LEN and TREL2_LEN)
+ - the received decoder signal width (SIG_WIDTH)
+ - the extrinsic information signal width (Z_WIDTH)
+ - the accumulated distance signal width (ACC_DIST_WIDTH)
+
+AUTHOR
+------
+David Brochart
doc/README.txt
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: src/myhdl/synthesis.py
===================================================================
--- src/myhdl/synthesis.py (nonexistent)
+++ src/myhdl/synthesis.py (revision 7)
@@ -0,0 +1,9 @@
+from myhdl import toVHDL, Signal
+from misc import delayer
+
+clk = Signal(bool(0))
+rst = Signal(bool(0))
+d = Signal(bool(0))
+q = Signal(bool(0))
+
+synthesis_i0 = toVHDL(delayer, clk, rst, d, q)
Index: src/myhdl/punct.py
===================================================================
--- src/myhdl/punct.py (nonexistent)
+++ src/myhdl/punct.py (revision 7)
@@ -0,0 +1,123 @@
+######################################################################
+#### ####
+#### punct.py ####
+#### ####
+#### This file is part of the turbo decoder IP core project ####
+#### http://www.opencores.org/projects/turbocodes/ ####
+#### ####
+#### Author(s): ####
+#### - David Brochart(dbrochart@opencores.org) ####
+#### ####
+#### All additional information is available in the README.txt ####
+#### file. ####
+#### ####
+######################################################################
+#### ####
+#### Copyright (C) 2005 Authors ####
+#### ####
+#### This source file may be used and distributed without ####
+#### restriction provided that this copyright statement is not ####
+#### removed from the file and that any derivative work contains ####
+#### the original copyright notice and the associated disclaimer. ####
+#### ####
+#### This source file is free software; you can redistribute it ####
+#### and/or modify it under the terms of the GNU Lesser General ####
+#### Public License as published by the Free Software Foundation; ####
+#### either version 2.1 of the License, or (at your option) any ####
+#### later version. ####
+#### ####
+#### This source is distributed in the hope that it will be ####
+#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
+#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
+#### PURPOSE. See the GNU Lesser General Public License for more ####
+#### details. ####
+#### ####
+#### You should have received a copy of the GNU Lesser General ####
+#### Public License along with this source; if not, download it ####
+#### from http://www.opencores.org/lgpl.shtml ####
+#### ####
+######################################################################
+
+
+
+from myhdl import Signal, intbv, always_comb, always, posedge, negedge
+
+def punct(clk, rst, y1, y2, y1Int, y2Int, y1Punct, y2Punct, y1IntPunct, y2IntPunct, rate = 13):
+ """ Puncturing mechanism.
+
+ rate -- code rate (e.g. 13 for rate 1/3)
+ clk, rst -- in : clock and negative reset
+ y1, y2, y1Int, y2Int -- in : original data
+ y1Punct, y2Punct, y1IntPunct, y2IntPunct -- out : punctured data
+
+ """
+ y1Sel = Signal(bool(0))
+ y2Sel = Signal(bool(0))
+ punctSel_i0 = punctSel(clk, rst, y1Sel, y2Sel, rate)
+ punctMux_i0 = punctMux(y1Sel, y2Sel, y1, y2, y1Int, y2Int, y1Punct, y2Punct, y1IntPunct, y2IntPunct)
+
+ return punctSel_i0, punctMux_i0
+
+def punctSel(clk, rst, y1Sel, y2Sel, rate = 13):
+ """ Puncturing selection (between original data (1) and 0 (0)).
+
+ clk, rst -- in : clock and negative reset
+ y1Sel, y2Sel -- out : selection signals (1 -> original data, 0 -> 0)
+
+ """
+ if rate == 13:
+ pattern = [[1], [1]]
+ elif rate == 25:
+ pattern = [[1, 1], [1, 0]]
+ elif rate == 12:
+ pattern = [[1], [0]]
+ elif rate == 23:
+ pattern = [[1, 0], [0, 0]]
+ elif rate == 34:
+ pattern = [[1, 0, 0], [0, 0, 0]]
+ elif rate == 45:
+ pattern = [[1, 0, 0, 0], [0, 0, 0, 0]]
+ elif rate == 67:
+ pattern = [[1, 0, 0, 0, 0, 0], [0, 0, 0, 0, 0, 0]]
+ else:
+ print "ERROR: the code rate you specified is not valid!"
+ cntMax = len(pattern[0])
+ cnt = Signal(intbv(0, 0, cntMax))
+ @always(clk.posedge, rst.negedge)
+ def punctSelLogic():
+ if rst.val == 0:
+ y1Sel.next = 0
+ y2Sel.next = 0
+ cnt.next = 0
+ else:
+ if cnt.val < cntMax - 1:
+ cnt.next = cnt.val + 1
+ else:
+ cnt.next = 0
+ y1Sel.next = pattern[0][int(cnt.val)]
+ y2Sel.next = pattern[1][int(cnt.val)]
+ return punctSelLogic
+
+def punctMux(y1Sel, y2Sel, y1, y2, y1Int, y2Int, y1Punct, y2Punct, y1IntPunct, y2IntPunct):
+ """ Puncturing mux.
+
+ y1Sel, y2Sel -- in : selection signals (1 -> original data, 0 -> 0)
+ y1, y2, y1Int, y2Int -- in : original data
+ y1Punct, y2Punct, y1IntPunct, y2IntPunct -- out : punctured data
+
+ """
+ @always_comb
+ def punctMuxLogic():
+ if y1Sel.val == 1:
+ y1Punct.next = y1.val
+ y1IntPunct.next = y1Int.val
+ else:
+ y1Punct.next = 0
+ y1IntPunct.next = 0
+ if y2Sel.val == 1:
+ y2Punct.next = y2.val
+ y2IntPunct.next = y2Int.val
+ else:
+ y2Punct.next = 0
+ y2IntPunct.next = 0
+ return punctMuxLogic
Index: src/myhdl/clock.py
===================================================================
--- src/myhdl/clock.py (nonexistent)
+++ src/myhdl/clock.py (revision 7)
@@ -0,0 +1,91 @@
+######################################################################
+#### ####
+#### clock.py ####
+#### ####
+#### This file is part of the turbo decoder IP core project ####
+#### http://www.opencores.org/projects/turbocodes/ ####
+#### ####
+#### Author(s): ####
+#### - David Brochart(dbrochart@opencores.org) ####
+#### ####
+#### All additional information is available in the README.txt ####
+#### file. ####
+#### ####
+######################################################################
+#### ####
+#### Copyright (C) 2005 Authors ####
+#### ####
+#### This source file may be used and distributed without ####
+#### restriction provided that this copyright statement is not ####
+#### removed from the file and that any derivative work contains ####
+#### the original copyright notice and the associated disclaimer. ####
+#### ####
+#### This source file is free software; you can redistribute it ####
+#### and/or modify it under the terms of the GNU Lesser General ####
+#### Public License as published by the Free Software Foundation; ####
+#### either version 2.1 of the License, or (at your option) any ####
+#### later version. ####
+#### ####
+#### This source is distributed in the hope that it will be ####
+#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
+#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
+#### PURPOSE. See the GNU Lesser General Public License for more ####
+#### details. ####
+#### ####
+#### You should have received a copy of the GNU Lesser General ####
+#### Public License along with this source; if not, download it ####
+#### from http://www.opencores.org/lgpl.shtml ####
+#### ####
+######################################################################
+
+
+
+from myhdl import Signal, delay, posedge, negedge, instance, always
+
+def clkGen(clk, duration_1 = 10, duration_2 = 10):
+ """ Clock signal generator.
+
+ duration_1 -- first level duration
+ duration_2 -- second level duration
+ clk -- out : generated clock signal
+
+ """
+ @instance
+ def clkGenLogic():
+ while 1:
+ yield delay(duration_1)
+ clk.next = not clk.val
+ yield delay(duration_2)
+ clk.next = not clk.val
+ return clkGenLogic
+
+def rstGen(rst, start = 5, duration = 10):
+ """ Reset signal generator.
+
+ start -- reset pulse start time
+ duration -- reset pulse duration
+ rst -- out : generated reset signal
+
+ """
+ @instance
+ def rstGenLogic():
+ yield delay(start)
+ rst.next = not rst.val
+ yield delay(duration)
+ rst.next = not rst.val
+ return rstGenLogic
+
+def clkDiv(clk, rst, clkout):
+ """ Clock divider (freq/2).
+
+ clk, rst -- in : clock and negative reset
+ clkout -- out : clock which frequency is half of the input clock
+
+ """
+ @always(clk.posedge, rst.negedge)
+ def clkDivLogic():
+ if rst.val == 0:
+ clkout.next = False
+ else:
+ clkout.next = not clkout.val
+ return clkDivLogic
Index: src/myhdl/selec.py
===================================================================
--- src/myhdl/selec.py (nonexistent)
+++ src/myhdl/selec.py (revision 7)
@@ -0,0 +1,80 @@
+######################################################################
+#### ####
+#### select.py ####
+#### ####
+#### This file is part of the turbo decoder IP core project ####
+#### http://www.opencores.org/projects/turbocodes/ ####
+#### ####
+#### Author(s): ####
+#### - David Brochart(dbrochart@opencores.org) ####
+#### ####
+#### All additional information is available in the README.txt ####
+#### file. ####
+#### ####
+######################################################################
+#### ####
+#### Copyright (C) 2005 Authors ####
+#### ####
+#### This source file may be used and distributed without ####
+#### restriction provided that this copyright statement is not ####
+#### removed from the file and that any derivative work contains ####
+#### the original copyright notice and the associated disclaimer. ####
+#### ####
+#### This source file is free software; you can redistribute it ####
+#### and/or modify it under the terms of the GNU Lesser General ####
+#### Public License as published by the Free Software Foundation; ####
+#### either version 2.1 of the License, or (at your option) any ####
+#### later version. ####
+#### ####
+#### This source is distributed in the hope that it will be ####
+#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
+#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
+#### PURPOSE. See the GNU Lesser General Public License for more ####
+#### details. ####
+#### ####
+#### You should have received a copy of the GNU Lesser General ####
+#### Public License along with this source; if not, download it ####
+#### from http://www.opencores.org/lgpl.shtml ####
+#### ####
+######################################################################
+
+
+
+from misc import min4, cod2, mux4, min8, cod3
+from myhdl import Signal, instances
+
+def accDistSel(accDist, accDistCod, accDistOut, q = 8):
+ """ Accumulated distance selection (one out of four, per state)
+
+ accDist -- in : array of 32 (q+1)-bit accumulated distances
+ accDistCod -- out : array of 8 2-bit selection signals
+ accDistOut -- out : array of 8 (q+1)-bit selected accumulated distances
+
+ """
+ min4_i = [None for i in range(8)]
+ cod2_i = [None for i in range(8)]
+ mux4_i = [None for i in range(8)]
+ comp = [Signal(bool(0)) for i in range(24)]
+ from2to = [0, 25, 6, 31, 8, 17, 14, 23, 20, 13, 18, 11, 28, 5, 26, 3, 4, 29, 2, 27, 12, 21, 10, 19, 16, 9, 22, 15, 24, 1, 30, 7]
+ for i in range(8):
+ min4_i[i] = min4(accDist[from2to[4*i]], accDist[from2to[4*i+1]], accDist[from2to[4*i+2]], accDist[from2to[4*i+3]], comp[3*i], comp[3*i+1], comp[3*i+2], q)
+ for i in range(8):
+ cod2_i[i] = cod2(comp[3*i], comp[3*i+1], comp[3*i+2], accDistCod[i])
+ for i in range(8):
+ mux4_i[i] = mux4(accDist[from2to[4*i]], accDist[from2to[4*i+1]], accDist[from2to[4*i+2]], accDist[from2to[4*i+3]], accDistCod[i], accDistOut[i])
+
+ return min4_i, cod2_i, mux4_i
+
+def stateSel(stateDist, selState, q = 8):
+ """ State selection (one out of eight).
+
+ q -- accumulated distance width
+ stateDist -- in : state accumulated distance
+ selState -- out : selected state code
+
+ """
+ tmp = [Signal(bool(0)) for i in range(7)]
+ min8_i0 = min8(stateDist, tmp, q)
+ cod3_i0 = cod3(tmp, selState)
+
+ return min8_i0, cod3_i0
Index: src/myhdl/misc.py
===================================================================
--- src/myhdl/misc.py (nonexistent)
+++ src/myhdl/misc.py (revision 7)
@@ -0,0 +1,336 @@
+######################################################################
+#### ####
+#### misc.py ####
+#### ####
+#### This file is part of the turbo decoder IP core project ####
+#### http://www.opencores.org/projects/turbocodes/ ####
+#### ####
+#### Author(s): ####
+#### - David Brochart(dbrochart@opencores.org) ####
+#### ####
+#### All additional information is available in the README.txt ####
+#### file. ####
+#### ####
+######################################################################
+#### ####
+#### Copyright (C) 2005 Authors ####
+#### ####
+#### This source file may be used and distributed without ####
+#### restriction provided that this copyright statement is not ####
+#### removed from the file and that any derivative work contains ####
+#### the original copyright notice and the associated disclaimer. ####
+#### ####
+#### This source file is free software; you can redistribute it ####
+#### and/or modify it under the terms of the GNU Lesser General ####
+#### Public License as published by the Free Software Foundation; ####
+#### either version 2.1 of the License, or (at your option) any ####
+#### later version. ####
+#### ####
+#### This source is distributed in the hope that it will be ####
+#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
+#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
+#### PURPOSE. See the GNU Lesser General Public License for more ####
+#### details. ####
+#### ####
+#### You should have received a copy of the GNU Lesser General ####
+#### Public License along with this source; if not, download it ####
+#### from http://www.opencores.org/lgpl.shtml ####
+#### ####
+######################################################################
+
+
+
+from myhdl import Signal, intbv, always_comb, instance, always, posedge, negedge, concat
+
+def delayer(clk, rst, d, q, delay = 1, mi = 0, ma = 1):
+ """ Delayer.
+
+ delay -- number of clock cycles to delay
+ mi -- minimum value of the signal to delay
+ ma -- maximum value of the signal to delay
+ clk, rst -- in : clock and negative reset
+ d -- in : signal to be delayed by "delay" clock cycles
+ q -- out : delayed signal
+
+ """
+ r = [Signal(intbv(0, mi, ma)) for i in range(delay)]
+ @always(clk.posedge, rst.negedge)
+ def delayerLogic():
+ if rst.val == 0:
+ q.next = 0
+ for i in range(delay):
+ r[i].next = 0
+ else:
+ r[0].next = d
+ q.next = r[delay - 1].val
+ for i in range(delay - 1):
+ r[i + 1].next = r[i].val
+ return delayerLogic
+
+def opposite(pos, neg):
+ """ Take the opposite of a number.
+
+ pos -- in : original number
+ neg -- out : opposite number
+
+ """
+ @always_comb
+ def oppositeLogic():
+ neg.next = -pos.val
+ return oppositeLogic
+
+def adder(op1, op2, res):
+ """ Adder.
+
+ op1 -- in : first operand
+ op2 -- in : second operand
+ res -- out : result of the addition
+
+ """
+ @always_comb
+ def addLogic():
+ res.next = op1.val + op2.val
+ return addLogic
+
+def register(clk, rst, d, q):
+ """ Register.
+
+ clk, rst -- in : clock and negative reset
+ d -- in : next value
+ q -- out : current value
+
+ """
+ @always(clk.posedge, rst.negedge)
+ def registerLogic():
+ if rst.val == 0:
+ q.next = 0
+ else:
+ q.next = d.val
+ return registerLogic
+
+def cmp2(op1, op2, res):
+ """ 2-input comparator.
+
+ op1 -- in : first operand
+ op2 -- in : second operand
+ res -- out : compare result (0 if op2 < op1, 1 otherwise)
+
+ """
+ @always_comb
+ def cmp2Logic():
+ if op1.val > op2.val:
+ res.next = 0
+ else:
+ res.next = 1
+ return cmp2Logic
+
+def mux2(in1, in2, sel, outSel):
+ """ 2-input mux.
+
+ in1 -- in : first input signal
+ in2 -- in : second input signal
+ sel -- in : 1-bit control signal
+ outSel -- out : selected output signal
+
+ """
+ @always_comb
+ def mux2Logic():
+ if sel.val == 0:
+ outSel.next = in2.val
+ else:
+ outSel.next = in1.val
+ return mux2Logic
+
+def orGate(op1, op2, res):
+ """ 2-input OR gate.
+
+ op1 -- in : first operand
+ op2 -- in : second operand
+ res -- out : result
+
+ """
+ @always_comb
+ def orGateLogic():
+ res.next = op1.val or op2.val
+ return orGateLogic
+
+def min4(op1, op2, op3, op4, res1, res2, res3, q = 8):
+ """ Selects the minimum between 4 values.
+
+ q -- width of the signals to compare
+ op1 -- in : first input signal
+ op2 -- in : second input signal
+ op3 -- in : third input signal
+ op4 -- in : fourth input signal
+ res1 -- out : partial code of the minimum value
+ res2 -- out : partial code of the minimum value
+ res3 -- out : partial code of the minimum value
+
+ """
+ op5 = Signal(intbv(0, 0, 2**q))
+ op6 = Signal(intbv(0, 0, 2**q))
+ cmp2_i0 = cmp2(op1, op2, res1)
+ cmp2_i1 = cmp2(op3, op4, res2)
+ mux2_i0 = mux2(op1, op2, res1, op5)
+ mux2_i1 = mux2(op3, op4, res2, op6)
+ cmp2_i2 = cmp2(op5, op6, res3)
+
+ return cmp2_i0, cmp2_i1, mux2_i0, mux2_i1, cmp2_i2
+
+def mux4(in1, in2, in3, in4, sel, outSel):
+ """ 4-input mux.
+
+ in1 -- in : first input signal
+ in2 -- in : second input signal
+ in3 -- in : third input signal
+ in4 -- in : fourth input signal
+ sel -- in : 2-bit control signal
+ outSel -- out : selected output signal
+
+ """
+ @always_comb
+ def mux4Logic():
+ if sel.val == 0:
+ outSel.next = in1.val
+ elif sel.val == 1:
+ outSel.next = in2.val
+ elif sel.val == 2:
+ outSel.next = in3.val
+ else:
+ outSel.next = in4.val
+ return mux4Logic
+
+def cod2(in1, in2, in3, outCod):
+ """ 2-bit coder.
+
+ in1 -- in : 1-bit first input signal
+ in2 -- in : 1-bit second input signal
+ in3 -- in : 1-bit third input signal
+ outCod -- out : 2-bit coded value
+
+ """
+ tmp = intbv(0, 0, 8)
+ @always_comb
+ def cod2Logic():
+ tmp = concat(bool(in1.val), bool(in2.val), bool(in3.val))
+ if tmp == 5:
+ outCod.next = 0
+ elif tmp == 7:
+ outCod.next = 0
+ elif tmp == 1:
+ outCod.next = 1
+ elif tmp == 3:
+ outCod.next = 1
+ elif tmp == 2:
+ outCod.next = 2
+ elif tmp == 6:
+ outCod.next = 2
+ elif tmp == 0:
+ outCod.next = 3
+ else:
+ outCod.next = 3
+ return cod2Logic
+
+def cod3(inSig, outCod):
+ """ 3-bit coder.
+
+ inSig -- in : 7 1-bit input signals
+ outCod -- out : 3-bit coded value
+
+ """
+ tmp = intbv(0, 0, 8)
+ @instance
+ def cod3Logic():
+ while 1:
+ tmp[0] = ((not inSig[6].val) and (not inSig[5].val) and (not inSig[3].val)) or ((not inSig[6].val) and inSig[5].val and (not inSig[2].val)) or (inSig[6].val and (not inSig[4].val) and (not inSig[1].val)) or ((inSig[6].val) and (inSig[4].val) and (not inSig[0].val));
+ tmp[1] = ((not inSig[6].val) and (not inSig[5].val)) or (inSig[6].val and (not inSig[4].val));
+ tmp[2] = not inSig[6].val
+ outCod.next = tmp
+ yield inSig[0], inSig[1], inSig[2], inSig[3], inSig[4], inSig[5], inSig[6]
+ return cod3Logic
+
+def min8(op, res, q = 8):
+ """ Selects the minimum between 8 values.
+
+ q -- accumulated distance width
+ op -- in : input signals
+ res -- out : code of the minimum value
+
+ """
+ tmp = [Signal(intbv(0, 0, 2**q)) for i in range(6)]
+ cmp2_i0 = cmp2(op[0], op[1], res[0])
+ cmp2_i1 = cmp2(op[2], op[3], res[1])
+ cmp2_i2 = cmp2(op[4], op[5], res[2])
+ cmp2_i3 = cmp2(op[6], op[7], res[3])
+ mux2_i0 = mux2(op[0], op[1], res[0], tmp[0])
+ mux2_i1 = mux2(op[2], op[3], res[1], tmp[1])
+ mux2_i2 = mux2(op[4], op[5], res[2], tmp[2])
+ mux2_i3 = mux2(op[6], op[7], res[3], tmp[3])
+ cmp2_i4 = cmp2(tmp[0], tmp[1], res[4])
+ cmp2_i5 = cmp2(tmp[2], tmp[3], res[5])
+ mux2_i4 = mux2(tmp[0], tmp[1], res[4], tmp[4])
+ mux2_i5 = mux2(tmp[2], tmp[3], res[5], tmp[5])
+ cmp2_i6 = cmp2(tmp[4], tmp[5], res[6])
+
+ return cmp2_i0, cmp2_i1, cmp2_i2, cmp2_i3, mux2_i0, mux2_i1, mux2_i2, mux2_i3, cmp2_i4, cmp2_i5, mux2_i4, mux2_i5, cmp2_i6
+
+def mux8(in1, in2, in3, in4, in5, in6, in7, in8, sel, outSel):
+ """ 8-input mux (4 bits per input).
+
+ in1 -- in : first input signals
+ in2 -- in : second input signals
+ in3 -- in : third input signals
+ in4 -- in : fourth input signals
+ in5 -- in : fifth input signals
+ in6 -- in : sixth input signals
+ in7 -- in : seventh input signals
+ in8 -- in : eighth input signals
+ sel -- in : 3-bit control signal
+ outSel -- out : selected output signals
+
+ """
+ @instance
+ def mux8Logic():
+ while 1:
+ if sel.val == 0:
+ for i in range(4):
+ outSel[i].next = in1[i].val
+ elif sel.val == 1:
+ for i in range(4):
+ outSel[i].next = in2[i].val
+ elif sel.val == 2:
+ for i in range(4):
+ outSel[i].next = in3[i].val
+ elif sel.val == 3:
+ for i in range(4):
+ outSel[i].next = in4[i].val
+ elif sel.val == 4:
+ for i in range(4):
+ outSel[i].next = in5[i].val
+ elif sel.val == 5:
+ for i in range(4):
+ outSel[i].next = in6[i].val
+ elif sel.val == 6:
+ for i in range(4):
+ outSel[i].next = in7[i].val
+ else:
+ for i in range(4):
+ outSel[i].next = in8[i].val
+ yield in1[0], in1[1], in1[2], in1[3], in2[0], in2[1], in2[2], in2[3], in3[0], in3[1], in3[2], in3[3], in4[0], in4[1], in4[2], in4[3], in5[0], in5[1], in5[2], in5[3], in6[0], in6[1], in6[2], in6[3], in7[0], in7[1], in7[2], in7[3], in8[0], in8[1], in8[2], in8[3], sel
+ return mux8Logic
+
+def sub(op1, op2, res):
+ """ Substracter.
+
+ op1 -- in : first operand
+ op2 -- in : second operand
+ res -- out : result of the substraction
+
+ """
+ @instance
+ def subLogic():
+ while 1:
+ if op1.val >= op2.val: # remove that when translate into Verilog (Python expects a positive result)
+ res.next = op1.val - op2.val
+ yield op1, op2
+ return subLogic
Index: src/myhdl/coder.py
===================================================================
--- src/myhdl/coder.py (nonexistent)
+++ src/myhdl/coder.py (revision 7)
@@ -0,0 +1,93 @@
+######################################################################
+#### ####
+#### coder.py ####
+#### ####
+#### This file is part of the turbo decoder IP core project ####
+#### http://www.opencores.org/projects/turbocodes/ ####
+#### ####
+#### Author(s): ####
+#### - David Brochart(dbrochart@opencores.org) ####
+#### ####
+#### All additional information is available in the README.txt ####
+#### file. ####
+#### ####
+######################################################################
+#### ####
+#### Copyright (C) 2005 Authors ####
+#### ####
+#### This source file may be used and distributed without ####
+#### restriction provided that this copyright statement is not ####
+#### removed from the file and that any derivative work contains ####
+#### the original copyright notice and the associated disclaimer. ####
+#### ####
+#### This source file is free software; you can redistribute it ####
+#### and/or modify it under the terms of the GNU Lesser General ####
+#### Public License as published by the Free Software Foundation; ####
+#### either version 2.1 of the License, or (at your option) any ####
+#### later version. ####
+#### ####
+#### This source is distributed in the hope that it will be ####
+#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
+#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
+#### PURPOSE. See the GNU Lesser General Public License for more ####
+#### details. ####
+#### ####
+#### You should have received a copy of the GNU Lesser General ####
+#### Public License along with this source; if not, download it ####
+#### from http://www.opencores.org/lgpl.shtml ####
+#### ####
+######################################################################
+
+
+
+from myhdl import Signal, posedge, negedge, always_comb, always
+
+def coderState(clk, rst, a, b, q1, q2, q3):
+ """ Coder state registers.
+
+ clk, rst -- in : clock and negative reset
+ a, b -- in : original data
+ q1, q2, q3 -- out : coder registers
+
+ """
+ @always(clk.posedge, rst.negedge)
+ def coderStateLogic():
+ if rst.val == 0:
+ q1.next = 0
+ q2.next = 0
+ q3.next = 0
+ else:
+ q1.next = a.val ^ b.val ^ q1.val ^ q3.val
+ q2.next = q1.val ^ b.val
+ q3.next = q2.val ^ b.val
+ return coderStateLogic
+
+def coderY1Y2(a, b, q1, q2, q3, y1, y2):
+ """ Coder redundant output generation.
+
+ a, b -- in : original data signals
+ q1, q2, q3 -- in : coder registers
+ y1, y2 -- out : coder redundant data signals
+
+ """
+ @always_comb
+ def coderY1Y2Logic():
+ y1.next = a.val ^ b.val ^ q1.val ^ q3.val ^ q2.val ^ q3.val
+ y2.next = a.val ^ b.val ^ q1.val ^ q3.val ^ q3.val
+ return coderY1Y2Logic
+
+def coder(clk, rst, a, b, y1, y2):
+ """ Coder top level.
+
+ clk, rst -- in : clock and negative reset
+ a, b -- in : original data signals (= systematic data)
+ y1, y2 -- out : coder redundant data signals
+
+ """
+ q1 = Signal(bool(0))
+ q2 = Signal(bool(0))
+ q3 = Signal(bool(0))
+ coderState_i0 = coderState(clk, rst, a, b, q1, q2, q3)
+ coderY1Y2_i0 = coderY1Y2(a, b, q1, q2, q3, y1, y2)
+
+ return coderState_i0, coderY1Y2_i0
Index: src/myhdl/args.py
===================================================================
--- src/myhdl/args.py (nonexistent)
+++ src/myhdl/args.py (revision 7)
@@ -0,0 +1,59 @@
+######################################################################
+#### ####
+#### args.py ####
+#### ####
+#### This file is part of the turbo decoder IP core project ####
+#### http://www.opencores.org/projects/turbocodes/ ####
+#### ####
+#### Author(s): ####
+#### - David Brochart(dbrochart@opencores.org) ####
+#### ####
+#### All additional information is available in the README.txt ####
+#### file. ####
+#### ####
+######################################################################
+#### ####
+#### Copyright (C) 2005 Authors ####
+#### ####
+#### This source file may be used and distributed without ####
+#### restriction provided that this copyright statement is not ####
+#### removed from the file and that any derivative work contains ####
+#### the original copyright notice and the associated disclaimer. ####
+#### ####
+#### This source file is free software; you can redistribute it ####
+#### and/or modify it under the terms of the GNU Lesser General ####
+#### Public License as published by the Free Software Foundation; ####
+#### either version 2.1 of the License, or (at your option) any ####
+#### later version. ####
+#### ####
+#### This source is distributed in the hope that it will be ####
+#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
+#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
+#### PURPOSE. See the GNU Lesser General Public License for more ####
+#### details. ####
+#### ####
+#### You should have received a copy of the GNU Lesser General ####
+#### Public License along with this source; if not, download it ####
+#### from http://www.opencores.org/lgpl.shtml ####
+#### ####
+######################################################################
+
+
+
+from sys import argv
+
+def getArgs(*args):
+ """ Gets the arguments and stores them in a dictionnary.
+
+ """
+ argDict = {}
+ for i in range(len(args)):
+ if argv.count(args[i]) != 0:
+ if args[i] == '-help':
+ argDict[args[i]] = 'on'
+ else:
+ j = argv.index(args[i])
+ argDict[args[i]] = argv[j + 1]
+ else:
+ argDict[args[i]] = None
+ return argDict
Index: src/myhdl/extInf.py
===================================================================
--- src/myhdl/extInf.py (nonexistent)
+++ src/myhdl/extInf.py (revision 7)
@@ -0,0 +1,106 @@
+######################################################################
+#### ####
+#### extInf.py ####
+#### ####
+#### This file is part of the turbo decoder IP core project ####
+#### http://www.opencores.org/projects/turbocodes/ ####
+#### ####
+#### Author(s): ####
+#### - David Brochart(dbrochart@opencores.org) ####
+#### ####
+#### All additional information is available in the README.txt ####
+#### file. ####
+#### ####
+######################################################################
+#### ####
+#### Copyright (C) 2005 Authors ####
+#### ####
+#### This source file may be used and distributed without ####
+#### restriction provided that this copyright statement is not ####
+#### removed from the file and that any derivative work contains ####
+#### the original copyright notice and the associated disclaimer. ####
+#### ####
+#### This source file is free software; you can redistribute it ####
+#### and/or modify it under the terms of the GNU Lesser General ####
+#### Public License as published by the Free Software Foundation; ####
+#### either version 2.1 of the License, or (at your option) any ####
+#### later version. ####
+#### ####
+#### This source is distributed in the hope that it will be ####
+#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
+#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
+#### PURPOSE. See the GNU Lesser General Public License for more ####
+#### details. ####
+#### ####
+#### You should have received a copy of the GNU Lesser General ####
+#### Public License along with this source; if not, download it ####
+#### from http://www.opencores.org/lgpl.shtml ####
+#### ####
+######################################################################
+
+
+
+from myhdl import Signal, intbv, instance
+
+def extInf(llr0, llr1, llr2, llr3, zin, a, b, zout, r = 5, n = 4, q = 8):
+ """ Extrinsic information.
+
+ r -- extrinsic information width
+ n -- systematic data width
+ q -- accumulated distance width
+ llr0 -- in : LLR for (a, b) = (0, 0)
+ llr1 -- in : LLR for (a, b) = (0, 1)
+ llr2 -- in : LLR for (a, b) = (1, 0)
+ llr3 -- in : LLR for (a, b) = (1, 1)
+ zin -- in : extrinsic information input signal
+ a, b -- in : decoder systematic input signals
+ zout -- out : extrinsic information output signal
+
+ """
+ a_plus_b = intbv(0, -(2**(n-1)), 2**(n-1))
+ a_min_b = intbv(0, -(2**(n-1)), 2**(n-1))
+ tmp = [intbv(0, -(2**(n-1)) - (2**r), 2**q + 2**(n-1)) for i in range(7)]
+ tmp2 = [intbv(0, 0, 2**q + 2**(n-1) + (2**(n-1)) + (2**r)) for i in range(4)]
+ @instance
+ def extInfLogic():
+ while 1:
+ a_plus_b = (a.val + b.val) / 2
+ a_min_b = (a.val - b.val) / 2
+ tmp[0] = llr0.val - a_plus_b - zin[0].val
+ tmp[1] = llr1.val - a_min_b - zin[1].val
+ tmp[2] = llr2.val + a_min_b - zin[2].val
+ tmp[3] = llr3.val + a_plus_b - zin[3].val
+ if tmp[0] < tmp[1]:
+ tmp[4] = tmp[0]
+ else:
+ tmp[4] = tmp[1]
+ if tmp[2] < tmp[3]:
+ tmp[5] = tmp[2]
+ else:
+ tmp[5] = tmp[3]
+ if tmp[4] < tmp[5]:
+ tmp[6] = tmp[4]
+ else:
+ tmp[6] = tmp[5]
+ tmp2[0] = intbv(tmp[0] - tmp[6])
+ tmp2[1] = intbv(tmp[1] - tmp[6])
+ tmp2[2] = intbv(tmp[2] - tmp[6])
+ tmp2[3] = intbv(tmp[3] - tmp[6])
+ if tmp2[0] >= 2**r:
+ zout[0].next = 2**r - 1
+ else:
+ zout[0].next = tmp2[0]
+ if tmp2[1] >= 2**r:
+ zout[1].next = 2**r - 1
+ else:
+ zout[1].next = tmp2[1]
+ if tmp2[2] >= 2**r:
+ zout[2].next = 2**r - 1
+ else:
+ zout[2].next = tmp2[2]
+ if tmp2[3] >= 2**r:
+ zout[3].next = 2**r - 1
+ else:
+ zout[3].next = tmp2[3]
+ yield llr0, llr1, llr2, llr3, zin[0], zin[1], zin[2], zin[3], a, b
+ return extInfLogic
Index: src/myhdl/iteration.py
===================================================================
--- src/myhdl/iteration.py (nonexistent)
+++ src/myhdl/iteration.py (revision 7)
@@ -0,0 +1,131 @@
+######################################################################
+#### ####
+#### iteration.py ####
+#### ####
+#### This file is part of the turbo decoder IP core project ####
+#### http://www.opencores.org/projects/turbocodes/ ####
+#### ####
+#### Author(s): ####
+#### - David Brochart(dbrochart@opencores.org) ####
+#### ####
+#### All additional information is available in the README.txt ####
+#### file. ####
+#### ####
+######################################################################
+#### ####
+#### Copyright (C) 2005 Authors ####
+#### ####
+#### This source file may be used and distributed without ####
+#### restriction provided that this copyright statement is not ####
+#### removed from the file and that any derivative work contains ####
+#### the original copyright notice and the associated disclaimer. ####
+#### ####
+#### This source file is free software; you can redistribute it ####
+#### and/or modify it under the terms of the GNU Lesser General ####
+#### Public License as published by the Free Software Foundation; ####
+#### either version 2.1 of the License, or (at your option) any ####
+#### later version. ####
+#### ####
+#### This source is distributed in the hope that it will be ####
+#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
+#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
+#### PURPOSE. See the GNU Lesser General Public License for more ####
+#### details. ####
+#### ####
+#### You should have received a copy of the GNU Lesser General ####
+#### Public License along with this source; if not, download it ####
+#### from http://www.opencores.org/lgpl.shtml ####
+#### ####
+######################################################################
+
+
+
+from misc import delayer
+from interleaver import interleaver
+from permut import zPermut, abPermut
+from sova import sova
+from myhdl import Signal, intbv, instances
+
+def iteration(clk, rst, flipflop, a, b, y1, y2, y1Int, y2Int, zin, zout, aDec, bDec, aDel, bDel, y1Del, y2Del, y1IntDel, y2IntDel, l = 20, m = 10, q = 8, p = 48, r = 5, n = 4, delay = 0):
+ """ Decoding iteration top level (two SOVAs).
+
+ l -- first trellis length
+ m -- second trellis length
+ q -- accumulated distance width
+ p -- interleaver frame size in bit couples
+ r -- extrinsic information width
+ n -- systematic data width
+ delay -- additional delay created by the previous iterations
+ clk, rst -- in : clock and negative reset
+ flipflop -- in : permutation control signal (on/off)
+ a, b, y1, y2, y1Int, y2Int -- in : received decoder signals
+ zin -- in : extrinsic information from the previous iteration
+ zout -- out : extrinsic information to the next iteration
+ aDec, bDec -- out : decoded signals
+ aDel, bDel, y1Del, y2Del, y1IntDel, y2IntDel -- out : delayed received decoder signals
+
+ """
+ # Signal declarations:
+ aDecInt = Signal(bool(0))
+ bDecInt = Signal(bool(0))
+ zoutInt1 = [Signal(intbv(0, 0, 2**r)) for i in range(4)]
+ zout1Perm = [Signal(intbv(0, 0, 2**r)) for i in range(4)]
+ aDel1 = Signal(intbv(0, -(2**(n-1)), 2**(n-1)))
+ bDel1 = Signal(intbv(0, -(2**(n-1)), 2**(n-1)))
+ aDel2 = Signal(intbv(0, -(2**(n-1)), 2**(n-1)))
+ bDel2 = Signal(intbv(0, -(2**(n-1)), 2**(n-1)))
+ y1Del1 = Signal(intbv(0, -(2**(n-1)), 2**(n-1)))
+ y2Del1 = Signal(intbv(0, -(2**(n-1)), 2**(n-1)))
+ y1Del2 = Signal(intbv(0, -(2**(n-1)), 2**(n-1)))
+ y2Del2 = Signal(intbv(0, -(2**(n-1)), 2**(n-1)))
+ y1IntDel1 = Signal(intbv(0, -(2**(n-1)), 2**(n-1)))
+ y2IntDel1 = Signal(intbv(0, -(2**(n-1)), 2**(n-1)))
+ y1IntDel3 = Signal(intbv(0, -(2**(n-1)), 2**(n-1)))
+ y2IntDel3 = Signal(intbv(0, -(2**(n-1)), 2**(n-1)))
+ y1IntDel4 = Signal(intbv(0, -(2**(n-1)), 2**(n-1)))
+ y2IntDel4 = Signal(intbv(0, -(2**(n-1)), 2**(n-1)))
+ aDel3 = Signal(intbv(0, -(2**(n-1)), 2**(n-1)))
+ bDel3 = Signal(intbv(0, -(2**(n-1)), 2**(n-1)))
+ abDel1Perm = [Signal(intbv(0, -(2**(n-1)), 2**(n-1))) for i in range(2)]
+ abDel1PermInt = [Signal(intbv(0, -(2**(n-1)), 2**(n-1))) for i in range(2)]
+ y1Del3 = Signal(intbv(0, -(2**(n-1)), 2**(n-1)))
+ y2Del3 = Signal(intbv(0, -(2**(n-1)), 2**(n-1)))
+ zout1 = [Signal(intbv(0, 0, 2**r)) for i in range(4)]
+ zout2 = [Signal(intbv(0, 0, 2**r)) for i in range(4)]
+ zout2Int = [Signal(intbv(0, 0, 2**r)) for i in range(4)]
+
+ # Instanciations:
+ sova_i0 = sova(clk, rst, a, b, y1, y2, zin, zout1, aDec, bDec, l, m, q, r, n)
+ zPermut_i0 = zPermut(flipflop, zout1, zout1Perm, (l + m + 2 + delay + 1) % 2)
+ interleaver_i0 = interleaver(clk, rst, zout1Perm, zoutInt1, p, l + m + 2 + delay, 0, 2**r, 4, 0)
+ delayer_i0 = delayer(clk, rst, a, aDel1, (l + m), -(2**(n-1)), 2**(n-1))
+ delayer_i1 = delayer(clk, rst, b, bDel1, (l + m), -(2**(n-1)), 2**(n-1))
+ delayer_i2 = delayer(clk, rst, y1, y1Del1, (l + m), -(2**(n-1)), 2**(n-1))
+ delayer_i3 = delayer(clk, rst, y2, y2Del1, (l + m), -(2**(n-1)), 2**(n-1))
+ delayer_i4 = delayer(clk, rst, y1Int, y1IntDel1, (l + m), -(2**(n-1)), 2**(n-1))
+ delayer_i5 = delayer(clk, rst, y2Int, y2IntDel1, (l + m), -(2**(n-1)), 2**(n-1))
+ abPermut_i0 = abPermut(flipflop, aDel1, bDel1, abDel1Perm, (l + m + 2 + delay + 1) % 2)
+ interleaver_i1 = interleaver(clk, rst, abDel1Perm, abDel1PermInt, p, l + m + 2 + delay, -(2**(n-1)), 2**(n-1), 2, 0)
+ delayer_i6 = delayer(clk, rst, aDel1, aDel2, p, -(2**(n-1)), 2**(n-1))
+ delayer_i7 = delayer(clk, rst, bDel1, bDel2, p, -(2**(n-1)), 2**(n-1))
+ delayer_i8 = delayer(clk, rst, y1Del1, y1Del2, p, -(2**(n-1)), 2**(n-1))
+ delayer_i9 = delayer(clk, rst, y2Del1, y2Del2, p, -(2**(n-1)), 2**(n-1))
+ sova_i1 = sova(clk, rst, abDel1PermInt[1], abDel1PermInt[0], y1IntDel1, y2IntDel1, zoutInt1, zout2, aDecInt, bDecInt, l, m, q, r, n)
+ deinterleaver_i0 = interleaver(clk, rst, zout2, zout2Int, p, 2 * (l + m + 2) + p + delay, 0, 2**r, 4, 1)
+ zPermut_i1 = zPermut(flipflop, zout2Int, zout, (2 * (l + m + 2) + p + delay) % 2)
+ delayer_i10 = delayer(clk, rst, aDel2, aDel3, (l + m), -(2**(n-1)), 2**(n-1))
+ delayer_i11 = delayer(clk, rst, bDel2, bDel3, (l + m), -(2**(n-1)), 2**(n-1))
+ delayer_i12 = delayer(clk, rst, y1Del2, y1Del3, (l + m), -(2**(n-1)), 2**(n-1))
+ delayer_i13 = delayer(clk, rst, y2Del2, y2Del3, (l + m), -(2**(n-1)), 2**(n-1))
+ delayer_i14 = delayer(clk, rst, y1IntDel1, y1IntDel3, (l + m), -(2**(n-1)), 2**(n-1))
+ delayer_i15 = delayer(clk, rst, y2IntDel1, y2IntDel3, (l + m), -(2**(n-1)), 2**(n-1))
+ delayer_i16 = delayer(clk, rst, aDel3, aDel, p, -(2**(n-1)), 2**(n-1))
+ delayer_i17 = delayer(clk, rst, bDel3, bDel, p, -(2**(n-1)), 2**(n-1))
+ delayer_i18 = delayer(clk, rst, y1Del3, y1Del, p, -(2**(n-1)), 2**(n-1))
+ delayer_i19 = delayer(clk, rst, y2Del3, y2Del, p, -(2**(n-1)), 2**(n-1))
+ delayer_i20 = delayer(clk, rst, y1IntDel3, y1IntDel4, p, -(2**(n-1)), 2**(n-1))
+ delayer_i21 = delayer(clk, rst, y2IntDel3, y2IntDel4, p, -(2**(n-1)), 2**(n-1))
+ delayer_i22 = delayer(clk, rst, y1IntDel4, y1IntDel, p, -(2**(n-1)), 2**(n-1))
+ delayer_i23 = delayer(clk, rst, y2IntDel4, y2IntDel, p, -(2**(n-1)), 2**(n-1))
+
+ return sova_i0, zPermut_i0, interleaver_i0, delayer_i0, delayer_i1, delayer_i2, delayer_i3, delayer_i4, delayer_i5, abPermut_i0, interleaver_i1, delayer_i6, delayer_i7, delayer_i8, delayer_i9, sova_i1, deinterleaver_i0, zPermut_i1, delayer_i10, delayer_i11, delayer_i12, delayer_i13, delayer_i14, delayer_i15, delayer_i16, delayer_i17, delayer_i18, delayer_i19, delayer_i20, delayer_i21, delayer_i22, delayer_i23
Index: src/myhdl/noiser.py
===================================================================
--- src/myhdl/noiser.py (nonexistent)
+++ src/myhdl/noiser.py (revision 7)
@@ -0,0 +1,109 @@
+######################################################################
+#### ####
+#### noiser.py ####
+#### ####
+#### This file is part of the turbo decoder IP core project ####
+#### http://www.opencores.org/projects/turbocodes/ ####
+#### ####
+#### Author(s): ####
+#### - David Brochart(dbrochart@opencores.org) ####
+#### ####
+#### All additional information is available in the README.txt ####
+#### file. ####
+#### ####
+######################################################################
+#### ####
+#### Copyright (C) 2005 Authors ####
+#### ####
+#### This source file may be used and distributed without ####
+#### restriction provided that this copyright statement is not ####
+#### removed from the file and that any derivative work contains ####
+#### the original copyright notice and the associated disclaimer. ####
+#### ####
+#### This source file is free software; you can redistribute it ####
+#### and/or modify it under the terms of the GNU Lesser General ####
+#### Public License as published by the Free Software Foundation; ####
+#### either version 2.1 of the License, or (at your option) any ####
+#### later version. ####
+#### ####
+#### This source is distributed in the hope that it will be ####
+#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
+#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
+#### PURPOSE. See the GNU Lesser General Public License for more ####
+#### details. ####
+#### ####
+#### You should have received a copy of the GNU Lesser General ####
+#### Public License along with this source; if not, download it ####
+#### from http://www.opencores.org/lgpl.shtml ####
+#### ####
+######################################################################
+
+
+
+from random import gauss
+from myhdl import Signal, posedge, negedge, always
+
+def noiser(clk, rst, a, b, y1, y2, y1Int, y2Int, aNoisy, bNoisy, y1Noisy, y2Noisy, y1IntNoisy, y2IntNoisy, n = 4 , mu = 2**(4 - 1), sigma = 2**(4 - 2) + 2**(4 - 3)):
+ """ Signal noiser (Gauss distribution).
+
+ n -- number of bits for the coding of the noisy signals (= for the sampling of the received data)
+ mu -- mean value for the distribution
+ sigma -- standard deviation for the distribution (0 means no noise)
+ clk, rst -- in : clock and negative reset
+ a, b, y1, y2, y1Int, y2Int -- in : original coder signals, coded with 1 bit
+ aNoisy, bNoisy, y1Noisy, y2Noisy, y1IntNoisy, y2IntNoisy -- out : noisy signals, coded with n bits and delayed by 1 clock cycle
+
+ """
+ #mu = 2**(n - 1) #8
+ #sigma = 2**(n - 2) + 2**(n - 3) #6
+# cnt = Signal(int(0))
+ @always(clk.posedge, rst.negedge)
+ def noiserLogic():
+ if rst.val == 0:
+ aNoisy.next = 0
+ bNoisy.next = 0
+ y1Noisy.next = 0
+ y2Noisy.next = 0
+# cnt.next = 0
+ else:
+# if cnt.val < 10:
+# cnt.next = cnt.next + 1
+# aNoisy.next = ((a.val * 2) - 1) * 7
+# bNoisy.next = ((b.val * 2) - 1) * 7
+# y1Noisy.next = ((y1.val * 2) - 1) * 7
+# y2Noisy.next = ((y2.val * 2) - 1) * 7
+# y1IntNoisy.next = ((y1Int.val * 2) - 1) * 7
+# y2IntNoisy.next = ((y2Int.val * 2) - 1) * 7
+# else:
+# cnt.next = 0
+# aNoisy.next = 7
+# bNoisy.next = 7
+# y1Noisy.next = 7
+# y2Noisy.next = 7
+# y1IntNoisy.next = 7
+# y2IntNoisy.next = 7
+ if a.val == 0:
+ aNoisy.next = int(round(gauss(-mu + 1, sigma)))
+ else:
+ aNoisy.next = int(round(gauss(mu - 1, sigma)))
+ if b.val == 0:
+ bNoisy.next = int(round(gauss(-mu + 1, sigma)))
+ else:
+ bNoisy.next = int(round(gauss(mu - 1, sigma)))
+ if y1.val == 0:
+ y1Noisy.next = int(round(gauss(-mu + 1, sigma)))
+ else:
+ y1Noisy.next = int(round(gauss(mu - 1, sigma)))
+ if y2.val == 0:
+ y2Noisy.next = int(round(gauss(-mu + 1, sigma)))
+ else:
+ y2Noisy.next = int(round(gauss(mu - 1, sigma)))
+ if y1Int.val == 0:
+ y1IntNoisy.next = int(round(gauss(-mu + 1, sigma)))
+ else:
+ y1IntNoisy.next = int(round(gauss(mu - 1, sigma)))
+ if y2Int.val == 0:
+ y2IntNoisy.next = int(round(gauss(-mu + 1, sigma)))
+ else:
+ y2IntNoisy.next = int(round(gauss(mu - 1, sigma)))
+ return noiserLogic
Index: src/myhdl/limiter.py
===================================================================
--- src/myhdl/limiter.py (nonexistent)
+++ src/myhdl/limiter.py (revision 7)
@@ -0,0 +1,91 @@
+######################################################################
+#### ####
+#### limiter.py ####
+#### ####
+#### This file is part of the turbo decoder IP core project ####
+#### http://www.opencores.org/projects/turbocodes/ ####
+#### ####
+#### Author(s): ####
+#### - David Brochart(dbrochart@opencores.org) ####
+#### ####
+#### All additional information is available in the README.txt ####
+#### file. ####
+#### ####
+######################################################################
+#### ####
+#### Copyright (C) 2005 Authors ####
+#### ####
+#### This source file may be used and distributed without ####
+#### restriction provided that this copyright statement is not ####
+#### removed from the file and that any derivative work contains ####
+#### the original copyright notice and the associated disclaimer. ####
+#### ####
+#### This source file is free software; you can redistribute it ####
+#### and/or modify it under the terms of the GNU Lesser General ####
+#### Public License as published by the Free Software Foundation; ####
+#### either version 2.1 of the License, or (at your option) any ####
+#### later version. ####
+#### ####
+#### This source is distributed in the hope that it will be ####
+#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
+#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
+#### PURPOSE. See the GNU Lesser General Public License for more ####
+#### details. ####
+#### ####
+#### You should have received a copy of the GNU Lesser General ####
+#### Public License along with this source; if not, download it ####
+#### from http://www.opencores.org/lgpl.shtml ####
+#### ####
+######################################################################
+
+
+
+from myhdl import Signal, always_comb
+
+def limiter(a, b, y1, y2, y1Int, y2Int, aLim, bLim, y1Lim, y2Lim, y1IntLim, y2IntLim, n = 4):
+ """ Limiter [-2**(n - 1) + 1, 2**(n - 1) - 1].
+
+ n -- number of bits for the coding of the decoder input signals
+ a, b, y1, y2, y1Int, y2Int -- in : decoder input signals, coded with n bits
+ aLim, bLim, y1Lim, y2Lim, y1IntLim, y2IntLim -- out : limited signals
+
+ """
+ @always_comb
+ def limitLogic():
+ if a.val <= -2**(n - 1):
+ aLim.next = -2**(n - 1) + 1
+ elif a.val >= 2**(n - 1):
+ aLim.next = 2**(n - 1) - 1
+ else:
+ aLim.next = a.val
+ if b.val <= -2**(n - 1):
+ bLim.next = -2**(n - 1) + 1
+ elif b.val >= 2**(n - 1):
+ bLim.next = 2**(n - 1) - 1
+ else:
+ bLim.next = b.val
+ if y1.val <= -2**(n - 1):
+ y1Lim.next = -2**(n - 1) + 1
+ elif y1.val >= 2**(n - 1):
+ y1Lim.next = 2**(n - 1) - 1
+ else:
+ y1Lim.next = y1.val
+ if y2.val <= -2**(n - 1):
+ y2Lim.next = -2**(n - 1) + 1
+ elif y2.val >= 2**(n - 1):
+ y2Lim.next = 2**(n - 1) - 1
+ else:
+ y2Lim.next = y2.val
+ if y1Int.val <= -2**(n - 1):
+ y1IntLim.next = -2**(n - 1) + 1
+ elif y1Int.val >= 2**(n - 1):
+ y1IntLim.next = 2**(n - 1) - 1
+ else:
+ y1IntLim.next = y1Int.val
+ if y2Int.val <= -2**(n - 1):
+ y2IntLim.next = -2**(n - 1) + 1
+ elif y2Int.val >= 2**(n - 1):
+ y2IntLim.next = 2**(n - 1) - 1
+ else:
+ y2IntLim.next = y2Int.val
+ return limitLogic
Index: src/myhdl/acs.py
===================================================================
--- src/myhdl/acs.py (nonexistent)
+++ src/myhdl/acs.py (revision 7)
@@ -0,0 +1,87 @@
+######################################################################
+#### ####
+#### acs.py ####
+#### ####
+#### This file is part of the turbo decoder IP core project ####
+#### http://www.opencores.org/projects/turbocodes/ ####
+#### ####
+#### Author(s): ####
+#### - David Brochart(dbrochart@opencores.org) ####
+#### ####
+#### All additional information is available in the README.txt ####
+#### file. ####
+#### ####
+######################################################################
+#### ####
+#### Copyright (C) 2005 Authors ####
+#### ####
+#### This source file may be used and distributed without ####
+#### restriction provided that this copyright statement is not ####
+#### removed from the file and that any derivative work contains ####
+#### the original copyright notice and the associated disclaimer. ####
+#### ####
+#### This source file is free software; you can redistribute it ####
+#### and/or modify it under the terms of the GNU Lesser General ####
+#### Public License as published by the Free Software Foundation; ####
+#### either version 2.1 of the License, or (at your option) any ####
+#### later version. ####
+#### ####
+#### This source is distributed in the hope that it will be ####
+#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
+#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
+#### PURPOSE. See the GNU Lesser General Public License for more ####
+#### details. ####
+#### ####
+#### You should have received a copy of the GNU Lesser General ####
+#### Public License along with this source; if not, download it ####
+#### from http://www.opencores.org/lgpl.shtml ####
+#### ####
+######################################################################
+
+
+
+from selec import accDistSel, stateSel
+from misc import opposite, delayer, mux8, mux4, sub
+from distances import distances, accDist
+from myhdl import Signal, instances, intbv
+
+def acs(clk, rst, a, b, y1, y2, z, selStateL, selDistL, selState, stateDist, weight, q = 8, l = 20, n = 4, r = 5):
+ """ Add-Compare-Select top level.
+
+ q -- accumulated distance width
+ l -- first trellis length
+ n -- received decoder signal width
+ r -- extrinsic information width
+ clk, rst -- in : clock and negative reset
+ a, b, y1, y2 -- in : received decoder signals
+ z -- in : extrinsic information
+ selStateL -- in : selected state at t = L
+ selDistL -- in : selected transition at selStateL
+ selState -- out : selected state
+ stateDist -- out : selected accumulated distances (per state)
+ weight -- out : four weights sorted by transition code
+
+ """
+ from2to = [0, 25, 6, 31, 8, 17, 14, 23, 20, 13, 18, 11, 28, 5, 26, 3, 4, 29, 2, 27, 12, 21, 10, 19, 16, 9, 22, 15, 24, 1, 30, 7]
+ distance16 = [Signal(intbv(0, 0, 4*(2**(n-1))+(2**r))) for i in range(16)]
+ accDist8 = [Signal(intbv(0, 0, 2**q)) for i in range(8)]
+ accDist32 = [Signal(intbv(0, 0, 2**q)) for i in range(32)]
+ accDistDel32 = [[Signal(intbv(0, 0, 2**q)) for i in range(4)] for j in range(8)]
+ accDistDel4 = [Signal(intbv(0, 0, 2**q)) for i in range(4)]
+ selAccDistL = Signal(intbv(0, 0, 2**q))
+ delayer_i = [None for i in range(32)]
+ distances_i0 = distances(a, b, y1, y2, z, distance16)
+ accDist_i0 = accDist(clk, rst, accDist8, distance16, accDist32, q)
+ for i in range(8):
+ for j in range(4):
+ delayer_i[i * 4 + j] = delayer(clk, rst, accDist32[from2to[i * 4 + j]], accDistDel32[i][j], l - 1, 0, 2**(q+1))
+ mux8_i0 = mux8(accDistDel32[0], accDistDel32[1], accDistDel32[2], accDistDel32[3], accDistDel32[4], accDistDel32[5], accDistDel32[6], accDistDel32[7], selStateL, accDistDel4)
+ mux4_i0 = mux4(accDistDel4[0], accDistDel4[1], accDistDel4[2], accDistDel4[3], selDistL, selAccDistL)
+ sub_i0 = sub(accDistDel4[0], selAccDistL, weight[0])
+ sub_i1 = sub(accDistDel4[1], selAccDistL, weight[1])
+ sub_i2 = sub(accDistDel4[2], selAccDistL, weight[2])
+ sub_i3 = sub(accDistDel4[3], selAccDistL, weight[3])
+ accDistSel_i0 = accDistSel(accDist32, stateDist, accDist8, q)
+ stateSel_i0 = stateSel(accDist8, selState, q)
+
+ return distances_i0, accDist_i0, mux8_i0, mux4_i0, sub_i0, sub_i1, sub_i2, sub_i3, accDistSel_i0, stateSel_i0, delayer_i
Index: src/myhdl/sova.py
===================================================================
--- src/myhdl/sova.py (nonexistent)
+++ src/myhdl/sova.py (revision 7)
@@ -0,0 +1,92 @@
+######################################################################
+#### ####
+#### sova.py ####
+#### ####
+#### This file is part of the turbo decoder IP core project ####
+#### http://www.opencores.org/projects/turbocodes/ ####
+#### ####
+#### Author(s): ####
+#### - David Brochart(dbrochart@opencores.org) ####
+#### ####
+#### All additional information is available in the README.txt ####
+#### file. ####
+#### ####
+######################################################################
+#### ####
+#### Copyright (C) 2005 Authors ####
+#### ####
+#### This source file may be used and distributed without ####
+#### restriction provided that this copyright statement is not ####
+#### removed from the file and that any derivative work contains ####
+#### the original copyright notice and the associated disclaimer. ####
+#### ####
+#### This source file is free software; you can redistribute it ####
+#### and/or modify it under the terms of the GNU Lesser General ####
+#### Public License as published by the Free Software Foundation; ####
+#### either version 2.1 of the License, or (at your option) any ####
+#### later version. ####
+#### ####
+#### This source is distributed in the hope that it will be ####
+#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
+#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
+#### PURPOSE. See the GNU Lesser General Public License for more ####
+#### details. ####
+#### ####
+#### You should have received a copy of the GNU Lesser General ####
+#### Public License along with this source; if not, download it ####
+#### from http://www.opencores.org/lgpl.shtml ####
+#### ####
+######################################################################
+
+
+
+from extInf import extInf
+from misc import delayer
+from trellis import trellis1, trellis2
+from acs import acs
+from myhdl import Signal, intbv, instances
+
+def sova(clk, rst, aNoisy, bNoisy, y1Noisy, y2Noisy, zin, zout, aClean, bClean, l = 20, m = 10, q = 8, r = 5, n = 4):
+ """ Soft Output Viterbi Algorithm top level.
+
+ l -- first trellis length
+ m -- second trellis length
+ q -- accumulated distance width
+ r -- extrinsic information width
+ n -- systematic data width
+ clk, rst -- in : clock and negative reset
+ aNoisy, bNoisy, y1Noisy, y2Noisy -- in : received decoder signals
+ zin -- in : extrinsic information input
+ zout -- out : extrinsic information output
+ aClean, bClean -- out : decoded systematic data
+
+ """
+ selStateL2 = Signal(intbv(0, 0, 8))
+ selStateL1 = Signal(intbv(0, 0, 8))
+ selTransL2 = Signal(intbv(0, 0, 4))
+ selTrans = [Signal(intbv(0, 0, 4)) for i in range(8)]
+ selState = Signal(intbv(0, 0, 8))
+ weight = [Signal(intbv(0, 0, 2**q)) for i in range(4)]
+ selTransL1 = [Signal(intbv(0, 0, 4)) for i in range(8)]
+ zinDel = [Signal(intbv(0, 0, 2**r)) for i in range(4)]
+ stateL1 = [Signal(intbv(0, 0, 8)) for i in range(4)]
+ llr0 = Signal(intbv(0, 0, 2**q))
+ llr1 = Signal(intbv(0, 0, 2**q))
+ llr2 = Signal(intbv(0, 0, 2**q))
+ llr3 = Signal(intbv(0, 0, 2**q))
+ aNoisyDel = Signal(intbv(0, -(2**(n-1)), 2**(n-1)))
+ bNoisyDel = Signal(intbv(0, -(2**(n-1)), 2**(n-1)))
+
+ delayer_i = [None for i in range(12)]
+ acs_i0 = acs(clk, rst, aNoisy, bNoisy, y1Noisy, y2Noisy, zin, selStateL2, selTransL2, selState, selTrans, weight, q, l, n, r)
+ trellis1_i0 = trellis1(clk, rst, selState, selTrans, selStateL2, selStateL1, stateL1, selTransL2, l)
+ trellis2_i0 = trellis2(clk, rst, selStateL1, stateL1, selTransL1, weight, llr0, llr1, llr2, llr3, aClean, bClean, m, q)
+ for i in range(8):
+ delayer_i[i] = delayer(clk, rst, selTrans[i], selTransL1[i], l - 1, 0, 2**2)
+ for i in range(4):
+ delayer_i[i + 8] = delayer(clk, rst, zin[i], zinDel[i], l + m, 0, 2**r)
+ delayer_i0 = delayer(clk, rst, aNoisy, aNoisyDel, l + m, -(2**(n-1)), 2**(n-1))
+ delayer_i1 = delayer(clk, rst, bNoisy, bNoisyDel, l + m, -(2**(n-1)), 2**(n-1))
+ extInf_i0 = extInf(llr0, llr1, llr2, llr3, zinDel, aNoisyDel, bNoisyDel, zout, r, n, q)
+
+ return delayer_i0, delayer_i1, extInf_i0, trellis1_i0, trellis2_i0, acs_i0, delayer_i
Index: src/myhdl/permut.py
===================================================================
--- src/myhdl/permut.py (nonexistent)
+++ src/myhdl/permut.py (revision 7)
@@ -0,0 +1,89 @@
+######################################################################
+#### ####
+#### permut.py ####
+#### ####
+#### This file is part of the turbo decoder IP core project ####
+#### http://www.opencores.org/projects/turbocodes/ ####
+#### ####
+#### Author(s): ####
+#### - David Brochart(dbrochart@opencores.org) ####
+#### ####
+#### All additional information is available in the README.txt ####
+#### file. ####
+#### ####
+######################################################################
+#### ####
+#### Copyright (C) 2005 Authors ####
+#### ####
+#### This source file may be used and distributed without ####
+#### restriction provided that this copyright statement is not ####
+#### removed from the file and that any derivative work contains ####
+#### the original copyright notice and the associated disclaimer. ####
+#### ####
+#### This source file is free software; you can redistribute it ####
+#### and/or modify it under the terms of the GNU Lesser General ####
+#### Public License as published by the Free Software Foundation; ####
+#### either version 2.1 of the License, or (at your option) any ####
+#### later version. ####
+#### ####
+#### This source is distributed in the hope that it will be ####
+#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
+#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
+#### PURPOSE. See the GNU Lesser General Public License for more ####
+#### details. ####
+#### ####
+#### You should have received a copy of the GNU Lesser General ####
+#### Public License along with this source; if not, download it ####
+#### from http://www.opencores.org/lgpl.shtml ####
+#### ####
+######################################################################
+
+
+
+from myhdl import Signal, instance
+
+def zPermut(flipflop, z, zPerm, flip = 0):
+ """ Extrinsic information permutation.
+
+ flip -- initialisation (permutation on/off)
+ flipflop -- in : permutation control signal (on/off)
+ z -- in : original extrinsic information
+ zPerm -- out : permuted extrinsic information
+
+ """
+ @instance
+ def zPermutLogic():
+ while 1:
+ if flipflop.val == bool(flip):
+ zPerm[0].next = z[0].val
+ zPerm[1].next = z[1].val
+ zPerm[2].next = z[2].val
+ zPerm[3].next = z[3].val
+ else:
+ zPerm[0].next = z[0].val
+ zPerm[1].next = z[2].val
+ zPerm[2].next = z[1].val
+ zPerm[3].next = z[3].val
+ yield flipflop, z[0], z[1], z[2], z[3]
+ return zPermutLogic
+
+def abPermut(flipflop, a, b, abPerm, flip = 0):
+ """ Systematic information permutation.
+
+ flip -- initialisation (permutation on/off)
+ flipflop -- in : permutation control signal (on/off)
+ a, b -- in : original systematic information
+ abPerm -- out : permuted systematic information
+
+ """
+ @instance
+ def abPermutLogic():
+ while 1:
+ if flipflop.val == bool(flip):
+ abPerm[1].next = a.val
+ abPerm[0].next = b.val
+ else:
+ abPerm[1].next = b.val
+ abPerm[0].next = a.val
+ yield flipflop, a, b
+ return abPermutLogic
Index: src/myhdl/distances.py
===================================================================
--- src/myhdl/distances.py (nonexistent)
+++ src/myhdl/distances.py (revision 7)
@@ -0,0 +1,161 @@
+######################################################################
+#### ####
+#### distances.py ####
+#### ####
+#### This file is part of the turbo decoder IP core project ####
+#### http://www.opencores.org/projects/turbocodes/ ####
+#### ####
+#### Author(s): ####
+#### - David Brochart(dbrochart@opencores.org) ####
+#### ####
+#### All additional information is available in the README.txt ####
+#### file. ####
+#### ####
+######################################################################
+#### ####
+#### Copyright (C) 2005 Authors ####
+#### ####
+#### This source file may be used and distributed without ####
+#### restriction provided that this copyright statement is not ####
+#### removed from the file and that any derivative work contains ####
+#### the original copyright notice and the associated disclaimer. ####
+#### ####
+#### This source file is free software; you can redistribute it ####
+#### and/or modify it under the terms of the GNU Lesser General ####
+#### Public License as published by the Free Software Foundation; ####
+#### either version 2.1 of the License, or (at your option) any ####
+#### later version. ####
+#### ####
+#### This source is distributed in the hope that it will be ####
+#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
+#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
+#### PURPOSE. See the GNU Lesser General Public License for more ####
+#### details. ####
+#### ####
+#### You should have received a copy of the GNU Lesser General ####
+#### Public License along with this source; if not, download it ####
+#### from http://www.opencores.org/lgpl.shtml ####
+#### ####
+######################################################################
+
+
+
+from misc import opposite, adder, register
+from myhdl import Signal, intbv, always_comb, instance
+
+def partDistance(a, b, y1, y2, res, ref = intbv(0, 0, 8)):
+ """ Partial distance from (a, b, y1, y2) = ref.
+
+ ref -- reference to compute the distance from
+ a, b, y1, y2 -- in : decoder input signals, coded with n bits
+ res -- out : partial distance signal, coded with (n + 2) bits
+
+ """
+ @instance
+ def partDistanceLogic():
+ while 1:
+ if ref[2] == 0:
+ bSigned = b.val
+ else:
+ bSigned = -b.val
+ if ref[1] == 0:
+ y1Signed = y1.val
+ else:
+ y1Signed = -y1.val
+ if ref[0] == 0:
+ y2Signed = y2.val
+ else:
+ y2Signed = -y2.val
+ res.next = a.val + bSigned + y1Signed + y2Signed
+ yield a, b, y1, y2
+ return partDistanceLogic
+
+def distance(partDist, z, dist, n = 4):
+ """ Distance computation.
+
+ n -- number of bits for the coding of the decoder input signals
+ partDist -- in : sum of the decoder input signals
+ z -- in : extrinsic information
+ dist -- out : distance
+
+ """
+ @always_comb
+ def distanceLogic():
+ dist.next = (4 * (2 ** (n - 1) - 1) + partDist.val) / 2 + z.val
+ return distanceLogic
+
+def distances(a, b, y1, y2, z, distance16, n = 4):
+ """ Computes the 16 distances from the decoder input signals.
+
+ n -- number of bits for the coding of the decoder input signals
+ a, b, y1, y2 -- in : decoder input signals, coded with n bits
+ z -- in : extrinsic information signals (x4), coded with m bits
+ distance16 -- out : distance signals (x16)
+
+ """
+ partDist = [Signal(intbv(0, -(2**(n+1)), 2**(n+1))) for i in range(16)]
+ opposite_i = [None for i in range(8)]
+ distance_i = [None for i in range(16)]
+ partDistance_i = [None for i in range(8)]
+ for i in range(8):
+ partDistance_i[i] = partDistance(a, b, y1, y2, partDist[i], intbv(i, 0, 8))
+ for i in range(8):
+ opposite_i[i] = opposite(partDist[i], partDist[15 - i])
+ for i in range(16):
+ distance_i[i] = distance(partDist[i], z[i / 4], distance16[i], n)
+
+ return partDistance_i, opposite_i, distance_i
+
+def reduction(org, chd, q = 8):
+ """ (Reduction: if anyone's q(th) bit is set, divide everyone by 2.)
+ Temporary test: when everyone's q(th) bit is set, reset everyone's q(th) bit.
+
+ q -- accumulated distance width
+ org -- in : original array of 8 q-bit accumulated distances
+ chd -- out : reduced array of 8 q-bit accumulated distances
+
+ """
+# tmp = intbv(0, 0, 2**q)
+ @instance
+ def reductionLogic():
+ while 1:
+# msb = bool(0)
+ msb = bool(1)
+ for i in range(8):
+# msb = msb or org[i].val[q-1]
+ msb = msb and org[i].val[q - 1]
+ for i in range(8):
+ chd[i].next[q-1:0] = org[i].val[q-1:0]
+ chd[i].next[q - 1] = (not msb) and org[i].val[q - 1]
+# if msb == 1:
+# tmp[q-1:0] = org[i].val[q:1]
+# else:
+# tmp = org[i].val
+# chd[i].next = tmp
+ yield org[0], org[1], org[2], org[3], org[4], org[5], org[6], org[7]
+ return reductionLogic
+
+def accDist(clk, rst, accDistReg, dist, accDistNew, q = 8):
+ """ Accumulated distances.
+
+ q -- in : accumulated distance width
+ clk, rst -- in : clock and negative reset
+ accDistReg -- in : original array of 8 q-bit accumulated distance registers
+ dist -- in : array of 16 distances
+ accDistNew -- out : array of 32 (q+1)-bit accumulated distances
+
+ """
+ adder_i = [None for i in range(32)]
+ register_i = [None for i in range(8)]
+ accDistOld = [Signal(intbv(0, 0, 2**q)) for i in range(8)]
+ accDistRed = [Signal(intbv(0, 0, 2**q)) for i in range(8)]
+ accDistRegSorted = [Signal(intbv(0, 0, 2**q)) for i in range(8)]
+ accDistRegDelta = [Signal(intbv(0, 0, 2**q)) for i in range(8)]
+ distIndex = [0, 7, 11, 12, 0, 7, 11, 12, 2, 5, 9, 14, 2, 5, 9, 14, 3, 4, 8, 15, 3, 4, 8, 15, 1, 6, 10, 13, 1, 6, 10, 13]
+ for i in range(32):
+ adder_i[i] = adder(accDistOld[i/4], dist[distIndex[i]], accDistNew[i])
+ reduction_i0 = reduction(accDistReg, accDistRed, q)
+ for i in range(8):
+ register_i[i] = register(clk, rst, accDistRed[i], accDistOld[i])
+
+ return adder_i, register_i, reduction_i0
Index: src/myhdl/turboTop.py
===================================================================
--- src/myhdl/turboTop.py (nonexistent)
+++ src/myhdl/turboTop.py (revision 7)
@@ -0,0 +1,161 @@
+######################################################################
+#### ####
+#### turboTop.py ####
+#### ####
+#### This file is part of the turbo decoder IP core project ####
+#### http://www.opencores.org/projects/turbocodes/ ####
+#### ####
+#### Author(s): ####
+#### - David Brochart(dbrochart@opencores.org) ####
+#### ####
+#### All additional information is available in the README.txt ####
+#### file. ####
+#### ####
+######################################################################
+#### ####
+#### Copyright (C) 2005 Authors ####
+#### ####
+#### This source file may be used and distributed without ####
+#### restriction provided that this copyright statement is not ####
+#### removed from the file and that any derivative work contains ####
+#### the original copyright notice and the associated disclaimer. ####
+#### ####
+#### This source file is free software; you can redistribute it ####
+#### and/or modify it under the terms of the GNU Lesser General ####
+#### Public License as published by the Free Software Foundation; ####
+#### either version 2.1 of the License, or (at your option) any ####
+#### later version. ####
+#### ####
+#### This source is distributed in the hope that it will be ####
+#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
+#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
+#### PURPOSE. See the GNU Lesser General Public License for more ####
+#### details. ####
+#### ####
+#### You should have received a copy of the GNU Lesser General ####
+#### Public License along with this source; if not, download it ####
+#### from http://www.opencores.org/lgpl.shtml ####
+#### ####
+######################################################################
+
+
+
+from punct import punct
+from iteration import iteration
+from permut import abPermut
+from interleaver import interleaver
+from testbench import ber, randGen, siho
+from misc import delayer
+from clock import rstGen, clkGen, clkDiv
+from coder import coder
+from noiser import noiser
+from limiter import limiter
+from myhdl import Signal, intbv, instances
+
+def turboTop(resFile, rate = 12, it = 5, n = 4, r = 5, p = 48, d = 0, mu = 8, sigma = 6, l = 20, m = 10, q = 8):
+ """ Turbo decoder top level.
+
+ resFile -- files where the results will be saved
+ rate -- code rate (e.g. 12 for rate 1/2)
+ it -- number of iterations for the turbo decoding
+ n -- number of bits for the sampling of the signals - a, b, y1, y2
+ r -- number of bits for the coding of the extrinsic information
+ p -- interleaver frame size in bit couples
+ d -- additional delay through the noiser - 0 means the noiser adds 2 clock cycles
+ mu -- mean value for the noise distribution (additive noise)
+ sigma -- standard deviation of the noise distribution (0 means no noise)
+ l -- first trellis' length
+ m -- second trellis' length
+ q -- number of bits for the coding of the accumulated distances
+
+ """
+ # Signal declarations:
+ clk = Signal(bool(0))
+ rst = Signal(bool(1))
+ flipflop = Signal(bool(0))
+ aClean = Signal(bool(0))
+ bClean = Signal(bool(0))
+ y1Clean = Signal(bool(0))
+ y2Clean = Signal(bool(0))
+ aCleanDel = Signal(bool(0))
+ bCleanDel = Signal(bool(0))
+ y1CleanDel = Signal(bool(0))
+ y2CleanDel = Signal(bool(0))
+ y1IntDel = Signal(bool(0))
+ y2IntDel = Signal(bool(0))
+ aNoisy = Signal(int(0))
+ bNoisy = Signal(int(0))
+ y1Noisy = Signal(int(0))
+ y2Noisy = Signal(int(0))
+ y1IntNoisy = Signal(int(0))
+ y2IntNoisy = Signal(int(0))
+ y1Full = Signal(intbv(0, -(2**(n-1)), 2**(n-1)))
+ y2Full = Signal(intbv(0, -(2**(n-1)), 2**(n-1)))
+ y1IntFull = Signal(intbv(0, -(2**(n-1)), 2**(n-1)))
+ y2IntFull = Signal(intbv(0, -(2**(n-1)), 2**(n-1)))
+ aLim = [Signal(intbv(0, -(2**(n-1)), 2**(n-1))) for i in range(it + 1)]
+ bLim = [Signal(intbv(0, -(2**(n-1)), 2**(n-1))) for i in range(it + 1)]
+ y1Lim = [Signal(intbv(0, -(2**(n-1)), 2**(n-1))) for i in range(it + 1)]
+ y2Lim = [Signal(intbv(0, -(2**(n-1)), 2**(n-1))) for i in range(it + 1)]
+ y1IntLim = [Signal(intbv(0, -(2**(n-1)), 2**(n-1))) for i in range(it + 1)]
+ y2IntLim = [Signal(intbv(0, -(2**(n-1)), 2**(n-1))) for i in range(it + 1)]
+ z = [[Signal(intbv(0, 0, 2**r)) for i in range(4)] for i in range(it + 1)]
+ zSorted = [Signal(intbv(0, 0, 2**r)) for i in range(4)]
+ aDec = [Signal(bool(0)) for i in range(it + 1)]
+ bDec = [Signal(bool(0)) for i in range(it + 1)]
+ aDel = [Signal(bool(0)) for i in range(it + 1)]
+ bDel = [Signal(bool(0)) for i in range(it + 1)]
+ abInt = [Signal(bool(0)) for i in range(2)]
+ y1Int = Signal(bool(0))
+ y2Int = Signal(bool(0))
+ abCleanPerm = [Signal(bool(0)) for i in range(2)]
+
+ delayer_ia = [None for i in range(it + 1)]
+ delayer_ib = [None for i in range(it + 1)]
+ ber_i = [None for i in range(it + 1)]
+ iteration_i = [None for i in range(it)]
+
+ # Reset and clock generation:
+ rstGen_i0 = rstGen(rst)
+ clkGen_i0 = clkGen(clk)
+
+ # Random data generation:
+ randGen_i0 = randGen(clk, rst, aClean, bClean)
+
+ # Interleaving and permuting:
+ clkDiv_i0 = clkDiv(clk, rst, flipflop)
+ abPermut_i0 = abPermut(flipflop, aClean, bClean, abCleanPerm, 1)
+ interleaver_i0 = interleaver(clk, rst, abCleanPerm, abInt, p, 0, 0, 2, 2, 0)
+
+ # Coder:
+ coder_i0 = coder(clk, rst, aClean, bClean, y1Clean, y2Clean)
+ coder_i1 = coder(clk, rst, abInt[1], abInt[0], y1Int, y2Int)
+
+ # Additional delay through the channel:
+ delayer_i0 = delayer(clk, rst, aClean, aCleanDel, d, 0, 2)
+ delayer_i1 = delayer(clk, rst, bClean, bCleanDel, d, 0, 2)
+ delayer_i2 = delayer(clk, rst, y1Clean, y1CleanDel, d, 0, 2)
+ delayer_i3 = delayer(clk, rst, y2Clean, y2CleanDel, d, 0, 2)
+ delayer_i4 = delayer(clk, rst, y1Int, y1IntDel, d, 0, 2)
+ delayer_i5 = delayer(clk, rst, y2Int, y2IntDel, d, 0, 2)
+
+ # Channel noiser:
+ noiser_i0 = noiser(clk, rst, aCleanDel, bCleanDel, y1CleanDel, y2CleanDel, y1IntDel, y2IntDel, aNoisy, bNoisy, y1Noisy, y2Noisy, y1IntNoisy, y2IntNoisy, n, mu, sigma)
+
+ # Decoder:
+ limiter_i0 = limiter(aNoisy, bNoisy, y1Noisy, y2Noisy, y1IntNoisy, y2IntNoisy, aLim[0], bLim[0], y1Full, y2Full, y1IntFull, y2IntFull, n)
+ punct_i0 = punct(clk, rst, y1Full, y2Full, y1IntFull, y2IntFull, y1Lim[0], y2Lim[0], y1IntLim[0], y2IntLim[0], rate)
+ for i in range(it):
+ iteration_i[i] = iteration(clk, rst, flipflop, aLim[i], bLim[i], y1Lim[i], y2Lim[i], y1IntLim[i], y2IntLim[i], z[i], z[i + 1], aDec[i + 1], bDec[i + 1], aLim[i + 1], bLim[i + 1], y1Lim[i + 1], y2Lim[i + 1], y1IntLim[i + 1], y2IntLim[i + 1], l, m, q, p, r, n, 2 * i * (l + m + 2) + 2 * i * p + 2)
+
+ # Bit Error Rate monitoring:
+ siho_i0 = siho(aLim[0], bLim[0], aDec[0], bDec[0])
+ delayer_ia[0] = delayer(clk, rst, aClean, aDel[0], 1 + d, 0, 2)
+ delayer_ib[0] = delayer(clk, rst, bClean, bDel[0], 1 + d, 0, 2)
+ ber_i[0] = ber(clk, rst, aDel[0], bDel[0], aDec[0], bDec[0], d + 100, resFile[0])
+ for i in range(it):
+ delayer_ia[i + 1] = delayer(clk, rst, aClean, aDel[i + 1], (2 * i + 1) * (l + m + 2) + 2 * i * p + d, 0, 2)
+ delayer_ib[i + 1] = delayer(clk, rst, bClean, bDel[i + 1], (2 * i + 1) * (l + m + 2) + 2 * i * p + d, 0, 2)
+ ber_i[i + 1] = ber(clk, rst, aDel[i + 1], bDel[i + 1], aDec[i + 1], bDec[i + 1], (2 * i + 1) * (l + m + 2) + 2 * i * p + d + 100, resFile[i + 1])
+
+ return rstGen_i0, clkGen_i0, randGen_i0, clkDiv_i0, abPermut_i0, interleaver_i0, coder_i0, coder_i1, delayer_i0, delayer_i1, delayer_i2, delayer_i3, delayer_i4, delayer_i5, noiser_i0, limiter_i0, punct_i0, siho_i0, delayer_ia, delayer_ib, ber_i, iteration_i
Index: src/myhdl/trellis.py
===================================================================
--- src/myhdl/trellis.py (nonexistent)
+++ src/myhdl/trellis.py (revision 7)
@@ -0,0 +1,318 @@
+######################################################################
+#### ####
+#### trellis.py ####
+#### ####
+#### This file is part of the turbo decoder IP core project ####
+#### http://www.opencores.org/projects/turbocodes/ ####
+#### ####
+#### Author(s): ####
+#### - David Brochart(dbrochart@opencores.org) ####
+#### ####
+#### All additional information is available in the README.txt ####
+#### file. ####
+#### ####
+######################################################################
+#### ####
+#### Copyright (C) 2005 Authors ####
+#### ####
+#### This source file may be used and distributed without ####
+#### restriction provided that this copyright statement is not ####
+#### removed from the file and that any derivative work contains ####
+#### the original copyright notice and the associated disclaimer. ####
+#### ####
+#### This source file is free software; you can redistribute it ####
+#### and/or modify it under the terms of the GNU Lesser General ####
+#### Public License as published by the Free Software Foundation; ####
+#### either version 2.1 of the License, or (at your option) any ####
+#### later version. ####
+#### ####
+#### This source is distributed in the hope that it will be ####
+#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
+#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
+#### PURPOSE. See the GNU Lesser General Public License for more ####
+#### details. ####
+#### ####
+#### You should have received a copy of the GNU Lesser General ####
+#### Public License along with this source; if not, download it ####
+#### from http://www.opencores.org/lgpl.shtml ####
+#### ####
+######################################################################
+
+
+
+from myhdl import Signal, posedge, negedge, intbv, always
+
+trans2state = [[0, 6, 1, 7], [2, 4, 3, 5], [5, 3, 4, 2], [7, 1, 6, 0], [1, 7, 0, 6], [3, 5, 2, 4], [4, 2, 5, 3], [6, 0, 7, 1]]
+state2trans = [[0, 2, 1, 3], [1, 3, 0, 2], [2, 0, 3, 1], [3, 1, 2, 0], [2, 0, 3, 1], [3, 1, 2, 0], [0, 2, 1, 3], [1, 3, 0, 2]]
+
+def trellis1(clk, rst, selState, selTrans, selStateL2, selStateL1, stateL1, selTransL2, l = 20):
+ """ First trellis.
+
+ l -- first trellis length
+ clk, rst -- in : clock and negative reset
+ selState -- in : selected state at time 0
+ selTrans -- in : 8 selected transitions (1 per state) at time 0
+ selStateL2 -- out : selected state at time (l - 2)
+ selStateL1 -- out : selected state at time (l - 1)
+ stateL1 -- out : 4 possible states at time (l - 1)
+ selTransL2 -- out : selected transition at time (l - 2)
+
+ """
+ reg = [[Signal(intbv(0, 0, 4)) for i in range(8)] for j in range(l)]
+ free = intbv(255, 0, 256)
+ freeBeg = [bool(1) for i in range(8)]
+ pastState = [intbv(0, 0, 8) for i in range(8)]
+ pathIdReg = [Signal(intbv(i, 0, 8)) for i in range(8)]
+ pathId = [intbv(0, 0, 8) for i in range(8)]
+ freePathId = intbv(0, 0, 8)
+ current_state = intbv(0, 0, 8)
+ outState_l2 = intbv(0, 0, 8)
+ outState_l1 = intbv(0, 0, 8)
+ state_l3 = intbv(0, 0, 4)
+ state_l2 = intbv(0, 0, 4)
+ state_l1 = intbv(0, 0, 4)
+ @always(clk.posedge, rst.negedge)
+ def trellis1Logic():
+ if rst.val == 0:
+ for i in range(4):
+ stateL1[i].next = 0
+ selStateL1.next = 0
+ selStateL2.next = 0
+ selTransL2.next = 0
+ for i in range(8):
+ pathIdReg[i].next = i
+ for j in range(l):
+ reg[j][i].next = 0
+ else:
+ free = intbv(255)
+ for i in range(8):
+ pastState[i] = trans2state[i][int(selTrans[i].val)]
+ pathId[i] = pathIdReg[pastState[i]].val
+ free[int(pathId[i])] = 0
+ freeBeg = [bool(1) for i in range(8)]
+ for i in range(8):
+ current_state = intbv(i)
+ if freeBeg[int(pathId[int(current_state)])] == 1:
+ reg[0][int(pathId[int(current_state)])].next = current_state[2:0]
+ freeBeg[int(pathId[i])] = 0
+ pathIdReg[int(current_state)].next = pathId[int(current_state)]
+ for j in range(l - 1):
+ reg[j + 1][int(pathId[int(current_state)])].next = reg[j][int(pathId[int(current_state)])].val
+ else:
+ if free[0] == 1:
+ freePathId = 0
+ if free[2:0] == 2:
+ freePathId = 1
+ if free[3:0] == 4:
+ freePathId = 2
+ if free[4:0] == 8:
+ freePathId = 3
+ if free[5:0] == 16:
+ freePathId = 4
+ if free[6:0] == 32:
+ freePathId = 5
+ if free[7:0] == 64:
+ freePathId = 6
+ if free[8:0] == 128:
+ freePathId = 7
+ reg[0][freePathId].next = current_state[2:0]
+ free[freePathId] = 0
+ pathIdReg[int(current_state)].next = freePathId
+ for j in range(l - 1):
+ reg[j + 1][freePathId].next = reg[j][int(pathId[int(current_state)])].val
+ state_l3 = reg[l - 3][int(pathId[int(selState.val)])].val
+ state_l2 = reg[l - 2][int(pathId[int(selState.val)])].val
+ state_l1 = reg[l - 1][int(pathId[int(selState.val)])].val
+ outState_l2[2] = state_l3[1] ^ (state_l3[0] ^ state_l2[1])
+ outState_l2[2:0] = state_l2
+ outState_l1[2] = state_l2[1] ^ (state_l2[0] ^ state_l1[1])
+ outState_l1[2:0] = state_l1
+ selStateL1.next = outState_l1
+ selStateL2.next = outState_l2
+ selTransL2.next = state2trans[int(outState_l2)][int(state_l1)]
+ for i in range(4):
+ stateL1[i].next = trans2state[int(outState_l2)][i]
+ if __debug__:
+ # Monitor: checks that in the first trellis, from each of the 8 states (trellis' beginning) we arrive at the same state (trellis' end).
+ # (Ignore this message until every iteration is fully started)
+ diff = 0
+ ref = intbv(0)
+ tmp = intbv(0)
+ state_l2_deb = reg[l - 2][int(pathId[7])].val
+ state_l1_deb = reg[l - 1][int(pathId[7])].val
+ ref[2] = state_l2_deb[1] ^ (state_l2_deb[0] ^ state_l1_deb[1])
+ ref[2:0] = state_l1_deb
+ for i in range(7):
+ state_l2_deb = reg[l - 2][int(pathId[i])].val
+ state_l1_deb = reg[l - 1][int(pathId[i])].val
+ tmp[2] = state_l2_deb[1] ^ (state_l2_deb[0] ^ state_l1_deb[1])
+ tmp[2:0] = state_l1_deb
+ if ref != tmp:
+ diff = 1
+ if diff == 1:
+ print "WARNING: all paths don't arrive at same state at end of first trellis (you should think about increasing its length)"
+ return trellis1Logic
+
+def trellis2(clk, rst, selState, state, selTrans, weight, llr0, llr1, llr2, llr3, a, b, m = 10, q = 8):
+ """ Second trellis and revision logic.
+
+ m -- second trellis length
+ q -- accumulated distance width
+ clk, rst -- in : clock and negative reset
+ selState -- in : selected state at time (l - 1)
+ state -- in : 4 possible states at time (l - 1)
+ selTrans -- in : 8 selected transitions (1 per state) at time (l - 1)
+ weight -- in : four weights sorted by transition code at time (l - 1)
+ llr0 -- out : LLR for (a, b) = (0, 0) at time (l + m - 1)
+ llr1 -- out : LLR for (a, b) = (0, 1) at time (l + m - 1)
+ llr2 -- out : LLR for (a, b) = (1, 0) at time (l + m - 1)
+ llr3 -- out : LLR for (a, b) = (1, 1) at time (l + m - 1)
+ a, b -- out : decoded values of (a, b) at time (l + m - 1)
+
+ """
+ reg = [[Signal(intbv(0, 0, 4)) for i in range(8)] for j in range(m)]
+ free = intbv(255, 0, 256)
+ freeBeg = [bool(1) for i in range(8)]
+ pastState = [intbv(0, 0, 8) for i in range(8)]
+ pathIdReg = [Signal(intbv(i, 0, 8)) for i in range(8)]
+ pathId = [intbv(0, 0, 8) for i in range(8)]
+ freePathId = intbv(0, 0, 8)
+ revWeight = [[Signal(intbv(0, 0, 2**q)) for i in range(m)] for j in range(4)]
+ revWeightTmp = [[intbv(0, 0, 2**q) for i in range(m)] for j in range(4)]
+ revWeightFilt = [intbv(0, 0, 2**q) for j in range(3)]
+ op = [intbv(0, 0, 2**q) for i in range(4)]
+ tmp = [intbv(0, 0, 2**q) for i in range(4)]
+ tmp4 = intbv(0, 0, 2**(q+1))
+ notZero = [[intbv(0, 0, 4) for i in range(3)] for j in range(2)]
+ ind = [[intbv(0, 0, 4) for i in range(3)] for j in range(2)]
+ minTmp = [bool(0) for i in range(3)]
+ @always(clk.posedge, rst.negedge)
+ def trellis2Logic():
+ if rst.val == 0:
+ for i in range(4):
+ for j in range(m):
+ revWeight[i][j].next = 0
+ a.next = 0
+ b.next = 0
+ llr0.next = 0
+ llr1.next = 0
+ llr2.next = 0
+ llr3.next = 0
+ for i in range(8):
+ pathIdReg[i].next = i
+ for j in range(m):
+ reg[j][i].next = 0
+ else:
+ free = intbv(255)
+ for i in range(8):
+ pastState[i] = trans2state[i][int(selTrans[i].val)]
+ pathId[i] = pathIdReg[pastState[i]].val
+ free[int(pathId[i])] = 0
+ freeBeg = [bool(1) for i in range(8)]
+ for i in range(8):
+ if freeBeg[int(pathId[i])] == 1:
+ reg[0][int(pathId[i])].next = selTrans[i].val
+ freeBeg[int(pathId[i])] = 0
+ pathIdReg[i].next = pathId[i]
+ for j in range(m - 1):
+ reg[j + 1][int(pathId[i])].next = reg[j][int(pathId[i])].val
+ else:
+ if free[1:0] == 1:
+ freePathId = 0
+ if free[2:0] == 2:
+ freePathId = 1
+ if free[3:0] == 4:
+ freePathId = 2
+ if free[4:0] == 8:
+ freePathId = 3
+ if free[5:0] == 16:
+ freePathId = 4
+ if free[6:0] == 32:
+ freePathId = 5
+ if free[7:0] == 64:
+ freePathId = 6
+ if free[8:0] == 128:
+ freePathId = 7
+ reg[0][freePathId].next = selTrans[i].val
+ free[freePathId] = 0
+ pathIdReg[i].next = freePathId
+ for j in range(m - 1):
+ reg[j + 1][freePathId].next = reg[j][int(pathId[i])].val
+ a.next = reg[m - 1][int(pathId[int(selState.val)])].val[1]
+ b.next = reg[m - 1][int(pathId[int(selState.val)])].val[0]
+ for i in range(4):
+ for j in range(m - 1):
+ for k in range(4):
+ if reg[j][int(pathId[int(state[k].val)])].val == i and state[k].val != selState.val:
+ op[k] = weight[k].val
+ else:
+ op[k] = (2 ** q) - 1
+ if op[0] < op[1]:
+ tmp[0] = op[0]
+ else:
+ tmp[0] = op[1]
+ if op[2] < op[3]:
+ tmp[1] = op[2]
+ else:
+ tmp[1] = op[3]
+ if tmp[0] < tmp[1]:
+ tmp[2] = tmp[0]
+ else:
+ tmp[2] = tmp[1]
+ if tmp[2] < revWeight[i][j].val:
+ revWeightTmp[i][j + 1] = tmp[2]
+ else:
+ revWeightTmp[i][j + 1] = revWeight[i][j].val
+ revWeightTmp[i][0] = weight[i].val
+ for j in range(2):
+ if revWeightTmp[0][j] == 0:
+ notZero[j] = [1, 2, 3]
+ elif revWeightTmp[1][j] == 0:
+ notZero[j] = [0, 2, 3]
+ elif revWeightTmp[2][j] == 0:
+ notZero[j] = [0, 1, 3]
+ elif revWeightTmp[3][j] == 0:
+ notZero[j] = [0, 1, 2]
+ if revWeightTmp[int(notZero[j][0])][j] <= revWeightTmp[int(notZero[j][1])][j]:
+ minTmp[0] = 0
+ else:
+ minTmp[0] = 1
+ if revWeightTmp[int(notZero[j][0])][j] <= revWeightTmp[int(notZero[j][2])][j]:
+ minTmp[1] = 0
+ else:
+ minTmp[1] = 1
+ if revWeightTmp[int(notZero[j][1])][j] <= revWeightTmp[int(notZero[j][2])][j]:
+ minTmp[2] = 0
+ else:
+ minTmp[2] = 1
+ if minTmp == [0, 0, 0]:
+ ind[j] = [0, 1, 2]
+ elif minTmp == [0, 0, 1]:
+ ind[j] = [0, 2, 1]
+ elif minTmp == [1, 0, 0]:
+ ind[j] = [1, 0, 2]
+ elif minTmp == [0, 1, 1]:
+ ind[j] = [1, 2, 0]
+ elif minTmp == [1, 1, 0]:
+ ind[j] = [2, 0, 1]
+ elif minTmp == [1, 1, 1]:
+ ind[j] = [2, 1, 0]
+ else:
+ print "ERROR: Configuration does not exist", minTmp
+ for i in range(3):
+ tmp[3] = revWeightTmp[int(notZero[0][int(ind[0][i])])][0]
+ tmp4 = revWeightTmp[int(notZero[1][int(ind[1][i])])][1] + (2 ** (q - 4))
+ if tmp[3] < tmp4:
+ revWeightFilt[int(ind[0][i])] = tmp[3]
+ else:
+ revWeightFilt[int(ind[0][i])] = intbv(tmp4)[q:0]
+ for i in range(3):
+ revWeightTmp[int(notZero[0][i])][0] = revWeightFilt[i]
+ for i in range(4):
+ for j in range(m):
+ revWeight[i][j].next = revWeightTmp[i][j]
+ llr0.next = revWeight[0][m - 1]
+ llr1.next = revWeight[1][m - 1]
+ llr2.next = revWeight[2][m - 1]
+ llr3.next = revWeight[3][m - 1]
+ return trellis2Logic
Index: src/myhdl/testbench.py
===================================================================
--- src/myhdl/testbench.py (nonexistent)
+++ src/myhdl/testbench.py (revision 7)
@@ -0,0 +1,219 @@
+######################################################################
+#### ####
+#### testbench.py ####
+#### ####
+#### This file is part of the turbo decoder IP core project ####
+#### http://www.opencores.org/projects/turbocodes/ ####
+#### ####
+#### Author(s): ####
+#### - David Brochart(dbrochart@opencores.org) ####
+#### ####
+#### All additional information is available in the README.txt ####
+#### file. ####
+#### ####
+######################################################################
+#### ####
+#### Copyright (C) 2005 Authors ####
+#### ####
+#### This source file may be used and distributed without ####
+#### restriction provided that this copyright statement is not ####
+#### removed from the file and that any derivative work contains ####
+#### the original copyright notice and the associated disclaimer. ####
+#### ####
+#### This source file is free software; you can redistribute it ####
+#### and/or modify it under the terms of the GNU Lesser General ####
+#### Public License as published by the Free Software Foundation; ####
+#### either version 2.1 of the License, or (at your option) any ####
+#### later version. ####
+#### ####
+#### This source is distributed in the hope that it will be ####
+#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
+#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
+#### PURPOSE. See the GNU Lesser General Public License for more ####
+#### details. ####
+#### ####
+#### You should have received a copy of the GNU Lesser General ####
+#### Public License along with this source; if not, download it ####
+#### from http://www.opencores.org/lgpl.shtml ####
+#### ####
+######################################################################
+
+
+
+from random import randrange
+from myhdl import Signal, posedge, negedge, always, instance
+
+def randGen(clk, rst, a, b):
+ """ Random signal generator.
+
+ clk, rst -- in : clock and negative reset
+ a, b -- out : generated random signals
+
+ """
+# x = Signal(int(0))
+ @always(clk.posedge, rst.negedge)
+ def randGenLogic():
+ if rst.val == 0:
+ a.next = 0
+ b.next = 0
+# x.next = 0
+ else:
+ a.next = randrange(2)
+ b.next = randrange(2)
+
+# a.next = 1
+# b.next = 1
+
+# if x.val == 0:
+# a.next = 1
+# b.next = 0
+# x.next = 1
+# if x.val == 1:
+# a.next = 0
+# b.next = 1
+# x.next = 2
+# if x.val == 2:
+# a.next = 0
+# b.next = 0
+# x.next = 0
+
+# if x.val == 0:
+# a.next = 0
+# b.next = 1
+# x.next = 1
+# else:
+# a.next = 0
+# b.next = 1
+ return randGenLogic
+
+def ber(clk, rst, aOrg, bOrg, aDec, bDec, wait, resFile):
+ """ Bit Error Rate monitor.
+
+ it -- iteration number (0 is before decoding)
+ clk, rst -- in : clock and negative reset
+ aOrg, bOrg -- in : original data
+ aDec, bDec -- in : decoded data
+ wait -- in : number of clock cycles to wait before computing the BER
+ resFile -- out : file where the BER is saved
+
+ """
+ ber = Signal(0.0)
+ cnt = Signal(0)
+ diffCnt = Signal(0)
+ waitCnt = Signal(0)
+ @always(clk.posedge, rst.negedge)
+ def berLogic():
+ if rst.val == 0:
+ orgCnt = 0
+ j = 0
+ waitCnt.next = 0
+ else:
+ if waitCnt == wait:
+ cnt.next = cnt + 1
+ if aOrg.val != aDec.val:
+ diffCnt.next = diffCnt + 1
+ if bOrg.val != bDec.val:
+ diffCnt.next = diffCnt + 1
+ ber.next = float(diffCnt.next) / float(2 * cnt.next)
+ resFile.write('%1.10f\n' % ber.next)
+ if (cnt.next % 100) == 0:
+ resFile.flush()
+ else:
+ waitCnt.next = waitCnt + 1
+ return berLogic
+
+def siho(aSoft, bSoft, aHard, bHard):
+ """ Soft Input Hard Output decision.
+
+ aSoft, bSoft -- in : soft inputs
+ aHard, bHard -- out : hard outputs
+
+ """
+ @instance
+ def sihoLogic():
+ while 1:
+ if aSoft.val < 0:
+ aHard.next = 0
+ else:
+ aHard.next = 1
+ if bSoft.val < 0:
+ bHard.next = 0
+ else:
+ bHard.next = 1
+ yield aSoft, bSoft
+ return sihoLogic
+
+def monitor(clk, rst, *args):
+ """ Signal monitor.
+
+ clk, rst -- in : clock and negative reset
+ args -- in : list of signals to monitor
+
+ """
+ @always(clk.posedge, rst.negedge)
+ def monitorLogic():
+ if rst.val != 0:
+ for arg in args:
+ print "%3d" % int(arg),
+ print
+ return monitorLogic
+
+def sorter(clk, rst, *args):
+ """ Sorter.
+
+ clk, rst -- in : clock and negative reset
+ args -- in/out : arguments to be sorted / sorted arguments (first half is input / second half is output)
+
+ """
+ argNb = len(args) / 2
+ @always(clk.posedge, rst.negedge)
+ def sorterLogic():
+ if rst.val == 0:
+ for i in range(argNb):
+ args[i + argNb].next = 0
+ else:
+ arr = []
+ for i in range(argNb):
+ arr.append(int(args[i].val))
+ arr.sort()
+ for i in range(argNb):
+ args[i + argNb].next = arr[i]
+ return sorterLogic
+
+def sorter(*args):
+ """ Sorter.
+
+ args -- in/out : data to be sorted / sorted data (first half is input / second half is output)
+
+ """
+ argNb = len(args) / 2
+ @instance
+ def sorterLogic():
+ while 1:
+ arr = []
+ for i in range(argNb):
+ arr.append(int(args[i].val))
+ arr.sort()
+ for i in range(argNb):
+ args[i + argNb].next = arr[i]
+ yield args
+ return sorterLogic
+
+def delta(*args):
+ """ Removes the minimum value from all values.
+
+ args -- in/out : original data / delta data (first half is input / second half is output)
+
+ """
+ argNb = len(args) / 2
+ @instance
+ def deltaLogic():
+ while 1:
+ arr = []
+ for i in range(argNb):
+ arr.append(int(args[i].val))
+ minimum = min(arr)
+ for i in range(argNb):
+ args[i + argNb].next = arr[i] - minimum
+ yield args
+ return deltaLogic
Index: src/myhdl/interleaver.py
===================================================================
--- src/myhdl/interleaver.py (nonexistent)
+++ src/myhdl/interleaver.py (revision 7)
@@ -0,0 +1,189 @@
+######################################################################
+#### ####
+#### interleaver.py ####
+#### ####
+#### This file is part of the turbo decoder IP core project ####
+#### http://www.opencores.org/projects/turbocodes/ ####
+#### ####
+#### Author(s): ####
+#### - David Brochart(dbrochart@opencores.org) ####
+#### ####
+#### All additional information is available in the README.txt ####
+#### file. ####
+#### ####
+######################################################################
+#### ####
+#### Copyright (C) 2005 Authors ####
+#### ####
+#### This source file may be used and distributed without ####
+#### restriction provided that this copyright statement is not ####
+#### removed from the file and that any derivative work contains ####
+#### the original copyright notice and the associated disclaimer. ####
+#### ####
+#### This source file is free software; you can redistribute it ####
+#### and/or modify it under the terms of the GNU Lesser General ####
+#### Public License as published by the Free Software Foundation; ####
+#### either version 2.1 of the License, or (at your option) any ####
+#### later version. ####
+#### ####
+#### This source is distributed in the hope that it will be ####
+#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
+#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
+#### PURPOSE. See the GNU Lesser General Public License for more ####
+#### details. ####
+#### ####
+#### You should have received a copy of the GNU Lesser General ####
+#### Public License along with this source; if not, download it ####
+#### from http://www.opencores.org/lgpl.shtml ####
+#### ####
+######################################################################
+
+
+
+from myhdl import Signal, intbv, posedge, negedge, always
+
+def interleaver(clk, rst, d, q, frSize = 48, delay = 0, minVal = 0, maxVal = 2, dim = 2, way = 0):
+ """ DVB-RCS (de)interleaver.
+
+ frSize -- frame size
+ delay -- number of clock cycles to wait before starting the (de)interleaver
+ minVal, maxVal -- min and max values of the stored signals
+ dim -- number of dimensions of the stored signals
+ way -- 0 for interleaving, 1 for deinterleaving
+ clk, rst -- in : clock and negative reset
+ d -- in : input data
+ q -- out : interleaved data
+
+ """
+ array1 = [[Signal(intbv(0, minVal, maxVal)) for l in range(dim)] for k in range(frSize)]
+ array2 = [[Signal(intbv(0, minVal, maxVal)) for l in range(dim)] for k in range(frSize)]
+ full = Signal(bool(0))
+ i = Signal(intbv(0, 0, frSize))
+ j = Signal(intbv(0, 0, frSize))
+ iTmp = Signal(intbv(0, 0, frSize))
+ iTmp1 = intbv(0, 0, 2 * frSize)
+ iTmp2 = intbv(0, 0, 2 * frSize)
+ iTmp3 = intbv(0, 0, 2 * frSize)
+ cnt = Signal(intbv(0, 0, delay + 1))
+ if frSize == 48:
+ p0 = 11
+ p1 = 24
+ p2 = 0
+ p3 = 24
+ elif frSize == 64:
+ p0 = 7
+ p1 = 34
+ p2 = 32
+ p3 = 2
+ elif frSize == 212:
+ p0 = 13
+ p1 = 106
+ p2 = 108
+ p3 = 2
+ elif frSize == 220:
+ p0 = 23
+ p1 = 112
+ p2 = 4
+ p3 = 116
+ elif frSize == 228:
+ p0 = 17
+ p1 = 116
+ p2 = 72
+ p3 = 188
+ elif frSize == 424:
+ p0 = 11
+ p1 = 6
+ p2 = 8
+ p3 = 2
+ elif frSize == 432:
+ p0 = 13
+ p1 = 0
+ p2 = 4
+ p3 = 8
+ elif frSize == 440:
+ p0 = 13
+ p1 = 10
+ p2 = 4
+ p3 = 2
+ elif frSize == 848:
+ p0 = 19
+ p1 = 2
+ p2 = 16
+ p3 = 6
+ elif frSize == 856:
+ p0 = 19
+ p1 = 428
+ p2 = 224
+ p3 = 652
+ elif frSize == 864:
+ p0 = 19
+ p1 = 2
+ p2 = 16
+ p3 = 6
+ elif frSize == 752:
+ p0 = 19
+ p1 = 376
+ p2 = 224
+ p3 = 600
+ else:
+ print "ERROR: interleaver does not have a valid DVB-RCS frame size!"
+ @always(clk.posedge, rst.negedge)
+ def interleaverLogic():
+ if rst.val == 0:
+ iTmp.next = 0
+ i.next = 0
+ j.next = 0
+ cnt.next = 0
+ full.next = 0
+ for l in range(dim):
+ q[l].next = 0
+ for k in range(frSize):
+ for l in range(dim):
+ array1[k][l].next = 0
+ array2[k][l].next = 0
+ else:
+ if cnt.val < delay:
+ cnt.next = cnt.val + 1
+ else:
+ if j.val[2:0] == 0:
+ p = 0
+ elif j.val[2:0] == 1:
+ p = frSize / 2 + p1
+ elif j.val[2:0] == 2:
+ p = p2
+ else: # if j.val[2:0] == 3:
+ p = frSize / 2 + p3
+ iTmp1 = iTmp.val + p0
+ if iTmp1 >= frSize:
+ iTmp2 = iTmp1 - frSize
+ else:
+ iTmp2 = iTmp1
+ iTmp.next = iTmp2
+ iTmp3 = iTmp2 + p + 1
+ if iTmp3 >= 2 * frSize:
+ i.next = iTmp3 - 2 * frSize
+ elif iTmp3 >= frSize:
+ i.next = iTmp3 - frSize
+ else:
+ i.next = iTmp3
+# i.next = intbv((p0 * j.val + p + 1) % frSize)
+ if j.val == (frSize - 1):
+ j.next = 0
+ full.next = not full.val
+ else:
+ j.next = j.val + 1
+ if way == 0:
+ ii = i.val
+ jj = j.val
+ else:
+ ii = j.val
+ jj = i.val
+ if full.val == 0:
+ for l in range(dim):
+ array1[int(jj)][l].next = d[l].val
+ q[l].next = array2[int(ii)][l].val
+ else:
+ for l in range(dim):
+ array2[int(jj)][l].next = d[l].val
+ q[l].next = array1[int(ii)][l].val
+ return interleaverLogic
Index: src/myhdl/launchTurbo.py
===================================================================
--- src/myhdl/launchTurbo.py (nonexistent)
+++ src/myhdl/launchTurbo.py (revision 7)
@@ -0,0 +1,148 @@
+######################################################################
+#### ####
+#### launchTurbo.py ####
+#### ####
+#### This file is part of the turbo decoder IP core project ####
+#### http://www.opencores.org/projects/turbocodes/ ####
+#### ####
+#### Author(s): ####
+#### - David Brochart(dbrochart@opencores.org) ####
+#### ####
+#### All additional information is available in the README.txt ####
+#### file. ####
+#### ####
+######################################################################
+#### ####
+#### Copyright (C) 2005 Authors ####
+#### ####
+#### This source file may be used and distributed without ####
+#### restriction provided that this copyright statement is not ####
+#### removed from the file and that any derivative work contains ####
+#### the original copyright notice and the associated disclaimer. ####
+#### ####
+#### This source file is free software; you can redistribute it ####
+#### and/or modify it under the terms of the GNU Lesser General ####
+#### Public License as published by the Free Software Foundation; ####
+#### either version 2.1 of the License, or (at your option) any ####
+#### later version. ####
+#### ####
+#### This source is distributed in the hope that it will be ####
+#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
+#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
+#### PURPOSE. See the GNU Lesser General Public License for more ####
+#### details. ####
+#### ####
+#### You should have received a copy of the GNU Lesser General ####
+#### Public License along with this source; if not, download it ####
+#### from http://www.opencores.org/lgpl.shtml ####
+#### ####
+######################################################################
+
+
+
+from math import sqrt
+from turboTop import turboTop
+from args import getArgs
+from myhdl import Simulation, traceSignals
+
+args = getArgs('-rate', '-iter', '-vcd', '-time', '-snr', '-help', '-sig', '-ext', '-trel1', '-trel2', '-dist', '-int', '-delay')
+rate = args['-rate']
+vcd = args['-vcd']
+time = args['-time']
+snr = args['-snr']
+help = args['-help']
+sig = args['-sig']
+ext = args['-ext']
+trel1 = args['-trel1']
+trel2 = args['-trel2']
+dist = args['-dist']
+inter = args['-int']
+dela = args['-delay']
+iter = args['-iter']
+if help == 'on':
+ print "python launchTurbo.py"
+ print " [-help] : prints this message"
+ print " [-iter val] : number of iterations for the turbo decoding (default: 5)"
+ print " [-snr val] : specifies the signal-to-noise ratio in dB (default: 5.1 dB)"
+ print " [-vcd on/off] : turns on/off the signal logging into a VCD file (default: off)"
+ print " [-time val] : time to run the simulation (default: forever)"
+ print " [-sig val] : number of bits for the quantization of the signals - a, b, y1, y2 (default: 4)"
+ print " [-ext val] : number of bits for the coding of the extrinsic information (default: 5)"
+ print " [-trel1 val] : first trellis' length (default: 24)"
+ print " [-trel2 val] : second trellis' length (default: 12)"
+ print " [-dist val] : number of bits for the coding of the accumulated distances (default: 9)"
+ print " [-int val] : interleaver frame size in bit couples - valid values are 48, 64, 212, 220, 228, 424, 432, 440, 848, 856, 864, 752 (default: 64)"
+ print " [-delay val] : additional delay through the noiser - 0 means the noiser adds 1 clock cycle (default: 0)"
+ print " [-rate val] : code rate (e.g. 13 for rate 1/3) - valid values are 13, 25, 12, 23, 34, 45, 67 (default is 12)"
+else:
+ if rate != None:
+ rate = int(rate) # code rate (e.g. 13 for rate 1/3)
+ else:
+ rate = 12
+ if iter != None:
+ it = int(iter)
+ else:
+ it = 5 # number of iterations for the turbo decoding
+ if sig != None:
+ n = int(sig)
+ else:
+ n = 4 # number of bits for the quantization of the signals - a, b, y1, y2
+ if ext != None:
+ r = int(ext)
+ else:
+ r = 5 # number of bits for the coding of the extrinsic information
+ if trel1 != None:
+ l = int(trel1)
+ else:
+ l = 24 # first trellis' length
+ if trel2 != None:
+ m = int(trel2)
+ else:
+ m = 12 # second trellis' length
+ if dist != None:
+ q = int(dist)
+ else:
+ q = 9 # number of bits for the coding of the accumulated distances
+ if inter != None:
+ p = int(inter)
+ else:
+ p = 64 # interleaver frame size in bit couples
+ if dela != None:
+ d = int(dela) + 1
+ else:
+ d = 1 # additional delay through the noiser - 0 means the noiser adds 2 clock cycles
+ if snr == None:
+ snr = 5.1 # signal-to-noise ratio in dB
+ sigma = sqrt(((2 ** (n - 1) - 1) ** 2)/(10 ** (float(snr) / 10))) # standard deviation of the noise distribution
+ if time != None:
+ time = int(time) # time to run the simulation
+ else:
+ time = None
+ mu = 2**(n - 1) # mean value of the noise distribution (additive noise)
+ print "Parameters of the simulation:"
+ print "-----------------------------"
+ print
+ print it, "iterations for the turbo decoding"
+ print n, "bits for the quantization of the signals - a, b, y1, y2"
+ print r, "bits for the coding of the extrinsic information"
+ print "The length of the first trellis is", l
+ print "The length of the second trellis is", m
+ print q, "bits for the coding of the accumulated distances"
+ print "The interleaver has a frame size of", p, "bit couples"
+ print "There is an additional delay through the noiser of", (d - 1), "clock cycle(s) - 0 means the noiser adds 2 clock cycles"
+ print "The signal-to-noise ratio is", snr, "dB"
+ print "The code rate is", str(rate)[0], "/", str(rate)[1]
+ print
+ print
+ print
+ resFile = [None for i in range(it + 1)]
+ for i in range(it + 1):
+ resFile[i] = open('./turbo' + str(i) + '.txt', 'w')
+ if vcd == 'on':
+ turbo = traceSignals(turboTop, resFile, rate, it, n, r, p, d, mu, sigma, l, m, q)
+ else:
+ turbo = turboTop(resFile, rate, it, n, r, p, d, mu, sigma, l, m, q)
+ sim = Simulation(turbo)
+ sim.run(time)
+ for i in range(it + 1):
+ resFile[i].close
Index: src/vhdl/mux2_e.vhd
===================================================================
--- src/vhdl/mux2_e.vhd (nonexistent)
+++ src/vhdl/mux2_e.vhd (revision 7)
@@ -0,0 +1,53 @@
+----------------------------------------------------------------------
+---- ----
+---- mux2_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity mux2 is -- 2-input mux
+ port (
+ in1 : in std_logic_vector; -- first input signal
+ in2 : in std_logic_vector; -- second input signal
+ sel : in std_logic; -- 1-bit control signal
+ outSel : out std_logic_vector -- selected output signal
+ );
+end mux2;
Index: src/vhdl/reduction_e.vhd
===================================================================
--- src/vhdl/reduction_e.vhd (nonexistent)
+++ src/vhdl/reduction_e.vhd (revision 7)
@@ -0,0 +1,52 @@
+----------------------------------------------------------------------
+---- ----
+---- reduction_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.turbopack.all;
+
+entity reduction is -- metric reduction: when everyone's MSb is set, reset everyone's MSb
+ port (
+ org : in ARRAY8a; -- original array of 8 accumulated distances
+ chd : out ARRAY8a -- reduced array of 8 accumulated distances
+ );
+end reduction;
Index: src/vhdl/mux4_e.vhd
===================================================================
--- src/vhdl/mux4_e.vhd (nonexistent)
+++ src/vhdl/mux4_e.vhd (revision 7)
@@ -0,0 +1,56 @@
+----------------------------------------------------------------------
+---- ----
+---- mux4_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.turbopack.all;
+
+entity mux4 is -- 4-input mux
+ port (
+ in1 : in std_logic_vector; -- first input signal
+ in2 : in std_logic_vector; -- second input signal
+ in3 : in std_logic_vector; -- third input signal
+ in4 : in std_logic_vector; -- fourth input signal
+ sel : in std_logic_vector(1 downto 0); -- 2-bit control signal
+ outSel : out std_logic_vector -- selected output signal
+ );
+end mux4;
Index: src/vhdl/distances_synth.vhd
===================================================================
--- src/vhdl/distances_synth.vhd (nonexistent)
+++ src/vhdl/distances_synth.vhd (revision 7)
@@ -0,0 +1,71 @@
+----------------------------------------------------------------------
+---- ----
+---- distances_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of distances is
+ signal partDist : ARRAY16b;
+begin
+ partDistance_g : for i in 0 to 7 generate
+ partDistance_i : partDistance generic map (
+ ref => i
+ )
+ port map (
+ a => a,
+ b => b,
+ y => y,
+ w => w,
+ res => partDist(i)
+ );
+ end generate;
+ opposite_g : for i in 0 to 7 generate
+ opposite_i : opposite port map (
+ pos => partDist(i),
+ neg => partDist(15 - i)
+ );
+ end generate;
+ distance_g : for i in 0 to 15 generate
+ distance_i : distance port map (
+ partDist => partDist(i),
+ z => z(i / 4),
+ dist => distance16(i)
+ );
+ end generate;
+end;
Index: src/vhdl/iteration_e.vhd
===================================================================
--- src/vhdl/iteration_e.vhd (nonexistent)
+++ src/vhdl/iteration_e.vhd (revision 7)
@@ -0,0 +1,72 @@
+----------------------------------------------------------------------
+---- ----
+---- iteration_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.turbopack.all;
+
+entity iteration is -- decoding iteration top level (two SOVAs)
+ generic (
+ delay : integer := 0 -- additional delay created by the previous iterations
+ );
+ port (
+ clk : in std_logic; -- clock
+ rst : in std_logic; -- negative reset
+ flipflop : in std_logic; -- permutation control signal (on/off)
+ a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ y : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ w : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ yInt : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ wInt : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ zin : in ARRAY4c; -- extrinsic information from the previous iteration
+ zout : out ARRAY4c; -- extrinsic information to the next iteration
+ aDec : out std_logic; -- decoded signal
+ bDec : out std_logic; -- decoded signal
+ aDel : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal
+ bDel : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal
+ yDel : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal
+ wDel : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal
+ yIntDel : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal
+ wIntDel : out std_logic_vector(SIG_WIDTH - 1 downto 0) -- delayed received decoder signal
+ );
+end iteration;
Index: src/vhdl/trellis2_e.vhd
===================================================================
--- src/vhdl/trellis2_e.vhd (nonexistent)
+++ src/vhdl/trellis2_e.vhd (revision 7)
@@ -0,0 +1,63 @@
+----------------------------------------------------------------------
+---- ----
+---- trellis2_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use work.turbopack.all;
+
+entity trellis2 is -- second trellis
+ port (
+ clk : in std_logic; -- clock
+ rst : in std_logic; -- negative reset
+ selState : in std_logic_vector(2 downto 0); -- selected state at time (l - 1)
+ state : in ARRAY4d; -- 4 possible states at time (l - 1)
+ selTrans : in ARRAY8b; -- 8 selected transitions (1 per state) at time (l - 1)
+ weight : in ARRAY4a; -- four weights sorted by transition code at time (l - 1)
+ llr0 : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (0, 0) at time (l + m - 1)
+ llr1 : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (0, 1) at time (l + m - 1)
+ llr2 : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (1, 0) at time (l + m - 1)
+ llr3 : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (1, 1) at time (l + m - 1)
+ a : out std_logic; -- decoded value of a at time (l + m - 1)
+ b : out std_logic -- decoded value of b at time (l + m - 1)
+ );
+end trellis2;
Index: src/vhdl/mux8_e.vhd
===================================================================
--- src/vhdl/mux8_e.vhd (nonexistent)
+++ src/vhdl/mux8_e.vhd (revision 7)
@@ -0,0 +1,53 @@
+----------------------------------------------------------------------
+---- ----
+---- mux8_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.turbopack.all;
+
+entity mux8 is -- 8-input mux (4 bits per input)
+ port (
+ in8x4 : in ARRAY32c; -- 4x8 input signals
+ sel : in std_logic_vector(2 downto 0); -- 3-bit control signal
+ outSel4 : out ARRAY4a -- selected output signals
+ );
+end mux8;
Index: src/vhdl/opposite_e.vhd
===================================================================
--- src/vhdl/opposite_e.vhd (nonexistent)
+++ src/vhdl/opposite_e.vhd (revision 7)
@@ -0,0 +1,53 @@
+----------------------------------------------------------------------
+---- ----
+---- opposite_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use work.turbopack.all;
+
+entity opposite is -- take the opposite of a number
+ port (
+ pos : in std_logic_vector(SIG_WIDTH + 1 downto 0); -- original number
+ neg : out std_logic_vector(SIG_WIDTH + 1 downto 0) -- opposite number
+ );
+end opposite;
Index: src/vhdl/clkrst_e.vhd
===================================================================
--- src/vhdl/clkrst_e.vhd (nonexistent)
+++ src/vhdl/clkrst_e.vhd (revision 7)
@@ -0,0 +1,54 @@
+----------------------------------------------------------------------
+---- ----
+---- clkrst_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity clkrst is -- clock and reset generator
+ generic (
+ period : time := 5 ns -- clock period
+ );
+ port (
+ clk : out std_logic; -- generated clock
+ rst : out std_logic -- generated reset
+ );
+end clkrst;
Index: src/vhdl/stateSel_synth.vhd
===================================================================
--- src/vhdl/stateSel_synth.vhd (nonexistent)
+++ src/vhdl/stateSel_synth.vhd (revision 7)
@@ -0,0 +1,54 @@
+----------------------------------------------------------------------
+---- ----
+---- stateSel_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of stateSel is
+ signal tmp : std_logic_vector(6 downto 0);
+begin
+ min8_i : min8 port map (
+ op => stateDist,
+ res => tmp
+ );
+ cod3_i : cod3 port map (
+ inSig => tmp,
+ outCod => selState
+ );
+end;
Index: src/vhdl/cod3_synth.vhd
===================================================================
--- src/vhdl/cod3_synth.vhd (nonexistent)
+++ src/vhdl/cod3_synth.vhd (revision 7)
@@ -0,0 +1,53 @@
+----------------------------------------------------------------------
+---- ----
+---- cod3_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of cod3 is
+begin
+ process (inSig)
+ variable tmp : std_logic_vector(2 downto 0);
+ begin
+ tmp(0) := ((not inSig(6)) and (not inSig(5)) and (not inSig(3))) or ((not inSig(6)) and inSig(5) and (not inSig(2))) or (inSig(6) and (not inSig(4)) and (not inSig(1))) or ((inSig(6)) and (inSig(4)) and (not inSig(0)));
+ tmp(1) := ((not inSig(6)) and (not inSig(5))) or (inSig(6) and (not inSig(4)));
+ tmp(2) := not inSig(6);
+ outCod <= tmp;
+ end process;
+end;
Index: src/vhdl/accDist_e.vhd
===================================================================
--- src/vhdl/accDist_e.vhd (nonexistent)
+++ src/vhdl/accDist_e.vhd (revision 7)
@@ -0,0 +1,55 @@
+----------------------------------------------------------------------
+---- ----
+---- accDist_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.turbopack.all;
+
+entity accDist is -- accumulated distances
+ port (
+ clk : in std_logic; -- clock
+ rst : in std_logic; -- negative reset
+ accDistReg : in ARRAY8a; -- original array of 8 accumulated distance registers
+ dist : in ARRAY16a; -- array of 16 distances
+ accDistNew : out ARRAY32c -- array of 32 accumulated distances
+ );
+end accDist;
Index: src/vhdl/clkDiv_e.vhd
===================================================================
--- src/vhdl/clkDiv_e.vhd (nonexistent)
+++ src/vhdl/clkDiv_e.vhd (revision 7)
@@ -0,0 +1,53 @@
+----------------------------------------------------------------------
+---- ----
+---- clkDiv_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.turbopack.all;
+
+entity clkDiv is
+ port (
+ clk : in std_logic; -- clock
+ rst : in std_logic; -- negative reset
+ clkout : out std_logic -- clock which frequency is half of the input clock
+ );
+end clkDiv;
Index: src/vhdl/coder_synth.vhd
===================================================================
--- src/vhdl/coder_synth.vhd (nonexistent)
+++ src/vhdl/coder_synth.vhd (revision 7)
@@ -0,0 +1,62 @@
+----------------------------------------------------------------------
+---- ----
+---- coder_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of coder is
+ signal q1 : std_logic;
+ signal q2 : std_logic;
+ signal q3 : std_logic;
+begin
+ process(clk, rst)
+ begin
+ if rst = '0' then
+ q1 <= '0';
+ q2 <= '0';
+ q3 <= '0';
+ elsif clk = '1' and clk'event then
+ q1 <= a xor b xor q1 xor q3;
+ q2 <= q1 xor b;
+ q3 <= q2 xor b;
+ end if;
+ end process;
+ y <= a xor b xor q1 xor q3 xor q2 xor q3;
+ w <= a xor b xor q1 xor q3 xor q3;
+end;
Index: src/vhdl/extInf_synth.vhd
===================================================================
--- src/vhdl/extInf_synth.vhd (nonexistent)
+++ src/vhdl/extInf_synth.vhd (revision 7)
@@ -0,0 +1,97 @@
+----------------------------------------------------------------------
+---- ----
+---- extInf_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of extInf is
+begin
+ process (llr0, llr1, llr2, llr3, zin, a, b)
+ variable a_plus_b : std_logic_vector(SIG_WIDTH - 1 downto 0);
+ variable a_min_b : std_logic_vector(SIG_WIDTH - 1 downto 0);
+ variable tmp : ARRAY7a;
+ variable tmp2 : ARRAY4e;
+ begin
+ a_plus_b := std_logic_vector(conv_signed(((conv_integer(signed(a)) + conv_integer(signed(b))) / 2), SIG_WIDTH));
+ a_min_b := std_logic_vector(conv_signed(((conv_integer(signed(a)) - conv_integer(signed(b))) / 2), SIG_WIDTH));
+ tmp(0) := conv_integer(unsigned(llr0)) - conv_integer(signed(a_plus_b)) - conv_integer(unsigned(zin(0)));
+ tmp(1) := conv_integer(unsigned(llr1)) - conv_integer(signed(a_min_b)) - conv_integer(unsigned(zin(1)));
+ tmp(2) := conv_integer(unsigned(llr2)) + conv_integer(signed(a_min_b)) - conv_integer(unsigned(zin(2)));
+ tmp(3) := conv_integer(unsigned(llr3)) + conv_integer(signed(a_plus_b)) - conv_integer(unsigned(zin(3)));
+ if tmp(0) < tmp(1) then
+ tmp(4) := tmp(0);
+ else
+ tmp(4) := tmp(1);
+ end if;
+ if tmp(2) < tmp(3) then
+ tmp(5) := tmp(2);
+ else
+ tmp(5) := tmp(3);
+ end if;
+ if tmp(4) < tmp(5) then
+ tmp(6) := tmp(4);
+ else
+ tmp(6) := tmp(5);
+ end if;
+ tmp2(0) := tmp(0) - tmp(6);
+ tmp2(1) := tmp(1) - tmp(6);
+ tmp2(2) := tmp(2) - tmp(6);
+ tmp2(3) := tmp(3) - tmp(6);
+ if tmp2(0) >= (2 ** Z_WIDTH) then
+ zout(0) <= std_logic_vector(conv_unsigned((2 ** Z_WIDTH) - 1, Z_WIDTH));
+ else
+ zout(0) <= std_logic_vector(conv_unsigned(tmp2(0), Z_WIDTH));
+ end if;
+ if tmp2(1) >= (2 ** Z_WIDTH) then
+ zout(1) <= std_logic_vector(conv_unsigned((2 ** Z_WIDTH) - 1, Z_WIDTH));
+ else
+ zout(1) <= std_logic_vector(conv_unsigned(tmp2(1), Z_WIDTH));
+ end if;
+ if tmp2(2) >= (2 ** Z_WIDTH) then
+ zout(2) <= std_logic_vector(conv_unsigned((2 ** Z_WIDTH) - 1, Z_WIDTH));
+ else
+ zout(2) <= std_logic_vector(conv_unsigned(tmp2(2), Z_WIDTH));
+ end if;
+ if tmp2(3) >= (2 ** Z_WIDTH) then
+ zout(3) <= std_logic_vector(conv_unsigned((2 ** Z_WIDTH) - 1, Z_WIDTH));
+ else
+ zout(3) <= std_logic_vector(conv_unsigned(tmp2(3), Z_WIDTH));
+ end if;
+ end process;
+end;
Index: src/vhdl/abPermut_e.vhd
===================================================================
--- src/vhdl/abPermut_e.vhd (nonexistent)
+++ src/vhdl/abPermut_e.vhd (revision 7)
@@ -0,0 +1,57 @@
+----------------------------------------------------------------------
+---- ----
+---- abPermut_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.turbopack.all;
+
+entity abPermut is -- systematic information permutation
+ generic (
+ flip : integer := 0 -- initialisation (permutation on/off)
+ );
+ port (
+ flipflop : in std_logic; -- permutation control signal (on/off)
+ a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- origiral systematic information
+ b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- origiral systematic information
+ abPerm : out ARRAY2a -- permuted systematic information
+ );
+end abPermut;
Index: src/vhdl/interleaver_e.vhd
===================================================================
--- src/vhdl/interleaver_e.vhd (nonexistent)
+++ src/vhdl/interleaver_e.vhd (revision 7)
@@ -0,0 +1,59 @@
+----------------------------------------------------------------------
+---- ----
+---- interleaver_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use work.turbopack.all;
+
+entity interleaver is -- DVB-RCS (de)interleaver
+ generic (
+ delay : integer := 0; -- number of clock cycles to wait before starting the (de)interleaver
+ way : integer := 0 -- 0 for interleaving, 1 for deinterleaving
+ );
+ port (
+ clk : in std_logic; -- clock
+ rst : in std_logic; -- negative reset
+ d : in std_logic_vector; -- input data
+ q : out std_logic_vector -- (de)interleaved data
+ );
+end interleaver;
Index: src/vhdl/partDistance_e.vhd
===================================================================
--- src/vhdl/partDistance_e.vhd (nonexistent)
+++ src/vhdl/partDistance_e.vhd (revision 7)
@@ -0,0 +1,59 @@
+----------------------------------------------------------------------
+---- ----
+---- partDistance_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use work.turbopack.all;
+
+entity partDistance is
+ generic (
+ ref : integer := 0 -- reference to compute the distance from
+ );
+ port (
+ a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ y : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ w : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ res : out std_logic_vector(SIG_WIDTH + 1 downto 0) -- partial distance signal
+ );
+end partDistance;
Index: src/vhdl/delayer_e.vhd
===================================================================
--- src/vhdl/delayer_e.vhd (nonexistent)
+++ src/vhdl/delayer_e.vhd (revision 7)
@@ -0,0 +1,57 @@
+----------------------------------------------------------------------
+---- ----
+---- delayer_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity delayer is -- delayer
+ generic (
+ delay : integer := 1 -- number of clock cycles to delay
+ );
+ port (
+ clk : in std_logic; -- clock
+ rst : in std_logic; -- negative reset
+ d : in std_logic_vector; -- signal to be delayed by "delay" clock cycles
+ q : out std_logic_vector -- delayed signal
+ );
+end delayer;
Index: src/vhdl/limiter_synth.vhd
===================================================================
--- src/vhdl/limiter_synth.vhd (nonexistent)
+++ src/vhdl/limiter_synth.vhd (revision 7)
@@ -0,0 +1,63 @@
+----------------------------------------------------------------------
+---- ----
+---- limiter_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of limiter is
+begin
+ aLim <= std_logic_vector(conv_signed(-2**(SIG_WIDTH - 1) + 1, SIG_WIDTH)) when conv_integer(unsigned(a)) <= -2**(SIG_WIDTH - 1) else
+ std_logic_vector(conv_signed(2**(SIG_WIDTH - 1) - 1, SIG_WIDTH)) when conv_integer(unsigned(a)) >= 2**(SIG_WIDTH - 1) else
+ a;
+ bLim <= std_logic_vector(conv_signed(-2**(SIG_WIDTH - 1) + 1, SIG_WIDTH)) when conv_integer(unsigned(b)) <= -2**(SIG_WIDTH - 1) else
+ std_logic_vector(conv_signed(2**(SIG_WIDTH - 1) - 1, SIG_WIDTH)) when conv_integer(unsigned(b)) >= 2**(SIG_WIDTH - 1) else
+ b;
+ yLim <= std_logic_vector(conv_signed(-2**(SIG_WIDTH - 1) + 1, SIG_WIDTH)) when conv_integer(unsigned(y)) <= -2**(SIG_WIDTH - 1) else
+ std_logic_vector(conv_signed(2**(SIG_WIDTH - 1) - 1, SIG_WIDTH)) when conv_integer(unsigned(y)) >= 2**(SIG_WIDTH - 1) else
+ y;
+ wLim <= std_logic_vector(conv_signed(-2**(SIG_WIDTH - 1) + 1, SIG_WIDTH)) when conv_integer(unsigned(w)) <= -2**(SIG_WIDTH - 1) else
+ std_logic_vector(conv_signed(2**(SIG_WIDTH - 1) - 1, SIG_WIDTH)) when conv_integer(unsigned(w)) >= 2**(SIG_WIDTH - 1) else
+ w;
+ yIntLim <= std_logic_vector(conv_signed(-2**(SIG_WIDTH - 1) + 1, SIG_WIDTH)) when conv_integer(unsigned(yInt)) <= -2**(SIG_WIDTH - 1) else
+ std_logic_vector(conv_signed(2**(SIG_WIDTH - 1) - 1, SIG_WIDTH)) when conv_integer(unsigned(yInt)) >= 2**(SIG_WIDTH - 1) else
+ yInt;
+ wIntLim <= std_logic_vector(conv_signed(-2**(SIG_WIDTH - 1) + 1, SIG_WIDTH)) when conv_integer(unsigned(wInt)) <= -2**(SIG_WIDTH - 1) else
+ std_logic_vector(conv_signed(2**(SIG_WIDTH - 1) - 1, SIG_WIDTH)) when conv_integer(unsigned(wInt)) >= 2**(SIG_WIDTH - 1) else
+ wInt;
+end;
Index: src/vhdl/acs_synth.vhd
===================================================================
--- src/vhdl/acs_synth.vhd (nonexistent)
+++ src/vhdl/acs_synth.vhd (revision 7)
@@ -0,0 +1,106 @@
+----------------------------------------------------------------------
+---- ----
+---- acs_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of acs is
+ signal distance16 : ARRAY16a;
+ signal accDist8 : ARRAY8a;
+ signal accDist32 : ARRAY32c;
+ signal accDistDel32 : ARRAY32c;
+ signal accDistDel4 : ARRAY4a;
+ signal selAccDistL : std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
+begin
+ distances_i0 : distances port map (
+ a => a,
+ b => b,
+ y => y,
+ w => w,
+ z => z,
+ distance16 => distance16
+ );
+ accDist_i0 : accDist port map (
+ clk => clk,
+ rst => rst,
+ accDistReg => accDist8,
+ dist => distance16,
+ accDistNew => accDist32
+ );
+ delayer_g0 : for i in 0 to 31 generate
+ delayer_i : delayer generic map (
+ delay => TREL1_LEN - 1
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ d => accDist32(FROM2TO(i)),
+ q => accDistDel32(i)
+ );
+ end generate;
+ mux8_i0 : mux8 port map (
+ in8x4 => accDistDel32,
+ sel => selStateL,
+ outSel4 => accDistDel4
+ );
+ mux4_i0 : mux4 port map (
+ in1 => accDistDel4(0),
+ in2 => accDistDel4(1),
+ in3 => accDistDel4(2),
+ in4 => accDistDel4(3),
+ sel => selTransL,
+ outSel => selAccDistL
+ );
+ subs_g : for i in 0 to 3 generate
+ subs_i : subs port map (
+ op1 => accDistDel4(i),
+ op2 => selAccDistL,
+ res => weight(i)
+ );
+ end generate;
+ accDistSel_i0 : accDistSel port map (
+ accDist => accDist32,
+ accDistCod => stateDist,
+ accDistOut => accDist8
+ );
+ stateSel_i0 : stateSel port map (
+ stateDist => accDist8,
+ selState => selState
+ );
+end;
Index: src/vhdl/cod2_e.vhd
===================================================================
--- src/vhdl/cod2_e.vhd (nonexistent)
+++ src/vhdl/cod2_e.vhd (revision 7)
@@ -0,0 +1,53 @@
+----------------------------------------------------------------------
+---- ----
+---- cod2_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cod2 is -- 2-bit coder
+ port (
+ in1 : in std_logic; -- 1-bit first input signal
+ in2 : in std_logic; -- 1-bit second input signal
+ in3 : in std_logic; -- 1-bit third input signal
+ outCod : out std_logic_vector(1 downto 0) -- 2-bit coded value
+ );
+end cod2;
Index: src/vhdl/sova_synth.vhd
===================================================================
--- src/vhdl/sova_synth.vhd (nonexistent)
+++ src/vhdl/sova_synth.vhd (revision 7)
@@ -0,0 +1,148 @@
+----------------------------------------------------------------------
+---- ----
+---- sova_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of sova is
+ signal selStateL2 : std_logic_vector(2 downto 0);
+ signal selStateL1 : std_logic_vector(2 downto 0);
+ signal selState : std_logic_vector(2 downto 0);
+ signal selTransL2 : std_logic_vector(1 downto 0);
+ signal selTrans : ARRAY8b;
+ signal selTransL1 : ARRAY8b;
+ signal weight : ARRAY4a;
+ signal stateL1 : ARRAY4d;
+ signal llr0 : std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
+ signal llr1 : std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
+ signal llr2 : std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
+ signal llr3 : std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
+ signal zinDel : ARRAY4c;
+ signal aNoisyDel : std_logic_vector(SIG_WIDTH - 1 downto 0);
+ signal bNoisyDel : std_logic_vector(SIG_WIDTH - 1 downto 0);
+begin
+ acs_i0 : acs port map (
+ clk => clk,
+ rst => rst,
+ a => aNoisy,
+ b => bNoisy,
+ y => yNoisy,
+ w => wNoisy,
+ z => zin,
+ selStateL => selStateL2,
+ selTransL => selTransL2,
+ selState => selState,
+ stateDist => selTrans,
+ weight => weight
+ );
+ trellis1_i0 : trellis1 port map (
+ clk => clk,
+ rst => rst,
+ selState => selState,
+ selTrans => selTrans,
+ selStateL2 => selStateL2,
+ selStateL1 => selStateL1,
+ stateL1 => stateL1,
+ selTransL2 => selTransL2
+ );
+ trellis2_i0 : trellis2 port map (
+ clk => clk,
+ rst => rst,
+ selState => selStateL1,
+ state => stateL1,
+ selTrans => selTransL1,
+ weight => weight,
+ llr0 => llr0,
+ llr1 => llr1,
+ llr2 => llr2,
+ llr3 => llr3,
+ a => aClean,
+ b => bClean
+ );
+ delayer_g0 : for i in 0 to 7 generate
+ delayer_i : delayer generic map (
+ delay => TREL1_LEN - 1
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ d => selTrans(i),
+ q => selTransL1(i)
+ );
+ end generate;
+ delayer_g1 : for i in 0 to 3 generate
+ delayer_i : delayer generic map (
+ delay => TREL1_LEN + TREL2_LEN
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ d => zin(i),
+ q => zinDel(i)
+ );
+ end generate;
+ delayer_i0 : delayer generic map (
+ delay => TREL1_LEN + TREL2_LEN
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ d => aNoisy,
+ q => aNoisyDel
+ );
+ delayer_i1 : delayer generic map (
+ delay => TREL1_LEN + TREL2_LEN
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ d => bNoisy,
+ q => bNoisyDel
+ );
+ extInf_i0 : extInf port map (
+ llr0 => llr0,
+ llr1 => llr1,
+ llr2 => llr2,
+ llr3 => llr3,
+ zin => zinDel,
+ a => aNoisyDel,
+ b => bNoisyDel,
+ zout => zout
+ );
+end;
Index: src/vhdl/subs_synth.vhd
===================================================================
--- src/vhdl/subs_synth.vhd (nonexistent)
+++ src/vhdl/subs_synth.vhd (revision 7)
@@ -0,0 +1,49 @@
+----------------------------------------------------------------------
+---- ----
+---- subs_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of subs is
+begin
+ process (op1, op2)
+ begin
+ res <= std_logic_vector(conv_unsigned(conv_integer(unsigned(op1)) - conv_integer(unsigned(op2)), res'length));
+ end process;
+end;
Index: src/vhdl/adder_synth.vhd
===================================================================
--- src/vhdl/adder_synth.vhd (nonexistent)
+++ src/vhdl/adder_synth.vhd (revision 7)
@@ -0,0 +1,49 @@
+----------------------------------------------------------------------
+---- ----
+---- adder_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of adder is
+begin
+ process (op1, op2)
+ begin
+ res <= std_logic_vector(conv_unsigned(conv_integer(unsigned(op1)) + conv_integer(unsigned(op2)), res'length));
+ end process;
+end;
Index: src/vhdl/cmp2_e.vhd
===================================================================
--- src/vhdl/cmp2_e.vhd (nonexistent)
+++ src/vhdl/cmp2_e.vhd (revision 7)
@@ -0,0 +1,53 @@
+----------------------------------------------------------------------
+---- ----
+---- cmp2_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity cmp2 is -- 2-input comparator (operand must be positive)
+ port (
+ op1 : in std_logic_vector; -- first operand
+ op2 : in std_logic_vector; -- second operand
+ res : out std_logic -- compare result (0 if op2 < op1, 1 otherwise)
+ );
+end cmp2;
Index: src/vhdl/zPermut_e.vhd
===================================================================
--- src/vhdl/zPermut_e.vhd (nonexistent)
+++ src/vhdl/zPermut_e.vhd (revision 7)
@@ -0,0 +1,56 @@
+----------------------------------------------------------------------
+---- ----
+---- zPermut_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.turbopack.all;
+
+entity zPermut is -- extrinsic information permutation
+ generic (
+ flip : integer := 0 -- initialisation (permutation on/off)
+ );
+ port (
+ flipflop : in std_logic; -- permutation control signal (on/off)
+ z : in ARRAY4c; -- original extrinsic information
+ zPerm : out ARRAY4c -- permuted extrinsic information
+ );
+end zPermut;
Index: src/vhdl/min4_e.vhd
===================================================================
--- src/vhdl/min4_e.vhd (nonexistent)
+++ src/vhdl/min4_e.vhd (revision 7)
@@ -0,0 +1,57 @@
+----------------------------------------------------------------------
+---- ----
+---- min4_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.turbopack.all;
+
+entity min4 is -- selects the minimum between 4 values
+ port (
+ op1 : in std_logic_vector; -- first input signal
+ op2 : in std_logic_vector; -- second input signal
+ op3 : in std_logic_vector; -- third input signal
+ op4 : in std_logic_vector; -- fourth input signal
+ res1 : out std_logic; -- partial code of the minimum value
+ res2 : out std_logic; -- partial code of the minimum value
+ res3 : out std_logic -- partial code of the minimum value
+ );
+end min4;
Index: src/vhdl/min8_e.vhd
===================================================================
--- src/vhdl/min8_e.vhd (nonexistent)
+++ src/vhdl/min8_e.vhd (revision 7)
@@ -0,0 +1,52 @@
+----------------------------------------------------------------------
+---- ----
+---- min8_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.turbopack.all;
+
+entity min8 is -- selects the minimum between 8 values
+ port (
+ op : in ARRAY8a; -- input signals
+ res : out std_logic_vector(6 downto 0) -- code of the minimum value
+ );
+end min8;
Index: src/vhdl/mux2_synth.vhd
===================================================================
--- src/vhdl/mux2_synth.vhd (nonexistent)
+++ src/vhdl/mux2_synth.vhd (revision 7)
@@ -0,0 +1,47 @@
+----------------------------------------------------------------------
+---- ----
+---- mux2_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of mux2 is
+begin
+ outSel <= in2 when sel = '0' else
+ in1;
+end;
Index: src/vhdl/reg_e.vhd
===================================================================
--- src/vhdl/reg_e.vhd (nonexistent)
+++ src/vhdl/reg_e.vhd (revision 7)
@@ -0,0 +1,54 @@
+----------------------------------------------------------------------
+---- ----
+---- reg_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity reg is -- register
+ port (
+ clk : in std_logic; -- clock
+ rst : in std_logic; -- negative reset
+ d : in std_logic_vector; -- next value
+ q : out std_logic_vector -- current value
+ );
+end reg;
Index: src/vhdl/reduction_synth.vhd
===================================================================
--- src/vhdl/reduction_synth.vhd (nonexistent)
+++ src/vhdl/reduction_synth.vhd (revision 7)
@@ -0,0 +1,57 @@
+----------------------------------------------------------------------
+---- ----
+---- reduction_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of reduction is
+begin
+ process (org)
+ variable msb : std_logic;
+ begin
+ msb := '1';
+ for i in 0 to 7 loop
+ msb := msb and org(i)(ACC_DIST_WIDTH - 1);
+ end loop;
+ for i in 0 to 7 loop
+ chd(i)(ACC_DIST_WIDTH - 2 downto 0) <= org(i)(ACC_DIST_WIDTH - 2 downto 0);
+ chd(i)(ACC_DIST_WIDTH - 1) <= (not msb) and org(i)(ACC_DIST_WIDTH - 1);
+ end loop;
+ end process;
+end;
Index: src/vhdl/accDistSel_e.vhd
===================================================================
--- src/vhdl/accDistSel_e.vhd (nonexistent)
+++ src/vhdl/accDistSel_e.vhd (revision 7)
@@ -0,0 +1,53 @@
+----------------------------------------------------------------------
+---- ----
+---- accDistSel_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.turbopack.all;
+
+entity accDistSel is -- accumulated distance selection (one out of four, per state)
+ port (
+ accDist : in ARRAY32c; -- array of 32 accumulated distances
+ accDistCod : out ARRAY8b; -- array of 8 2-bit selection signals
+ accDistOut : out ARRAY8a -- array of 8 selected accumulated distances
+ );
+end accDistSel;
Index: src/vhdl/mux4_synth.vhd
===================================================================
--- src/vhdl/mux4_synth.vhd (nonexistent)
+++ src/vhdl/mux4_synth.vhd (revision 7)
@@ -0,0 +1,57 @@
+----------------------------------------------------------------------
+---- ----
+---- mux4_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of mux4 is
+begin
+ process (in1, in2, in3, in4, sel)
+ begin
+ if sel = "00" then
+ outSel <= in1;
+ elsif sel = "01" then
+ outSel <= in2;
+ elsif sel = "10" then
+ outSel <= in3;
+ else
+ outSel <= in4;
+ end if;
+ end process;
+end;
Index: src/vhdl/iteration_synth.vhd
===================================================================
--- src/vhdl/iteration_synth.vhd (nonexistent)
+++ src/vhdl/iteration_synth.vhd (revision 7)
@@ -0,0 +1,251 @@
+----------------------------------------------------------------------
+---- ----
+---- iteration_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of iteration is
+ signal zout1 : ARRAY4c;
+ signal zout2 : ARRAY4c;
+ signal zout1Perm : ARRAY4c;
+ signal zoutInt1 : ARRAY4c;
+ signal zout2Int : ARRAY4c;
+ signal tmp0 : std_logic_vector(Z_WIDTH * 4 + SIG_WIDTH * 2 - 1 downto 0);
+ signal tmp1 : std_logic_vector(Z_WIDTH * 4 + SIG_WIDTH * 2 - 1 downto 0);
+ signal tmp2 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0);
+ signal tmp3 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0);
+ signal tmp4 : std_logic_vector(SIG_WIDTH * 4 - 1 downto 0);
+ signal tmp5 : std_logic_vector(SIG_WIDTH * 4 - 1 downto 0);
+ signal tmp6 : std_logic_vector(Z_WIDTH * 4 - 1 downto 0);
+ signal tmp7 : std_logic_vector(Z_WIDTH * 4 - 1 downto 0);
+ signal tmp8 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0);
+ signal tmp9 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0);
+ signal tmp10 : std_logic_vector(SIG_WIDTH * 8 - 1 downto 0);
+ signal tmp11 : std_logic_vector(SIG_WIDTH * 8 - 1 downto 0);
+ signal abDel1Perm : ARRAY2a;
+ signal abDel1PermInt: ARRAY2a;
+ signal aDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
+ signal bDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
+ signal yDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
+ signal wDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
+ signal yIntDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
+ signal wIntDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
+ signal aDel2 : std_logic_vector(SIG_WIDTH - 1 downto 0);
+ signal bDel2 : std_logic_vector(SIG_WIDTH - 1 downto 0);
+ signal yDel2 : std_logic_vector(SIG_WIDTH - 1 downto 0);
+ signal wDel2 : std_logic_vector(SIG_WIDTH - 1 downto 0);
+ signal aDecInt : std_logic;
+ signal bDecInt : std_logic;
+ signal aDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
+ signal bDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
+ signal yDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
+ signal wDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
+ signal yIntDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
+ signal wIntDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
+ signal yIntDel4 : std_logic_vector(SIG_WIDTH - 1 downto 0);
+ signal wIntDel4 : std_logic_vector(SIG_WIDTH - 1 downto 0);
+begin
+ sova_i0 : sova port map (
+ clk => clk,
+ rst => rst,
+ aNoisy => a,
+ bNoisy => b,
+ yNoisy => y,
+ wNoisy => w,
+ zin => zin,
+ zout => zout1,
+ aClean => aDec,
+ bClean => bDec
+ );
+ zPermut_i0 : zPermut generic map (
+ flip => (TREL1_LEN + TREL2_LEN + 2 + delay + 1) mod 2
+ )
+ port map (
+ flipflop => flipflop,
+ z => zout1,
+ zPerm => zout1Perm
+ );
+
+ tmp0 <= zout1Perm(0) & zout1Perm(1) & zout1Perm(2) & zout1Perm(3) & abDel1Perm(0) & abDel1Perm(1);
+
+ interleaver_i0 : interleaver generic map (
+ delay => TREL1_LEN + TREL2_LEN + 2 + delay,
+ way => 0
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ d => tmp0,
+ q => tmp1
+ );
+
+ zoutInt1(0) <= tmp1(Z_WIDTH * 4 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 3 + SIG_WIDTH * 2);
+ zoutInt1(1) <= tmp1(Z_WIDTH * 3 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 2 + SIG_WIDTH * 2);
+ zoutInt1(2) <= tmp1(Z_WIDTH * 2 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 1 + SIG_WIDTH * 2);
+ zoutInt1(3) <= tmp1(Z_WIDTH * 1 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 0 + SIG_WIDTH * 2);
+ abDel1PermInt(0) <= tmp1(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
+ abDel1PermInt(1) <= tmp1(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
+
+ tmp2 <= a & b & y & w & yInt & wInt;
+
+ delayer_i0 : delayer generic map (
+ delay => TREL1_LEN + TREL2_LEN
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ d => tmp2,
+ q => tmp3
+ );
+
+ aDel1 <= tmp3(SIG_WIDTH * 6 - 1 downto SIG_WIDTH * 5);
+ bDel1 <= tmp3(SIG_WIDTH * 5 - 1 downto SIG_WIDTH * 4);
+ yDel1 <= tmp3(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3);
+ wDel1 <= tmp3(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2);
+ yIntDel1 <= tmp3(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
+ wIntDel1 <= tmp3(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
+
+ abPermut_i0 : abPermut generic map (
+ flip => (TREL1_LEN + TREL2_LEN + 2 + delay + 1) mod 2
+ )
+ port map (
+ flipflop => flipflop,
+ a => aDel1,
+ b => bDel1,
+ abPerm => abDel1Perm
+ );
+
+ tmp4 <= aDel1 & bDel1 & yDel1 & wDel1;
+
+ delayer_i1 : delayer generic map (
+ delay => FRSIZE
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ d => tmp4,
+ q => tmp5
+ );
+
+ aDel2 <= tmp5(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3);
+ bDel2 <= tmp5(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2);
+ yDel2 <= tmp5(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
+ wDel2 <= tmp5(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
+
+ sova_i1 : sova port map (
+ clk => clk,
+ rst => rst,
+ aNoisy => abDel1PermInt(1),
+ bNoisy => abDel1PermInt(0),
+ yNoisy => yIntDel1,
+ wNoisy => wIntDel1,
+ zin => zoutInt1,
+ zout => zout2,
+ aClean => aDecInt,
+ bClean => bDecInt
+ );
+
+ tmp6 <= zout2(0) & zout2(1) & zout2(2) & zout2(3);
+
+ deinterleaver_i0 : interleaver generic map (
+ delay => 2 * (TREL1_LEN + TREL2_LEN + 2) + FRSIZE + delay,
+ way => 1
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ d => tmp6,
+ q => tmp7
+ );
+
+ zout2Int(0) <= tmp7(Z_WIDTH * 4 - 1 downto Z_WIDTH * 3);
+ zout2Int(1) <= tmp7(Z_WIDTH * 3 - 1 downto Z_WIDTH * 2);
+ zout2Int(2) <= tmp7(Z_WIDTH * 2 - 1 downto Z_WIDTH * 1);
+ zout2Int(3) <= tmp7(Z_WIDTH * 1 - 1 downto Z_WIDTH * 0);
+
+ zPermut_i1 : zPermut generic map (
+ flip => (2 * (TREL1_LEN + TREL2_LEN + 2) + FRSIZE + delay) mod 2
+ )
+ port map (
+ flipflop => flipflop,
+ z => zout2Int,
+ zPerm => zout
+ );
+
+ tmp8 <= aDel2 & bDel2 & yDel2 & wDel2 & yIntDel1 & wIntDel1;
+
+ delayer_i2 : delayer generic map (
+ delay => TREL1_LEN + TREL2_LEN
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ d => tmp8,
+ q => tmp9
+ );
+
+ aDel3 <= tmp9(SIG_WIDTH * 6 - 1 downto SIG_WIDTH * 5);
+ bDel3 <= tmp9(SIG_WIDTH * 5 - 1 downto SIG_WIDTH * 4);
+ yDel3 <= tmp9(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3);
+ wDel3 <= tmp9(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2);
+ yIntDel3 <= tmp9(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
+ wIntDel3 <= tmp9(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
+
+ tmp10 <= aDel3 & bDel3 & yDel3 & wDel3 & yIntDel3 & wIntDel3 & yIntDel4 & wIntDel4;
+
+ delayer_i3 : delayer generic map (
+ delay => FRSIZE
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ d => tmp10,
+ q => tmp11
+ );
+
+ aDel <= tmp11(SIG_WIDTH * 8 - 1 downto SIG_WIDTH * 7);
+ bDel <= tmp11(SIG_WIDTH * 7 - 1 downto SIG_WIDTH * 6);
+ yDel <= tmp11(SIG_WIDTH * 6 - 1 downto SIG_WIDTH * 5);
+ wDel <= tmp11(SIG_WIDTH * 5 - 1 downto SIG_WIDTH * 4);
+ yIntDel4 <= tmp11(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3);
+ wIntDel4 <= tmp11(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2);
+ yIntDel <= tmp11(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
+ wIntDel <= tmp11(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
+
+end;
Index: src/vhdl/trellis2_synth.vhd
===================================================================
--- src/vhdl/trellis2_synth.vhd (nonexistent)
+++ src/vhdl/trellis2_synth.vhd (revision 7)
@@ -0,0 +1,246 @@
+----------------------------------------------------------------------
+---- ----
+---- trellis2_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of trellis2 is
+ signal revWeight : ARRAY_4xTREL2_LEN;
+ signal pathIdReg : ARRAY8d;
+ signal reg : ARRAY_TREL2_LENx8;
+begin
+ process (clk, rst)
+ variable free : std_logic_vector(7 downto 0);
+ variable freeBeg : std_logic_vector(7 downto 0);
+ variable pastState : ARRAY8d;
+ variable pathId : ARRAY8d;
+ variable freePathId : INT3BIT;
+ variable op : ARRAY4a;
+ variable tmp : ARRAY4a;
+ variable revWeightTmp : ARRAY_4xTREL2_LEN;
+ variable revWeightFilt : ARRAY3a;
+ variable notZero : ARRAY6b;
+ variable minTmp : std_logic_vector(0 to 2);
+ variable ind : ARRAY6b;
+ variable tmp4 : std_logic_vector(ACC_DIST_WIDTH downto 0);
+ begin
+ if rst = '0' then
+ for i in 0 to 3 loop
+ for j in 0 to TREL2_LEN - 1 loop
+ revWeight(i * TREL2_LEN + j) <= (others => '0');
+ end loop;
+ end loop;
+ a <= '0';
+ b <= '0';
+ llr0 <= (others => '0');
+ llr1 <= (others => '0');
+ llr2 <= (others => '0');
+ llr3 <= (others => '0');
+ for i in 0 to 7 loop
+ pathIdReg(i) <= i;
+ for j in 0 to TREL2_LEN - 1 loop
+ reg(j * 8 + i) <= "00";
+ end loop;
+ end loop;
+ elsif clk = '1' and clk'event then
+ free := "11111111";
+ for i in 0 to 7 loop
+ pastState(i) := TRANS2STATE(i * 4 + conv_integer(unsigned(selTrans(i))));
+ pathId(i) := pathIdReg(pastState(i));
+ free(pathId(i)) := '0';
+ end loop;
+ freeBeg := "11111111";
+ for i in 0 to 7 loop
+ if freeBeg(pathId(i)) = '1' then
+ reg(0 * 8 + pathId(i)) <= selTrans(i);
+ freeBeg(pathId(i)) := '0';
+ pathIdReg(i) <= pathId(i);
+ for j in 0 to TREL2_LEN - 2 loop
+ reg((j + 1) * 8 + pathId(i)) <= reg(j * 8 + pathId(i));
+ end loop;
+ else
+ if free(0) = '1' then
+ freePathId := 0;
+ end if;
+ if free(1 downto 0) = "10" then
+ freePathId := 1;
+ end if;
+ if free(2 downto 0) = "100" then
+ freePathId := 2;
+ end if;
+ if free(3 downto 0) = "1000" then
+ freePathId := 3;
+ end if;
+ if free(4 downto 0) = "10000" then
+ freePathId := 4;
+ end if;
+ if free(5 downto 0) = "100000" then
+ freePathId := 5;
+ end if;
+ if free(6 downto 0) = "1000000" then
+ freePathId := 6;
+ end if;
+ if free(7 downto 0) = "10000000" then
+ freePathId := 7;
+ end if;
+ reg(0 * 8 + freePathId) <= selTrans(i);
+ free(freePathId) := '0';
+ pathIdReg(i) <= freePathId;
+ for j in 0 to TREL2_LEN - 2 loop
+ reg((j + 1) * 8 + freePathId) <= reg(j * 8 + pathId(i));
+ end loop;
+ end if;
+ end loop;
+ a <= reg((TREL2_LEN - 1) * 8 + pathId(conv_integer(unsigned(selState))))(1);
+ b <= reg((TREL2_LEN - 1) * 8 + pathId(conv_integer(unsigned(selState))))(0);
+ for i in 0 to 3 loop
+ for j in 0 to TREL2_LEN - 2 loop
+ for k in 0 to 3 loop
+ if reg(j * 8 + pathId(conv_integer(unsigned(state(k))))) = std_logic_vector(conv_unsigned(i, 2)) and state(k) /= selState then
+ op(k) := weight(k);
+ else
+ op(k) := std_logic_vector(conv_unsigned((2 ** ACC_DIST_WIDTH) - 1, ACC_DIST_WIDTH));
+ end if;
+ end loop;
+ if conv_integer(unsigned(op(0))) < conv_integer(unsigned(op(1))) then
+ tmp(0) := op(0);
+ else
+ tmp(0) := op(1);
+ end if;
+ if conv_integer(unsigned(op(2))) < conv_integer(unsigned(op(3))) then
+ tmp(1) := op(2);
+ else
+ tmp(1) := op(3);
+ end if;
+ if conv_integer(unsigned(tmp(0))) < conv_integer(unsigned(tmp(1))) then
+ tmp(2) := tmp(0);
+ else
+ tmp(2) := tmp(1);
+ end if;
+ if conv_integer(unsigned(tmp(2))) < conv_integer(unsigned(revWeight(i * TREL2_LEN + j))) then
+ revWeightTmp(i * TREL2_LEN + j + 1) := tmp(2);
+ else
+ revWeightTmp(i * TREL2_LEN + j + 1) := revWeight(i * TREL2_LEN + j);
+ end if;
+ end loop;
+ revWeightTmp(i * TREL2_LEN + 0) := weight(i);
+ end loop;
+ for j in 0 to 1 loop
+ if revWeightTmp(0 * TREL2_LEN + j) = std_logic_vector(conv_unsigned(0, ACC_DIST_WIDTH)) then
+ notZero(j * 3 + 0) := 1;
+ notZero(j * 3 + 1) := 2;
+ notZero(j * 3 + 2) := 3;
+ elsif revWeightTmp(1 * TREL2_LEN + j) = std_logic_vector(conv_unsigned(0, ACC_DIST_WIDTH)) then
+ notZero(j * 3 + 0) := 0;
+ notZero(j * 3 + 1) := 2;
+ notZero(j * 3 + 2) := 3;
+ elsif revWeightTmp(2 * TREL2_LEN + j) = std_logic_vector(conv_unsigned(0, ACC_DIST_WIDTH)) then
+ notZero(j * 3 + 0) := 0;
+ notZero(j * 3 + 1) := 1;
+ notZero(j * 3 + 2) := 3;
+ elsif revWeightTmp(3 * TREL2_LEN + j) = std_logic_vector(conv_unsigned(0, ACC_DIST_WIDTH)) then
+ notZero(j * 3 + 0) := 0;
+ notZero(j * 3 + 1) := 1;
+ notZero(j * 3 + 2) := 2;
+ end if;
+ if conv_integer(unsigned(revWeightTmp(notZero(j * 3 + 0) * TREL2_LEN + j))) <= conv_integer(unsigned(revWeightTmp(notZero(j * 3 + 1) * TREL2_LEN + j))) then
+ minTmp(0) := '0';
+ else
+ minTmp(0) := '1';
+ end if;
+ if conv_integer(unsigned(revWeightTmp(notZero(j * 3 + 0) * TREL2_LEN + j))) <= conv_integer(unsigned(revWeightTmp(notZero(j * 3 + 2) * TREL2_LEN + j))) then
+ minTmp(1) := '0';
+ else
+ minTmp(1) := '1';
+ end if;
+ if conv_integer(unsigned(revWeightTmp(notZero(j * 3 + 1) * TREL2_LEN + j))) <= conv_integer(unsigned(revWeightTmp(notZero(j * 3 + 2) * TREL2_LEN + j))) then
+ minTmp(2) := '0';
+ else
+ minTmp(2) := '1';
+ end if;
+ if minTmp = "000" then
+ ind(j * 3 + 0) := 0;
+ ind(j * 3 + 1) := 1;
+ ind(j * 3 + 2) := 2;
+ elsif minTmp = "001" then
+ ind(j * 3 + 0) := 0;
+ ind(j * 3 + 1) := 2;
+ ind(j * 3 + 2) := 1;
+ elsif minTmp = "100" then
+ ind(j * 3 + 0) := 1;
+ ind(j * 3 + 1) := 0;
+ ind(j * 3 + 2) := 2;
+ elsif minTmp = "011" then
+ ind(j * 3 + 0) := 1;
+ ind(j * 3 + 1) := 2;
+ ind(j * 3 + 2) := 0;
+ elsif minTmp = "110" then
+ ind(j * 3 + 0) := 2;
+ ind(j * 3 + 1) := 0;
+ ind(j * 3 + 2) := 1;
+ else -- if minTmp = "111" then
+ ind(j * 3 + 0) := 2;
+ ind(j * 3 + 1) := 1;
+ ind(j * 3 + 2) := 0;
+ end if;
+ end loop;
+ for i in 0 to 2 loop
+ tmp(3) := revWeightTmp(notZero(0 * 3 + ind(0 * 3 + i)) * TREL2_LEN + 0);
+ tmp4 := std_logic_vector(conv_unsigned(conv_integer(unsigned(revWeightTmp(notZero(1 * 3 + ind(1 * 3 + i)) * TREL2_LEN + 1))) + (2 ** (ACC_DIST_WIDTH - 4)), ACC_DIST_WIDTH + 1));
+ if conv_integer(unsigned(tmp(3))) < conv_integer(unsigned(tmp4)) then
+ revWeightFilt(ind(0 * 3 + i)) := tmp(3);
+ else
+ revWeightFilt(ind(0 * 3 + i)) := tmp4(ACC_DIST_WIDTH - 1 downto 0);
+ end if;
+ end loop;
+ for i in 0 to 2 loop
+ revWeightTmp(notZero(0 * 3 + i) * TREL2_LEN + 0) := revWeightFilt(i);
+ end loop;
+ for i in 0 to 3 loop
+ for j in 0 to TREL2_LEN - 1 loop
+ revWeight(TREL2_LEN * i + j) <= revWeightTmp(TREL2_LEN * i + j);
+ end loop;
+ end loop;
+ llr0 <= revWeight(1 * TREL2_LEN - 1);
+ llr1 <= revWeight(2 * TREL2_LEN - 1);
+ llr2 <= revWeight(3 * TREL2_LEN - 1);
+ llr3 <= revWeight(4 * TREL2_LEN - 1);
+ end if;
+ end process;
+end;
Index: src/vhdl/mux8_synth.vhd
===================================================================
--- src/vhdl/mux8_synth.vhd (nonexistent)
+++ src/vhdl/mux8_synth.vhd (revision 7)
@@ -0,0 +1,81 @@
+----------------------------------------------------------------------
+---- ----
+---- mux8_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of mux8 is
+begin
+ process (in8x4, sel)
+ begin
+ if sel = "000" then
+ for i in 0 to 3 loop
+ outSel4(i) <= in8x4(i);
+ end loop;
+ elsif sel = "001" then
+ for i in 0 to 3 loop
+ outSel4(i) <= in8x4(i + 4);
+ end loop;
+ elsif sel = "010" then
+ for i in 0 to 3 loop
+ outSel4(i) <= in8x4(i + 8);
+ end loop;
+ elsif sel = "011" then
+ for i in 0 to 3 loop
+ outSel4(i) <= in8x4(i + 12);
+ end loop;
+ elsif sel = "100" then
+ for i in 0 to 3 loop
+ outSel4(i) <= in8x4(i + 16);
+ end loop;
+ elsif sel = "101" then
+ for i in 0 to 3 loop
+ outSel4(i) <= in8x4(i + 20);
+ end loop;
+ elsif sel = "110" then
+ for i in 0 to 3 loop
+ outSel4(i) <= in8x4(i + 24);
+ end loop;
+ else
+ for i in 0 to 3 loop
+ outSel4(i) <= in8x4(i + 28);
+ end loop;
+ end if;
+ end process;
+end;
Index: src/vhdl/opposite_synth.vhd
===================================================================
--- src/vhdl/opposite_synth.vhd (nonexistent)
+++ src/vhdl/opposite_synth.vhd (revision 7)
@@ -0,0 +1,46 @@
+----------------------------------------------------------------------
+---- ----
+---- opposite_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of opposite is
+begin
+ neg <= std_logic_vector(conv_signed(-conv_integer(signed(pos)), SIG_WIDTH + 2));
+end;
Index: src/vhdl/turbopack.vhd
===================================================================
--- src/vhdl/turbopack.vhd (nonexistent)
+++ src/vhdl/turbopack.vhd (revision 7)
@@ -0,0 +1,443 @@
+----------------------------------------------------------------------
+---- ----
+---- turbopack.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package turbopack is
+ constant RATE : integer := 12; -- code rate (e.g. 13 for rate 1/3)
+ constant IT : integer := 5; -- number of decoding iterations
+ constant FRSIZE : integer := 64; -- interleaver frame size in bit couples
+ constant TREL1_LEN : integer := 24; -- first trellis length
+ constant TREL2_LEN : integer := 12; -- second trellis length
+ constant SIG_WIDTH : integer := 4; -- received decoder signal width
+ constant Z_WIDTH : integer := 5; -- extrinsic information width
+ constant ACC_DIST_WIDTH : integer := 9; -- accumulated distance width
+ subtype INT2BIT is integer range 0 to 3;
+ subtype INT3BIT is integer range 0 to 7;
+ subtype SUBINT0 is integer range -(2**(SIG_WIDTH-1)) - (2**Z_WIDTH) to 2**ACC_DIST_WIDTH + 2**(SIG_WIDTH-1) - 1;
+ subtype SUBINT1 is integer range 0 to 2**ACC_DIST_WIDTH + 2**(SIG_WIDTH-1) + 2**(SIG_WIDTH-1) + 2**Z_WIDTH - 1;
+ type ARRAY32a is array (0 to 31) of integer;
+ type ARRAY32b is array (0 to 31) of std_logic_vector(ACC_DIST_WIDTH downto 0);
+ type ARRAY32c is array (0 to 31) of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
+ constant FROM2TO : ARRAY32a := (0, 25, 6, 31, 8, 17, 14, 23, 20, 13, 18, 11, 28, 5, 26, 3, 4, 29, 2, 27, 12, 21, 10, 19, 16, 9, 22, 15, 24, 1, 30, 7);
+ constant DISTINDEX : ARRAY32a := (0, 7, 11, 12, 0, 7, 11, 12, 2, 5, 9, 14, 2, 5, 9, 14, 3, 4, 8, 15, 3, 4, 8, 15, 1, 6, 10, 13, 1, 6, 10, 13);
+ constant TRANS2STATE : ARRAY32a := (0, 6, 1, 7, 2, 4, 3, 5, 5, 3, 4, 2, 7, 1, 6, 0, 1, 7, 0, 6, 3, 5, 2, 4, 4, 2, 5, 3, 6, 0, 7, 1);
+ constant STATE2TRANS : ARRAY32a := (0, 2, 1, 3, 1, 3, 0, 2, 2, 0, 3, 1, 3, 1, 2, 0, 2, 0, 3, 1, 3, 1, 2, 0, 0, 2, 1, 3, 1, 3, 0, 2);
+ type ARRAY2a is array (0 to 1) of std_logic_vector(SIG_WIDTH - 1 downto 0);
+ type ARRAY3a is array (0 to 2) of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
+ type ARRAY4a is array (0 to 3) of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
+ type ARRAY4b is array (0 to 3) of std_logic_vector(ACC_DIST_WIDTH downto 0);
+ type ARRAY4c is array (0 to 3) of std_logic_vector(Z_WIDTH - 1 downto 0);
+ type ARRAY4d is array (0 to 3) of std_logic_vector(2 downto 0);
+ type ARRAY4e is array (0 to 3) of SUBINT1;
+ type ARRAY6a is array (0 to 5) of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
+ type ARRAY6b is array (0 to 5) of INT2BIT;
+ type ARRAY7a is array (0 to 6) of SUBINT0;
+ type ARRAY8a is array (0 to 7) of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
+ type ARRAY8b is array (0 to 7) of std_logic_vector(1 downto 0);
+ type ARRAY8d is array (0 to 7) of INT3BIT;
+ type ARRAY16a is array (0 to 15) of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
+ type ARRAY16b is array (0 to 15) of std_logic_vector(SIG_WIDTH + 1 downto 0);
+ type ARRAY_TREL1_LENx8 is array (0 to TREL1_LEN * 8 - 1) of INT2BIT;
+ type ARRAY_TREL2_LENx8 is array (0 to TREL2_LEN * 8 - 1) of std_logic_vector(1 downto 0);
+ type ARRAY_4xTREL2_LEN is array (0 to 4 * TREL2_LEN - 1) of std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
+ type ARRAY_ITa is array (0 to IT) of std_logic_vector(SIG_WIDTH - 1 downto 0);
+ type ARRAY_ITb is array (0 to IT) of ARRAY4c;
+
+ component delayer
+ generic (
+ delay : integer := 1 -- number of clock cycles to delay
+ );
+ port (
+ clk : in std_logic; -- clock
+ rst : in std_logic; -- negative reset
+ d : in std_logic_vector; -- signal to be delayed by "delay" clock cycles
+ q : out std_logic_vector -- delayed signal
+ );
+ end component;
+
+ component subs
+ port (
+ op1 : in std_logic_vector; -- first operand
+ op2 : in std_logic_vector; -- second operand
+ res : out std_logic_vector -- result of the substraction
+ );
+ end component;
+
+ component mux4
+ port (
+ in1 : in std_logic_vector; -- first input signal
+ in2 : in std_logic_vector; -- second input signal
+ in3 : in std_logic_vector; -- third input signal
+ in4 : in std_logic_vector; -- fourth input signal
+ sel : in std_logic_vector(1 downto 0); -- 2-bit control signal
+ outSel : out std_logic_vector -- selected output signal
+ );
+ end component;
+
+ component mux8
+ port (
+ in8x4 : in ARRAY32c; -- 8x4 input signals
+ sel : in std_logic_vector(2 downto 0); -- 3-bit control signal
+ outSel4 : out ARRAY4a -- selected output signals
+ );
+ end component;
+
+ component distances
+ port (
+ a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ y : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ w : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ z : in ARRAY4c; -- extrinsic information array
+ distance16 : out ARRAY16a -- distance signals (x16)
+ );
+ end component;
+
+ component partDistance
+ generic (
+ ref : integer := 0 -- reference to compute the distance from
+ );
+ port (
+ a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ y : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ w : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ res : out std_logic_vector(SIG_WIDTH + 1 downto 0) -- partial distance signal
+ );
+ end component;
+
+ component opposite
+ port (
+ pos : in std_logic_vector(SIG_WIDTH + 1 downto 0); -- original number
+ neg : out std_logic_vector(SIG_WIDTH + 1 downto 0) -- opposite number
+ );
+ end component;
+
+ component distance
+ port (
+ partDist : in std_logic_vector(SIG_WIDTH + 1 downto 0); -- sum of the decoder input signals
+ z : in std_logic_vector(Z_WIDTH - 1 downto 0); -- extrinsic information
+ dist : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0) -- distance
+ );
+ end component;
+
+ component reg
+ port (
+ clk : in std_logic; -- clock
+ rst : in std_logic; -- negative reset
+ d : in std_logic_vector; -- next value
+ q : out std_logic_vector -- current value
+ );
+ end component;
+
+ component adder
+ port (
+ op1 : in std_logic_vector; -- first operand
+ op2 : in std_logic_vector; -- second operand
+ res : out std_logic_vector -- result of the addition
+ );
+ end component;
+
+ component reduction
+ port (
+ org : in ARRAY8a; -- original array of 8 accumulated distances
+ chd : out ARRAY8a -- reduced array of 8 accumulated distances
+ );
+ end component;
+
+ component accDist
+ port (
+ clk : in std_logic; -- clock
+ rst : in std_logic; -- negative reset
+ accDistReg : in ARRAY8a; -- original array of 8 accumulated distance registers
+ dist : in ARRAY16a; -- array of 16 distances
+ accDistNew : out ARRAY32c -- array of 32 accumulated distances
+ );
+ end component;
+
+ component cmp2
+ port (
+ op1 : in std_logic_vector; -- first operand
+ op2 : in std_logic_vector; -- second operand
+ res : out std_logic -- compare result (0 if op2 < op1, 1 otherwise)
+ );
+ end component;
+
+ component mux2
+ port (
+ in1 : in std_logic_vector; -- first input signal
+ in2 : in std_logic_vector; -- second input signal
+ sel : in std_logic; -- 1-bit control signal
+ outSel : out std_logic_vector -- selected output signal
+ );
+ end component;
+
+ component min4
+ port (
+ op1 : in std_logic_vector; -- first input signal
+ op2 : in std_logic_vector; -- second input signal
+ op3 : in std_logic_vector; -- third input signal
+ op4 : in std_logic_vector; -- fourth input signal
+ res1 : out std_logic; -- partial code of the minimum value
+ res2 : out std_logic; -- partial code of the minimum value
+ res3 : out std_logic -- partial code of the minimum value
+ );
+ end component;
+
+ component accDistSel
+ port (
+ accDist : in ARRAY32c; -- array of 32 accumulated distances
+ accDistCod : out ARRAY8b; -- array of 8 2-bit selection signals
+ accDistOut : out ARRAY8a -- array of 8 selected accumulated distances
+ );
+ end component;
+
+ component cod2
+ port (
+ in1 : in std_logic; -- 1-bit first input signal
+ in2 : in std_logic; -- 1-bit second input signal
+ in3 : in std_logic; -- 1-bit third input signal
+ outCod : out std_logic_vector(1 downto 0) -- 2-bit coded value
+ );
+ end component;
+
+ component min8
+ port (
+ op : in ARRAY8a; -- input signals
+ res : out std_logic_vector(6 downto 0) -- code of the minimum value
+ );
+ end component;
+
+ component cod3
+ port (
+ inSig : in std_logic_vector(6 downto 0); -- 7 1-bit input signals
+ outCod : out std_logic_vector(2 downto 0) -- 3-bit coded value
+ );
+ end component;
+
+ component stateSel
+ port (
+ stateDist : in ARRAY8a; -- state accumulated distance
+ selState : out std_logic_vector(2 downto 0) -- selected state code
+ );
+ end component;
+
+ component acs
+ port (
+ clk : in std_logic; -- clock
+ rst : in std_logic; -- negative reset
+ a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ y : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ w : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ z : in ARRAY4c; -- extrinsic information array
+ selStateL : in std_logic_vector(2 downto 0); -- selected state at t = L
+ selTransL : in std_logic_vector(1 downto 0); -- selected transition at selStateL
+ selState : out std_logic_vector(2 downto 0); -- selected state
+ stateDist : out ARRAY8b; -- selected accumulated distances (per state)
+ weight : out ARRAY4a -- four weights sorted by transition code
+ );
+ end component;
+
+ component trellis1
+ port (
+ clk : in std_logic; -- clock
+ rst : in std_logic; -- negative reset
+ selState : in std_logic_vector(2 downto 0); -- selected state at time 0
+ selTrans : in ARRAY8b; -- 8 selected transitions (1 per state) at time 0
+ selStateL2 : out std_logic_vector(2 downto 0); -- selected state at time (l - 2)
+ selStateL1 : out std_logic_vector(2 downto 0); -- selected state at time (l - 1)
+ stateL1 : out ARRAY4d; -- 4 possible states at time (l - 1)
+ selTransL2 : out std_logic_vector(1 downto 0) -- selected transition at time (l - 2)
+ );
+ end component;
+
+ component trellis2
+ port (
+ clk : in std_logic; -- clock
+ rst : in std_logic; -- negative reset
+ selState : in std_logic_vector(2 downto 0); -- selected state at time (l - 1)
+ state : in ARRAY4d; -- 4 possible states at time (l - 1)
+ selTrans : in ARRAY8b; -- 8 selected transitions (1 per state) at time (l - 1)
+ weight : in ARRAY4a; -- four weights sorted by transition code at time (l - 1)
+ llr0 : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (0, 0) at time (l + m - 1)
+ llr1 : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (0, 1) at time (l + m - 1)
+ llr2 : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (1, 0) at time (l + m - 1)
+ llr3 : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (1, 1) at time (l + m - 1)
+ a : out std_logic; -- decoded value of a at time (l + m - 1)
+ b : out std_logic -- decoded value of b at time (l + m - 1)
+ );
+ end component;
+
+ component extInf
+ port (
+ llr0 : in std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (0, 0)
+ llr1 : in std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (0, 1)
+ llr2 : in std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (1, 0)
+ llr3 : in std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (1, 1)
+ zin : in ARRAY4c; -- extrinsic information input signal
+ a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder systematic input signal
+ b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder systematic input signal
+ zout : out ARRAY4c -- extrinsic information output signal
+ );
+ end component;
+
+ component sova
+ port (
+ clk : in std_logic; -- clock
+ rst : in std_logic; -- negative reset
+ aNoisy : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ bNoisy : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ yNoisy : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ wNoisy : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ zin : in ARRAY4c; -- extrinsic information input
+ zout : out ARRAY4c; -- extrinsic information output
+ aClean : out std_logic; -- decoded systematic data
+ bClean : out std_logic -- decoded systematic data
+ );
+ end component;
+
+ component zPermut
+ generic (
+ flip : integer := 0 -- initialisation (permutation on/off)
+ );
+ port (
+ flipflop : in std_logic; -- permutation control signal (on/off)
+ z : in ARRAY4c; -- original extrinsic information
+ zPerm : out ARRAY4c -- permuted extrinsic information
+ );
+ end component;
+
+ component interleaver
+ generic (
+ delay : integer := 0; -- number of clock cycles to wait before starting the (de)interleaver
+ way : integer := 0 -- 0 for interleaving, 1 for deinterleaving
+ );
+ port (
+ clk : in std_logic; -- clock
+ rst : in std_logic; -- negative reset
+ d : in std_logic_vector; -- input data
+ q : out std_logic_vector -- interleaved data
+ );
+ end component;
+
+ component abPermut
+ generic (
+ flip : integer := 0 -- initialisation (permutation on/off)
+ );
+ port (
+ flipflop : in std_logic; -- permutation control signal (on/off)
+ a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- origiral systematic information
+ b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- origiral systematic information
+ abPerm : out ARRAY2a -- permuted systematic information
+ );
+ end component;
+
+ component iteration
+ generic (
+ delay : integer := 0 -- additional delay created by the previous iterations
+ );
+ port (
+ clk : in std_logic; -- clock
+ rst : in std_logic; -- negative reset
+ flipflop : in std_logic; -- permutation control signal (on/off)
+ a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ y : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ w : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ yInt : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ wInt : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ zin : in ARRAY4c; -- extrinsic information from the previous iteration
+ zout : out ARRAY4c; -- extrinsic information to the next iteration
+ aDec : out std_logic; -- decoded signal
+ bDec : out std_logic; -- decoded signal
+ aDel : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal
+ bDel : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal
+ yDel : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal
+ wDel : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal
+ yIntDel : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal
+ wIntDel : out std_logic_vector(SIG_WIDTH - 1 downto 0) -- delayed received decoder signal
+ );
+ end component;
+
+ component clkDiv
+ port (
+ clk : in std_logic; -- clock
+ rst : in std_logic; -- negative reset
+ clkout : out std_logic -- clock which frequency is half of the input clock
+ );
+ end component;
+
+ component limiter
+ port (
+ a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
+ b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
+ y : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
+ w : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
+ yInt : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
+ wInt : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
+ aLim : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal
+ bLim : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal
+ yLim : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal
+ wLim : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal
+ yIntLim : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal
+ wIntLim : out std_logic_vector(SIG_WIDTH - 1 downto 0) -- limited signal
+ );
+ end component;
+
+ component punct
+ port (
+ clk : in std_logic; -- clock
+ rst : in std_logic; -- negative reset
+ y : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- original data
+ w : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- original data
+ yInt : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- original data
+ wInt : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- original data
+ yPunct : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- punctured data
+ wPunct : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- punctured data
+ yIntPunct : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- punctured data
+ wIntPunct : out std_logic_vector(SIG_WIDTH - 1 downto 0) -- punctured data
+ );
+ end component;
+end;
Index: src/vhdl/punct_e.vhd
===================================================================
--- src/vhdl/punct_e.vhd (nonexistent)
+++ src/vhdl/punct_e.vhd (revision 7)
@@ -0,0 +1,60 @@
+----------------------------------------------------------------------
+---- ----
+---- punct_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.turbopack.all;
+
+entity punct is
+ port (
+ clk : in std_logic; -- clock
+ rst : in std_logic; -- negative reset
+ y : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- original data
+ w : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- original data
+ yInt : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- original data
+ wInt : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- original data
+ yPunct : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- punctured data
+ wPunct : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- punctured data
+ yIntPunct : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- punctured data
+ wIntPunct : out std_logic_vector(SIG_WIDTH - 1 downto 0) -- punctured data
+ );
+end punct;
Index: src/vhdl/distance_e.vhd
===================================================================
--- src/vhdl/distance_e.vhd (nonexistent)
+++ src/vhdl/distance_e.vhd (revision 7)
@@ -0,0 +1,54 @@
+----------------------------------------------------------------------
+---- ----
+---- distance_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use work.turbopack.all;
+
+entity distance is -- distance computation
+ port (
+ partDist : in std_logic_vector(SIG_WIDTH + 1 downto 0); -- sum of the decoder input signals
+ z : in std_logic_vector(Z_WIDTH - 1 downto 0); -- extrinsic information
+ dist : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0) -- distance
+ );
+end distance;
Index: src/vhdl/accDist_synth.vhd
===================================================================
--- src/vhdl/accDist_synth.vhd (nonexistent)
+++ src/vhdl/accDist_synth.vhd (revision 7)
@@ -0,0 +1,66 @@
+----------------------------------------------------------------------
+---- ----
+---- accDist_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of accDist is
+ signal accDistOld : ARRAY8a;
+ signal accDistRed : ARRAY8a;
+begin
+ adder_g : for i in 0 to 31 generate
+ adder_i : adder port map (
+ op1 => accDistOld(i / 4),
+ op2 => dist(DISTINDEX(i)),
+ res => accDistNew(i)
+ );
+ end generate;
+ reduction_i0 : reduction port map (
+ org => accDistReg,
+ chd => accDistRed
+ );
+ reg_g : for i in 0 to 7 generate
+ reg_i : reg port map (
+ clk => clk,
+ rst => rst,
+ d => accDistRed(i),
+ q => accDistOld(i)
+ );
+ end generate;
+end;
Index: src/vhdl/clkDiv_synth.vhd
===================================================================
--- src/vhdl/clkDiv_synth.vhd (nonexistent)
+++ src/vhdl/clkDiv_synth.vhd (revision 7)
@@ -0,0 +1,55 @@
+----------------------------------------------------------------------
+---- ----
+---- clkDiv_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of clkDiv is
+ signal clkout_s : std_logic;
+begin
+ clkout <= clkout_s;
+ process(clk, rst)
+ begin
+ if rst = '0' then
+ clkout_s <= '0';
+ elsif clk = '1' and clk'event then
+ clkout_s <= not clkout_s;
+ end if;
+ end process;
+end;
Index: src/vhdl/trellis1_e.vhd
===================================================================
--- src/vhdl/trellis1_e.vhd (nonexistent)
+++ src/vhdl/trellis1_e.vhd (revision 7)
@@ -0,0 +1,59 @@
+----------------------------------------------------------------------
+---- ----
+---- trellis1_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use work.turbopack.all;
+
+entity trellis1 is -- first trellis
+ port (
+ clk : in std_logic; -- clock
+ rst : in std_logic; -- negative reset
+ selState : in std_logic_vector(2 downto 0); -- selected state at time 0
+ selTrans : in ARRAY8b; -- 8 selected transitions (1 per state) at time 0
+ selStateL2 : out std_logic_vector(2 downto 0); -- selected state at time (l - 2)
+ selStateL1 : out std_logic_vector(2 downto 0); -- selected state at time (l - 1)
+ stateL1 : out ARRAY4d; -- 4 possible states at time (l - 1)
+ selTransL2 : out std_logic_vector(1 downto 0) -- selected transition at time (l - 2)
+ );
+end trellis1;
Index: src/vhdl/abPermut_synth.vhd
===================================================================
--- src/vhdl/abPermut_synth.vhd (nonexistent)
+++ src/vhdl/abPermut_synth.vhd (revision 7)
@@ -0,0 +1,69 @@
+----------------------------------------------------------------------
+---- ----
+---- abPermut_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of abPermut is
+begin
+ flipflop_g0 : if flip = 0 generate
+ process (flipflop, a, b)
+ begin
+ if flipflop = '0' then
+ abPerm(1) <= a;
+ abPerm(0) <= b;
+ else
+ abPerm(1) <= b;
+ abPerm(0) <= a;
+ end if;
+ end process;
+ end generate;
+ flipflop_g1 : if flip = 1 generate
+ process (flipflop, a, b)
+ begin
+ if flipflop = '1' then
+ abPerm(1) <= a;
+ abPerm(0) <= b;
+ else
+ abPerm(1) <= b;
+ abPerm(0) <= a;
+ end if;
+ end process;
+ end generate;
+end;
Index: src/vhdl/interleaver_synth.vhd
===================================================================
--- src/vhdl/interleaver_synth.vhd (nonexistent)
+++ src/vhdl/interleaver_synth.vhd (revision 7)
@@ -0,0 +1,204 @@
+----------------------------------------------------------------------
+---- ----
+---- interleaver_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of interleaver is
+ type ARRAYfrSize is array (0 to FRSIZE - 1) of std_logic_vector(d'length - 1 downto 0);
+ subtype cnt_t is integer range 0 to delay;
+ subtype p_t is integer range 0 to 652;
+ subtype frSize_t is integer range 0 to FRSIZE - 1;
+ subtype frSize2_t is integer range 0 to 2 * FRSIZE - 1;
+ signal array1 : ARRAYfrSize;
+ signal array2 : ARRAYfrSize;
+ signal cnt : cnt_t;
+ signal i : frSize_t;
+ signal iTmp : frSize_t;
+ signal j : frSize_t;
+ signal full : std_logic;
+ signal p0 : p_t;
+ signal p1 : p_t;
+ signal p2 : p_t;
+ signal p3 : p_t;
+begin
+ frSize48_g : if FRSIZE = 48 generate
+ p0 <= 11;
+ p1 <= 24;
+ p2 <= 0;
+ p3 <= 24;
+ end generate;
+ frSize64_g : if FRSIZE = 64 generate
+ p0 <= 7;
+ p1 <= 34;
+ p2 <= 32;
+ p3 <= 2;
+ end generate;
+ frSize212_g : if FRSIZE = 212 generate
+ p0 <= 13;
+ p1 <= 106;
+ p2 <= 108;
+ p3 <= 2;
+ end generate;
+ frSize220_g : if FRSIZE = 220 generate
+ p0 <= 23;
+ p1 <= 112;
+ p2 <= 4;
+ p3 <= 116;
+ end generate;
+ frSize228_g : if FRSIZE = 228 generate
+ p0 <= 17;
+ p1 <= 116;
+ p2 <= 72;
+ p3 <= 188;
+ end generate;
+ frSize424_g : if FRSIZE = 424 generate
+ p0 <= 11;
+ p1 <= 6;
+ p2 <= 8;
+ p3 <= 2;
+ end generate;
+ frSize432_g : if FRSIZE = 432 generate
+ p0 <= 13;
+ p1 <= 0;
+ p2 <= 4;
+ p3 <= 8;
+ end generate;
+ frSize440_g : if FRSIZE = 440 generate
+ p0 <= 13;
+ p1 <= 10;
+ p2 <= 4;
+ p3 <= 2;
+ end generate;
+ frSize848_g : if FRSIZE = 848 generate
+ p0 <= 19;
+ p1 <= 2;
+ p2 <= 16;
+ p3 <= 6;
+ end generate;
+ frSize856_g : if FRSIZE = 856 generate
+ p0 <= 19;
+ p1 <= 428;
+ p2 <= 224;
+ p3 <= 652;
+ end generate;
+ frSize864_g : if FRSIZE = 864 generate
+ p0 <= 19;
+ p1 <= 2;
+ p2 <= 16;
+ p3 <= 6;
+ end generate;
+ frSize752_g : if FRSIZE = 752 generate
+ p0 <= 19;
+ p1 <= 376;
+ p2 <= 224;
+ p3 <= 600;
+ end generate;
+
+ process (clk, rst)
+ variable p : frSize2_t;
+ variable iTmp1 : frSize2_t;
+ variable iTmp2 : frSize2_t;
+ variable iTmp3 : frSize2_t;
+ variable ii : frSize_t;
+ variable jj : frSize_t;
+ begin
+ if rst = '0' then
+ cnt <= 0;
+ i <= 0;
+ j <= 0;
+ iTmp <= 0;
+ full <= '0';
+ q <= std_logic_vector(conv_unsigned(0, q'length));
+ for k in 0 to FRSIZE - 1 loop
+ array1(k) <= (others => '0');
+ array2(k) <= (others => '0');
+ end loop;
+ elsif clk = '1' and clk'event then
+ if cnt < delay then
+ cnt <= cnt + 1;
+ else
+ if j mod 4 = 0 then
+ p := 0;
+ elsif j mod 4 = 1 then
+ p := FRSIZE / 2 + p1;
+ elsif j mod 4 = 2 then
+ p := p2;
+ else -- if j mod 4 = 3 then
+ p := FRSIZE / 2 + p3;
+ end if;
+ iTmp1 := iTmp + p0;
+ if iTmp1 >= FRSIZE then
+ iTmp2 := iTmp1 - FRSIZE;
+ else
+ iTmp2 := iTmp1;
+ end if;
+ iTmp <= iTmp2;
+ iTmp3 := iTmp2 + p + 1;
+ if iTmp3 >= 2 * FRSIZE then
+ i <= iTmp3 - 2 * FRSIZE;
+ elsif iTmp3 >= FRSIZE then
+ i <= iTmp3 - FRSIZE;
+ else
+ i <= iTmp3;
+ end if;
+ if j = (FRSIZE - 1) then
+ j <= 0;
+ full <= not full;
+ else
+ j <= j + 1;
+ end if;
+ if way = 0 then
+ ii := i;
+ jj := j;
+ else
+ ii := j;
+ jj := i;
+ end if;
+ if full = '0' then
+ array1(jj) <= d;
+ q <= array2(ii);
+ else
+ array2(jj) <= d;
+ q <= array1(ii);
+ end if;
+ end if;
+ end if;
+ end process;
+end;
Index: src/vhdl/partDistance_synth.vhd
===================================================================
--- src/vhdl/partDistance_synth.vhd (nonexistent)
+++ src/vhdl/partDistance_synth.vhd (revision 7)
@@ -0,0 +1,67 @@
+----------------------------------------------------------------------
+---- ----
+---- partDistance_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of partDistance is
+ signal bSigned : std_logic_vector(SIG_WIDTH - 1 downto 0);
+ signal ySigned : std_logic_vector(SIG_WIDTH - 1 downto 0);
+ signal wSigned : std_logic_vector(SIG_WIDTH - 1 downto 0);
+begin
+ bPos_g : if std_logic_vector(conv_unsigned(ref, 3))(2) = '0' generate
+ bSigned <= b;
+ end generate;
+ bNeg_g : if std_logic_vector(conv_unsigned(ref, 3))(2) = '1' generate
+ bSigned <= std_logic_vector(conv_signed(-conv_integer(signed(b)), SIG_WIDTH));
+ end generate;
+ yPos_g : if std_logic_vector(conv_unsigned(ref, 3))(1) = '0' generate
+ ySigned <= y;
+ end generate;
+ yNeg_g : if std_logic_vector(conv_unsigned(ref, 3))(1) = '1' generate
+ ySigned <= std_logic_vector(conv_signed(-conv_integer(signed(y)), SIG_WIDTH));
+ end generate;
+ wPos_g : if std_logic_vector(conv_unsigned(ref, 3))(0) = '0' generate
+ wSigned <= w;
+ end generate;
+ wNeg_g : if std_logic_vector(conv_unsigned(ref, 3))(0) = '1' generate
+ wSigned <= std_logic_vector(conv_signed(-conv_integer(signed(w)), SIG_WIDTH));
+ end generate;
+ res <= std_logic_vector(conv_signed(conv_integer(signed(a)) + conv_integer(signed(bSigned)) + conv_integer(signed(ySigned)) + conv_integer(signed(wSigned)), SIG_WIDTH + 2));
+end;
Index: src/vhdl/delayer_synth.vhd
===================================================================
--- src/vhdl/delayer_synth.vhd (nonexistent)
+++ src/vhdl/delayer_synth.vhd (revision 7)
@@ -0,0 +1,62 @@
+----------------------------------------------------------------------
+---- ----
+---- delayer_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of delayer is
+ type ARRAYdelay is array (0 to delay - 1) of std_logic_vector(d'length - 1 downto 0);
+ signal r : ARRAYdelay;
+begin
+ process (clk, rst)
+ begin
+ if rst = '0' then
+ q <= std_logic_vector(conv_unsigned(0, d'length));
+ for i in 0 to delay - 1 loop
+ r(i) <= (others => '0');
+ end loop;
+ elsif clk = '1' and clk'event then
+ r(0) <= d;
+ q <= r(delay - 1);
+ for i in 0 to delay - 2 loop
+ r(i + 1) <= r(i);
+ end loop;
+ end if;
+ end process;
+end;
Index: src/vhdl/turboDec_e.vhd
===================================================================
--- src/vhdl/turboDec_e.vhd (nonexistent)
+++ src/vhdl/turboDec_e.vhd (revision 7)
@@ -0,0 +1,60 @@
+----------------------------------------------------------------------
+---- ----
+---- turboDec_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.turbopack.all;
+
+entity turboDec is
+ port (
+ clk : in std_logic; -- clock
+ rst : in std_logic; -- negative reset
+ aNoisy : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- noisy signal
+ bNoisy : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- noisy signal
+ yNoisy : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- noisy signal
+ wNoisy : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- noisy signal
+ yIntNoisy : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- noisy signal
+ wIntNoisy : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- noisy signal
+ aDec : out std_logic_vector(IT - 1 downto 0); -- decoded signal for every iteration
+ bDec : out std_logic_vector(IT - 1 downto 0) -- decoded signal for every iteration
+ );
+end turboDec;
Index: src/vhdl/cod2_synth.vhd
===================================================================
--- src/vhdl/cod2_synth.vhd (nonexistent)
+++ src/vhdl/cod2_synth.vhd (revision 7)
@@ -0,0 +1,68 @@
+----------------------------------------------------------------------
+---- ----
+---- cod2_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of cod2 is
+begin
+ process (in1, in2, in3)
+ variable tmp : std_logic_vector(2 downto 0);
+ begin
+ tmp := in1 & in2 & in3;
+ case tmp is
+ when "101" =>
+ outCod <= "00";
+ when "111" =>
+ outCod <= "00";
+ when "001" =>
+ outCod <= "01";
+ when "011" =>
+ outCod <= "01";
+ when "010" =>
+ outCod <= "10";
+ when "110" =>
+ outCod <= "10";
+ when "000" =>
+ outCod <= "11";
+ when others =>
+ outCod <= "11";
+ end case;
+ end process;
+end;
Index: src/vhdl/distances_e.vhd
===================================================================
--- src/vhdl/distances_e.vhd (nonexistent)
+++ src/vhdl/distances_e.vhd (revision 7)
@@ -0,0 +1,56 @@
+----------------------------------------------------------------------
+---- ----
+---- distances_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.turbopack.all;
+
+entity distances is -- computes the 16 distances from the decoder input signals
+ port (
+ a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ y : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ w : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ z : in ARRAY4c; -- extrinsic information array
+ distance16 : out ARRAY16a -- distance signals (x16)
+ );
+end distances;
Index: src/vhdl/cmp2_synth.vhd
===================================================================
--- src/vhdl/cmp2_synth.vhd (nonexistent)
+++ src/vhdl/cmp2_synth.vhd (revision 7)
@@ -0,0 +1,47 @@
+----------------------------------------------------------------------
+---- ----
+---- cmp2_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of cmp2 is
+begin
+ res <= '0' when conv_integer(unsigned(op1)) > conv_integer(unsigned(op2)) else
+ '1';
+end;
Index: src/vhdl/stateSel_e.vhd
===================================================================
--- src/vhdl/stateSel_e.vhd (nonexistent)
+++ src/vhdl/stateSel_e.vhd (revision 7)
@@ -0,0 +1,52 @@
+----------------------------------------------------------------------
+---- ----
+---- stateSel_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.turbopack.all;
+
+entity stateSel is -- state selection (one out of eight)
+ port (
+ stateDist : in ARRAY8a; -- state accumulated distance
+ selState : out std_logic_vector(2 downto 0) -- selected state code
+ );
+end stateSel;
Index: src/vhdl/zPermut_synth.vhd
===================================================================
--- src/vhdl/zPermut_synth.vhd (nonexistent)
+++ src/vhdl/zPermut_synth.vhd (revision 7)
@@ -0,0 +1,77 @@
+----------------------------------------------------------------------
+---- ----
+---- zPermut_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of zPermut is
+begin
+ flipflop_g0 : if flip = 0 generate
+ process (flipflop, z)
+ begin
+ if flipflop = '0' then
+ zPerm(0) <= z(0);
+ zPerm(1) <= z(1);
+ zPerm(2) <= z(2);
+ zPerm(3) <= z(3);
+ else
+ zPerm(0) <= z(0);
+ zPerm(1) <= z(2);
+ zPerm(2) <= z(1);
+ zPerm(3) <= z(3);
+ end if;
+ end process;
+ end generate;
+ flipflop_g1 : if flip = 1 generate
+ process (flipflop, z)
+ begin
+ if flipflop = '1' then
+ zPerm(0) <= z(0);
+ zPerm(1) <= z(1);
+ zPerm(2) <= z(2);
+ zPerm(3) <= z(3);
+ else
+ zPerm(0) <= z(0);
+ zPerm(1) <= z(2);
+ zPerm(2) <= z(1);
+ zPerm(3) <= z(3);
+ end if;
+ end process;
+ end generate;
+end;
Index: src/vhdl/min4_synth.vhd
===================================================================
--- src/vhdl/min4_synth.vhd (nonexistent)
+++ src/vhdl/min4_synth.vhd (revision 7)
@@ -0,0 +1,78 @@
+----------------------------------------------------------------------
+---- ----
+---- min4_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of min4 is
+ signal res1_s : std_logic;
+ signal res2_s : std_logic;
+ signal op5 : std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
+ signal op6 : std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);
+begin
+ res1 <= res1_s;
+ res2 <= res2_s;
+ cmp2_i0 : cmp2 port map (
+ op1 => op1,
+ op2 => op2,
+ res => res1_s
+ );
+ cmp2_i1 : cmp2 port map (
+ op1 => op3,
+ op2 => op4,
+ res => res2_s
+ );
+ mux2_i0 : mux2 port map (
+ in1 => op1,
+ in2 => op2,
+ sel => res1_s,
+ outSel => op5
+ );
+ mux2_i1 : mux2 port map (
+ in1 => op3,
+ in2 => op4,
+ sel => res2_s,
+ outSel => op6
+ );
+ cmp2_i2 : cmp2 port map (
+ op1 => op5,
+ op2 => op6,
+ res => res3
+ );
+end;
Index: src/vhdl/cod3_e.vhd
===================================================================
--- src/vhdl/cod3_e.vhd (nonexistent)
+++ src/vhdl/cod3_e.vhd (revision 7)
@@ -0,0 +1,51 @@
+----------------------------------------------------------------------
+---- ----
+---- cod3_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cod3 is -- 3-bit coder
+ port (
+ inSig : in std_logic_vector(6 downto 0); -- 7 1-bit input signals
+ outCod : out std_logic_vector(2 downto 0) -- 3-bit coded value
+ );
+end cod3;
Index: src/vhdl/min8_synth.vhd
===================================================================
--- src/vhdl/min8_synth.vhd (nonexistent)
+++ src/vhdl/min8_synth.vhd (revision 7)
@@ -0,0 +1,119 @@
+----------------------------------------------------------------------
+---- ----
+---- min8_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of min8 is
+ signal tmp : ARRAY6a;
+ signal res_s : std_logic_vector(6 downto 0);
+begin
+ res <= res_s;
+ cmp2_i0 : cmp2 port map (
+ op1 => op(0),
+ op2 => op(1),
+ res => res_s(0)
+ );
+ cmp2_i1 : cmp2 port map (
+ op1 => op(2),
+ op2 => op(3),
+ res => res_s(1)
+ );
+ cmp2_i2 : cmp2 port map (
+ op1 => op(4),
+ op2 => op(5),
+ res => res_s(2)
+ );
+ cmp2_i3 : cmp2 port map (
+ op1 => op(6),
+ op2 => op(7),
+ res => res_s(3)
+ );
+ mux2_i0 : mux2 port map (
+ in1 => op(0),
+ in2 => op(1),
+ sel => res_s(0),
+ outSel => tmp(0)
+ );
+ mux2_i1 : mux2 port map (
+ in1 => op(2),
+ in2 => op(3),
+ sel => res_s(1),
+ outSel => tmp(1)
+ );
+ mux2_i2 : mux2 port map (
+ in1 => op(4),
+ in2 => op(5),
+ sel => res_s(2),
+ outSel => tmp(2)
+ );
+ mux2_i3 : mux2 port map (
+ in1 => op(6),
+ in2 => op(7),
+ sel => res_s(3),
+ outSel => tmp(3)
+ );
+ cmp2_i4 : cmp2 port map (
+ op1 => tmp(0),
+ op2 => tmp(1),
+ res => res_s(4)
+ );
+ cmp2_i5 : cmp2 port map (
+ op1 => tmp(2),
+ op2 => tmp(3),
+ res => res_s(5)
+ );
+ mux2_i4 : mux2 port map (
+ in1 => tmp(0),
+ in2 => tmp(1),
+ sel => res_s(4),
+ outSel => tmp(4)
+ );
+ mux2_i5 : mux2 port map (
+ in1 => tmp(2),
+ in2 => tmp(3),
+ sel => res_s(5),
+ outSel => tmp(5)
+ );
+ cmp2_i6 : cmp2 port map (
+ op1 => tmp(4),
+ op2 => tmp(5),
+ res => res_s(6)
+ );
+end;
Index: src/vhdl/coder_e.vhd
===================================================================
--- src/vhdl/coder_e.vhd (nonexistent)
+++ src/vhdl/coder_e.vhd (revision 7)
@@ -0,0 +1,55 @@
+----------------------------------------------------------------------
+---- ----
+---- coder_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity coder is
+ port (
+ clk : in std_logic; -- clock
+ rst : in std_logic; -- negative reset
+ a : in std_logic; -- original data signal (= systematic data)
+ b : in std_logic; -- original data signal (= systematic data)
+ y : out std_logic; -- coder redundant data signal
+ w : out std_logic -- coder redundant data signal
+ );
+end coder;
Index: src/vhdl/extInf_e.vhd
===================================================================
--- src/vhdl/extInf_e.vhd (nonexistent)
+++ src/vhdl/extInf_e.vhd (revision 7)
@@ -0,0 +1,59 @@
+----------------------------------------------------------------------
+---- ----
+---- extInf_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use work.turbopack.all;
+
+entity extInf is -- extrinsic information
+ port (
+ llr0 : in std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (0, 0)
+ llr1 : in std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (0, 1)
+ llr2 : in std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (1, 0)
+ llr3 : in std_logic_vector(ACC_DIST_WIDTH - 1 downto 0); -- LLR for (a, b) = (1, 1)
+ zin : in ARRAY4c; -- extrinsic information input signal
+ a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder systematic input signal
+ b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder systematic input signal
+ zout : out ARRAY4c -- extrinsic information output signal
+ );
+end extInf;
Index: src/vhdl/reg_synth.vhd
===================================================================
--- src/vhdl/reg_synth.vhd (nonexistent)
+++ src/vhdl/reg_synth.vhd (revision 7)
@@ -0,0 +1,53 @@
+----------------------------------------------------------------------
+---- ----
+---- reg_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of reg is
+begin
+ process (clk, rst)
+ begin
+ if rst = '0' then
+ q <= std_logic_vector(conv_unsigned(0, d'length));
+ elsif clk = '1' and clk'event then
+ q <= d;
+ end if;
+ end process;
+end;
Index: src/vhdl/accDistSel_synth.vhd
===================================================================
--- src/vhdl/accDistSel_synth.vhd (nonexistent)
+++ src/vhdl/accDistSel_synth.vhd (revision 7)
@@ -0,0 +1,77 @@
+----------------------------------------------------------------------
+---- ----
+---- accDistSel_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of accDistSel is
+ signal comp : std_logic_vector(23 downto 0);
+ signal accDistCod_s : ARRAY8b;
+begin
+ accDistCod <= accDistCod_s;
+ min4_g : for i in 0 to 7 generate
+ min4_i : min4 port map (
+ op1 => accDist(FROM2TO(4 * i)),
+ op2 => accDist(FROM2TO(4 * i + 1)),
+ op3 => accDist(FROM2TO(4 * i + 2)),
+ op4 => accDist(FROM2TO(4 * i + 3)),
+ res1 => comp(3 * i),
+ res2 => comp(3 * i + 1),
+ res3 => comp(3 * i + 2)
+ );
+ end generate;
+ cod2_g : for i in 0 to 7 generate
+ cod2_i : cod2 port map (
+ in1 => comp(3 * i),
+ in2 => comp(3 * i + 1),
+ in3 => comp(3 * i + 2),
+ outCod => accDistCod_s(i)
+ );
+ end generate;
+ mux4_g : for i in 0 to 7 generate
+ mux4_i : mux4 port map (
+ in1 => accDist(FROM2TO(4 * i)),
+ in2 => accDist(FROM2TO(4 * i + 1)),
+ in3 => accDist(FROM2TO(4 * i + 2)),
+ in4 => accDist(FROM2TO(4 * i + 3)),
+ sel => accDistCod_s(i),
+ outSel => accDistOut(i)
+ );
+ end generate;
+end;
Index: src/vhdl/limiter_e.vhd
===================================================================
--- src/vhdl/limiter_e.vhd (nonexistent)
+++ src/vhdl/limiter_e.vhd (revision 7)
@@ -0,0 +1,63 @@
+----------------------------------------------------------------------
+---- ----
+---- limiter_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use work.turbopack.all;
+
+entity limiter is
+ port (
+ a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
+ b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
+ y : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
+ w : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
+ yInt : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
+ wInt : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
+ aLim : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal
+ bLim : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal
+ yLim : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal
+ wLim : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal
+ yIntLim : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal
+ wIntLim : out std_logic_vector(SIG_WIDTH - 1 downto 0) -- limited signal
+ );
+end limiter;
Index: src/vhdl/acs_e.vhd
===================================================================
--- src/vhdl/acs_e.vhd (nonexistent)
+++ src/vhdl/acs_e.vhd (revision 7)
@@ -0,0 +1,62 @@
+----------------------------------------------------------------------
+---- ----
+---- acs_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.turbopack.all;
+
+entity acs is -- Add-Compare-Select top level
+ port (
+ clk : in std_logic; -- clock
+ rst : in std_logic; -- negative reset
+ a : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ b : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ y : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ w : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ z : in ARRAY4c; -- extrinsic information array
+ selStateL : in std_logic_vector(2 downto 0); -- selected state at t = L
+ selTransL : in std_logic_vector(1 downto 0); -- selected transition at selStateL
+ selState : out std_logic_vector(2 downto 0); -- selected state
+ stateDist : out ARRAY8b; -- selected accumulated distances (per state)
+ weight : out ARRAY4a -- four weights sorted by transition code
+ );
+end acs;
Index: src/vhdl/sova_e.vhd
===================================================================
--- src/vhdl/sova_e.vhd (nonexistent)
+++ src/vhdl/sova_e.vhd (revision 7)
@@ -0,0 +1,60 @@
+----------------------------------------------------------------------
+---- ----
+---- sova_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.turbopack.all;
+
+entity sova is -- Soft Output Viterbi Algorithm top level
+ port (
+ clk : in std_logic; -- clock
+ rst : in std_logic; -- negative reset
+ aNoisy : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ bNoisy : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ yNoisy : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ wNoisy : in std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
+ zin : in ARRAY4c; -- extrinsic information input
+ zout : out ARRAY4c; -- extrinsic information output
+ aClean : out std_logic; -- decoded systematic data
+ bClean : out std_logic -- decoded systematic data
+ );
+end sova;
Index: src/vhdl/punct_synth.vhd
===================================================================
--- src/vhdl/punct_synth.vhd (nonexistent)
+++ src/vhdl/punct_synth.vhd (revision 7)
@@ -0,0 +1,105 @@
+----------------------------------------------------------------------
+---- ----
+---- punct_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of punct is
+ subtype cnt_t is integer range 0 to 6;
+ signal pattern : std_logic_vector(0 to 11);
+ signal cntMax : cnt_t;
+ signal cnt : cnt_t;
+ signal ySel : std_logic;
+ signal wSel : std_logic;
+begin
+ pattern_g13 : if RATE = 13 generate
+ pattern <= "110000000000";
+ cntMax <= 1;
+ end generate;
+ pattern_g25 : if RATE = 25 generate
+ pattern <= "111000000000";
+ cntMax <= 2;
+ end generate;
+ pattern_g12 : if RATE = 12 generate
+ pattern <= "100000000000";
+ cntMax <= 1;
+ end generate;
+ pattern_g23 : if RATE = 23 generate
+ pattern <= "100000000000";
+ cntMax <= 2;
+ end generate;
+ pattern_g34 : if RATE = 34 generate
+ pattern <= "100000000000";
+ cntMax <= 3;
+ end generate;
+ pattern_g45 : if RATE = 45 generate
+ pattern <= "100000000000";
+ cntMax <= 4;
+ end generate;
+ pattern_g67 : if RATE = 67 generate
+ pattern <= "100000000000";
+ cntMax <= 6;
+ end generate;
+
+ process(clk, rst)
+ begin
+ if rst = '0' then
+ ySel <= '0';
+ wSel <= '0';
+ cnt <= 0;
+ elsif clk = '1' and clk'event then
+ if cnt < cntMax - 1 then
+ cnt <= cnt + 1;
+ else
+ cnt <= 0;
+ end if;
+ ySel <= pattern(cnt);
+ wSel <= pattern(cntMax + cnt);
+ end if;
+ end process;
+
+ yPunct <= y when ySel = '1' else
+ (others => '0');
+ wPunct <= w when wSel = '1' else
+ (others => '0');
+ yIntPunct <= yInt when ySel = '1' else
+ (others => '0');
+ wIntPunct <= wInt when wSel = '1' else
+ (others => '0');
+end;
Index: src/vhdl/distance_synth.vhd
===================================================================
--- src/vhdl/distance_synth.vhd (nonexistent)
+++ src/vhdl/distance_synth.vhd (revision 7)
@@ -0,0 +1,46 @@
+----------------------------------------------------------------------
+---- ----
+---- distance_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of distance is
+begin
+ dist <= std_logic_vector(conv_unsigned((4 * (2 ** (SIG_WIDTH - 1) - 1) + conv_integer(signed(partDist))) / 2 + conv_integer(unsigned(z)), ACC_DIST_WIDTH));
+end;
Index: src/vhdl/clkrst_beh.vhd
===================================================================
--- src/vhdl/clkrst_beh.vhd (nonexistent)
+++ src/vhdl/clkrst_beh.vhd (revision 7)
@@ -0,0 +1,54 @@
+----------------------------------------------------------------------
+---- ----
+---- clkrst_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture beh of clkrst is
+begin
+ rst <= '0', '1' after (period / 4);
+
+ process
+ begin
+ clk <= '0';
+ wait for (period / 2);
+ clk <= '1';
+ wait for (period / 2);
+ end process;
+end;
Index: src/vhdl/subs_e.vhd
===================================================================
--- src/vhdl/subs_e.vhd (nonexistent)
+++ src/vhdl/subs_e.vhd (revision 7)
@@ -0,0 +1,53 @@
+----------------------------------------------------------------------
+---- ----
+---- subs_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity subs is -- substracter (operands and result must be positive)
+ port (
+ op1 : in std_logic_vector; -- first operand
+ op2 : in std_logic_vector; -- second operand
+ res : out std_logic_vector -- result of the substraction
+ );
+end subs;
Index: src/vhdl/adder_e.vhd
===================================================================
--- src/vhdl/adder_e.vhd (nonexistent)
+++ src/vhdl/adder_e.vhd (revision 7)
@@ -0,0 +1,53 @@
+----------------------------------------------------------------------
+---- ----
+---- adder_e.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity adder is -- adder (positive numbers)
+ port (
+ op1 : in std_logic_vector; -- first operand
+ op2 : in std_logic_vector; -- second operand
+ res : out std_logic_vector -- result of the addition
+ );
+end adder;
Index: src/vhdl/trellis1_synth.vhd
===================================================================
--- src/vhdl/trellis1_synth.vhd (nonexistent)
+++ src/vhdl/trellis1_synth.vhd (revision 7)
@@ -0,0 +1,138 @@
+----------------------------------------------------------------------
+---- ----
+---- trellis1_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of trellis1 is
+ signal pathIdReg : ARRAY8d;
+ signal reg : ARRAY_TREL1_LENx8;
+begin
+ process (clk, rst)
+ variable free : std_logic_vector(7 downto 0);
+ variable freeBeg : std_logic_vector(7 downto 0);
+ variable pastState : ARRAY8d;
+ variable pathId : ARRAY8d;
+ variable current_state : INT3BIT;
+ variable freePathId : INT3BIT;
+ variable state_l3 : INT2BIT;
+ variable state_l2 : INT2BIT;
+ variable state_l1 : INT2BIT;
+ variable outState_l2 : std_logic_vector(2 downto 0);
+ variable outState_l1 : std_logic_vector(2 downto 0);
+ begin
+ if rst = '0' then
+ for i in 0 to 3 loop
+ stateL1(i) <= (others => '0');
+ end loop;
+ selStateL1 <= (others => '0');
+ selStateL2 <= (others => '0');
+ selTransL2 <= (others => '0');
+ for i in 0 to 7 loop
+ pathIdReg(i) <= 0;
+ for j in 0 to TREL1_LEN - 1 loop
+ reg(j * 8 + i) <= 0;
+ end loop;
+ end loop;
+ elsif clk = '1' and clk'event then
+ free := "11111111";
+ for i in 0 to 7 loop
+ pastState(i) := TRANS2STATE(i * 4 + conv_integer(unsigned(selTrans(i))));
+ pathId(i) := pathIdReg(pastState(i));
+ free(pathId(i)) := '0';
+ end loop;
+ freeBeg := "11111111";
+ for i in 0 to 7 loop
+ current_state := i;
+ if freeBeg(pathId(current_state)) = '1' then
+ reg(pathId(current_state)) <= conv_integer(unsigned(std_logic_vector(conv_unsigned(current_state, 3))(1 downto 0)));
+ freeBeg(pathId(i)) := '0';
+ pathIdReg(current_state) <= pathId(current_state);
+ for j in 0 to TREL1_LEN - 2 loop
+ reg((j + 1) * 8 + pathId(current_state)) <= reg(j * 8 + pathId(current_state));
+ end loop;
+ else
+ if free(0) = '1' then
+ freePathId := 0;
+ end if;
+ if free(1 downto 0) = "10" then
+ freePathId := 1;
+ end if;
+ if free(2 downto 0) = "100" then
+ freePathId := 2;
+ end if;
+ if free(3 downto 0) = "1000" then
+ freePathId := 3;
+ end if;
+ if free(4 downto 0) = "10000" then
+ freePathId := 4;
+ end if;
+ if free(5 downto 0) = "100000" then
+ freePathId := 5;
+ end if;
+ if free(6 downto 0) = "1000000" then
+ freePathId := 6;
+ end if;
+ if free(7 downto 0) = "10000000" then
+ freePathId := 7;
+ end if;
+ reg(freePathId) <= conv_integer(unsigned(std_logic_vector(conv_unsigned(current_state, 3))(1 downto 0)));
+ free(freePathId) := '0';
+ pathIdReg(current_state) <= freePathId;
+ for j in 0 to TREL1_LEN - 2 loop
+ reg((j + 1) * 8 + freePathId) <= reg(j * 8 + pathId(current_state));
+ end loop;
+ end if;
+ end loop;
+ state_l3 := reg((TREL1_LEN - 3) * 8 + pathId(conv_integer(unsigned(selState))));
+ state_l2 := reg((TREL1_LEN - 2) * 8 + pathId(conv_integer(unsigned(selState))));
+ state_l1 := reg((TREL1_LEN - 1) * 8 + pathId(conv_integer(unsigned(selState))));
+ outState_l2(2) := std_logic_vector(conv_unsigned(state_l3, 2))(1) xor (std_logic_vector(conv_unsigned(state_l3, 2))(0) xor std_logic_vector(conv_unsigned(state_l2, 2))(1));
+ outState_l2(1 downto 0) := std_logic_vector(conv_unsigned(state_l2, 2));
+ outState_l1(2) := std_logic_vector(conv_unsigned(state_l2, 2))(1) xor (std_logic_vector(conv_unsigned(state_l2, 2))(0) xor std_logic_vector(conv_unsigned(state_l1, 2))(1));
+ outState_l1(1 downto 0) := std_logic_vector(conv_unsigned(state_l1, 2));
+ selStateL1 <= outState_l1;
+ selStateL2 <= outState_l2;
+ selTransL2 <= std_logic_vector(conv_unsigned(STATE2TRANS(conv_integer(unsigned(outState_l2)) * 4 + state_l1), 2));
+ for i in 0 to 3 loop
+ stateL1(i) <= std_logic_vector(conv_unsigned(TRANS2STATE(conv_integer(unsigned(outState_l2)) * 4 + i), 3));
+ end loop;
+ end if;
+ end process;
+end;
Index: src/vhdl/turboDec_synth.vhd
===================================================================
--- src/vhdl/turboDec_synth.vhd (nonexistent)
+++ src/vhdl/turboDec_synth.vhd (revision 7)
@@ -0,0 +1,118 @@
+----------------------------------------------------------------------
+---- ----
+---- turboDec_synth.vhd ----
+---- ----
+---- This file is part of the turbo decoder IP core project ----
+---- http://www.opencores.org/projects/turbocodes/ ----
+---- ----
+---- Author(s): ----
+---- - David Brochart(dbrochart@opencores.org) ----
+---- ----
+---- All additional information is available in the README.txt ----
+---- file. ----
+---- ----
+----------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2005 Authors ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------
+
+
+
+architecture synth of turboDec is
+ signal flipflop : std_logic;
+ signal aLim : ARRAY_ITa;
+ signal bLim : ARRAY_ITa;
+ signal yLim : ARRAY_ITa;
+ signal wLim : ARRAY_ITa;
+ signal yIntLim : ARRAY_ITa;
+ signal wIntLim : ARRAY_ITa;
+ signal z : ARRAY_ITb;
+ signal yFull : std_logic_vector(SIG_WIDTH - 1 downto 0);
+ signal wFull : std_logic_vector(SIG_WIDTH - 1 downto 0);
+ signal yIntFull : std_logic_vector(SIG_WIDTH - 1 downto 0);
+ signal wIntFull : std_logic_vector(SIG_WIDTH - 1 downto 0);
+begin
+ limiter_i0 : limiter port map (
+ a => aNoisy,
+ b => bNoisy,
+ y => yNoisy,
+ w => wNoisy,
+ yInt => yIntNoisy,
+ wInt => wIntNoisy,
+ aLim => aLim(0),
+ bLim => bLim(0),
+ yLim => yFull,
+ wLim => wFull,
+ yIntLim => yIntFull,
+ wIntLim => wIntFull
+ );
+
+ punct_i0 : punct port map (
+ clk => clk,
+ rst => rst,
+ y => yFull,
+ w => wFull,
+ yInt => yIntFull,
+ wInt => wIntFull,
+ yPunct => yLim(0),
+ wPunct => wLim(0),
+ yIntPunct => yIntLim(0),
+ wIntPunct => wIntLim(0)
+ );
+ clkDiv_i0 : clkDiv port map (
+ clk => clk,
+ rst => rst,
+ clkout => flipflop
+ );
+
+ z(0) <= ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
+
+ iteration_g : for i in 0 to (IT - 1) generate
+ iteration_i : iteration generic map (
+ delay => 2 * i * (TREL1_LEN + TREL2_LEN + 2) + 2 * i * FRSIZE + 2
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ flipflop => flipflop,
+ a => aLim(i),
+ b => bLim(i),
+ y => yLim(i),
+ w => wLim(i),
+ yInt => yIntLim(i),
+ wInt => wIntLim(i),
+ zin => z(i),
+ zout => z(i + 1),
+ aDec => aDec(i),
+ bDec => bDec(i),
+ aDel => aLim(i + 1),
+ bDel => bLim(i + 1),
+ yDel => yLim(i + 1),
+ wDel => wLim(i + 1),
+ yIntDel => yIntLim(i + 1),
+ wIntDel => wIntLim(i + 1)
+ );
+ end generate;
+end;