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Rev 100 → Rev 101

/rtl/app_localcfg/lcfg.v
0,0 → 1,225
/* Copyright (c) 2011, Guy Hutchison
All rights reserved.
 
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
 
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
* Neither the name of the author nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
 
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
//----------------------------------------------------------------------
// Author: Guy Hutchison
//
// Local Configuration Processor Application
//----------------------------------------------------------------------
 
module lcfg
(input clk,
input reset_n,
input lcfg_proc_reset,
input scan_mode,
input scan_enable,
 
// incoming config interface to
// read/write processor memory
input cfgi_irdy,
output cfgi_trdy,
input [14:0] cfgi_addr,
input cfgi_write,
input [31:0] cfgi_wr_data,
output [31:0] cfgi_rd_data,
 
// outgoing config interface to system
// configuration bus
output cfgo_irdy,
input cfgo_trdy,
output [15:0] cfgo_addr,
output cfgo_write,
output [31:0] cfgo_wr_data,
input [31:0] cfgo_rd_data
 
);
 
wire [15:0] addr;
wire [7:0] dout;
reg [7:0] di;
wire mreq_n;
wire rd_n, wr_n;
wire iorq_n;
 
reg fw_mode;
wire ram_wait_n;
 
wire fw_en = (addr[15:13] == {1'b0, !fw_mode, 1'b0}) && !mreq_n;
wire fw_we = !wr_n;
 
wire [7:0] ram_rd_data;
reg last_wait;
reg wait_n;
 
wire [7:0] reg_addr1, reg_addr0;
wire [7:0] reg_wr_data3;
wire [7:0] reg_wr_data2;
wire [7:0] reg_wr_data1;
wire [7:0] reg_wr_data0;
wire [7:0] cb_rd_data;
wire [1:0] cb_control;
reg [1:0] cb_control_clr;
wire [7:0] tim_rd_data;
wire [1:0] fw_up_ctrl;
wire dma_iorq_n;
wire [7:0] dma_rd_data;
reg [31:0] read_hold;
reg read_latch;
wire dma_int_n; // From dma of mx_lcfg_dma.v
wire proc_reset_n;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] cd_rdata; // From cfgo_driver of lcfg_cfgo_driver.v
wire cfgo_wait_n; // From cfgo_driver of lcfg_cfgo_driver.v
// End of automatics
wire ram_mreq_n;
 
assign ram_mreq_n = ~ (~mreq_n & ~addr[15]);
assign proc_reset_n = (scan_mode) ? 1'b1 : ~lcfg_proc_reset;
 
tv80s tv80 (
// Outputs
.dout (dout),
.m1_n (),
.mreq_n (mreq_n),
.iorq_n (iorq_n),
.rd_n (rd_n),
.wr_n (wr_n),
.rfsh_n (),
.halt_n (),
.busak_n (),
.A (addr),
// Inputs
.reset_n (proc_reset_n),
.clk (clk),
.wait_n (wait_n),
.int_n (dma_int_n),
.nmi_n (1'b1),
.busrq_n (1'b1),
.di (di));
 
always @(posedge clk)
begin
last_wait <= #1 wait_n;
end
always @*
begin
wait_n = 1;
if (!mreq_n)
begin
if (~ram_mreq_n)
begin
di = ram_rd_data[7:0];
wait_n = ram_wait_n;
end
else
begin
di = 8'h0;
end
end
else if (!iorq_n)
begin
if (addr[7:3] == 0)
begin
di = cd_rdata;
wait_n = cfgo_wait_n;
end
else
di = 8'h0;
end
else
di = 8'h0;
end // always @ *
/* lcfg_memctl AUTO_TEMPLATE
(
// Outputs
.a_mreq_n (ram_mreq_n),
.a_rd_n (rd_n),
.a_wr_n (wr_n),
.a_addr (addr[14:0]),
.a_wdata (dout),
.a_wait_n (ram_wait_n),
.a_rdata (ram_rd_data),
.b_wait_n (),
.b_rdata (),
.b_mreq_n (1'b1),
.b_wr_n (1'b1),
.b_addr (13'h0),
.b_wdata (32'h0),
);
*/
lcfg_memctl memctl
(/*AUTOINST*/
// Outputs
.a_wait_n (ram_wait_n), // Templated
.a_rdata (ram_rd_data), // Templated
.b_wait_n (), // Templated
.b_rdata (), // Templated
.cfgi_trdy (cfgi_trdy),
.cfgi_rd_data (cfgi_rd_data[31:0]),
// Inputs
.clk (clk),
.reset_n (reset_n),
.a_mreq_n (ram_mreq_n), // Templated
.a_rd_n (rd_n), // Templated
.a_wr_n (wr_n), // Templated
.a_addr (addr[14:0]), // Templated
.a_wdata (dout), // Templated
.b_mreq_n (1'b1), // Templated
.b_wr_n (1'b1), // Templated
.b_addr (13'h0), // Templated
.b_wdata (32'h0), // Templated
.lcfg_init (lcfg_init),
.cfgi_irdy (cfgi_irdy),
.cfgi_addr (cfgi_addr[14:0]),
.cfgi_write (cfgi_write),
.cfgi_wr_data (cfgi_wr_data[31:0]),
.test_resume_h (test_resume_h));
// DMA not needed
// Need GP interrupt register for timer
 
assign cfg_addr = { reg_addr1, reg_addr0 };
assign cfg_wr_data = { reg_wr_data3, reg_wr_data2, reg_wr_data1, reg_wr_data0 };
 
/* lcfg_cfgo_driver AUTO_TEMPLATE
(
.cd_wdata (dout[7:0]),
);
*/
lcfg_cfgo_driver #(.io_base_addr(8'h0)) cfgo_driver
(/*AUTOINST*/
// Outputs
.cd_rdata (cd_rdata[7:0]),
.cfgo_wait_n (cfgo_wait_n),
.cfgo_irdy (cfgo_irdy),
.cfgo_addr (cfgo_addr[15:0]),
.cfgo_write (cfgo_write),
.cfgo_wr_data (cfgo_wr_data[31:0]),
// Inputs
.clk (clk),
.reset_n (reset_n),
.addr (addr[15:0]),
.cd_wdata (dout[7:0]), // Templated
.mreq_n (mreq_n),
.rd_n (rd_n),
.wr_n (wr_n),
.iorq_n (iorq_n),
.cfgo_trdy (cfgo_trdy),
.cfgo_rd_data (cfgo_rd_data[31:0]));
 
endmodule
/rtl/app_localcfg/lcfg_memctl.v
0,0 → 1,406
/* Copyright (c) 2011, Guy Hutchison
All rights reserved.
 
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
 
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
* Neither the name of the author nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
 
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
//----------------------------------------------------------------------
// Author: Guy Hutchison
//
// Memory Controller/Arbiter
//----------------------------------------------------------------------
 
module lcfg_memctl
(/*AUTOARG*/
// Outputs
a_wait_n, a_rdata, b_wait_n, b_rdata, cfgi_trdy, cfgi_rd_data,
// Inputs
clk, reset_n, a_mreq_n, a_rd_n, a_wr_n, a_addr, a_wdata, b_mreq_n,
b_wr_n, b_addr, b_wdata, lcfg_init, cfgi_irdy, cfgi_addr,
cfgi_write, cfgi_wr_data, test_resume_h
);
 
input clk;
input reset_n;
 
// read port A (uP)
input a_mreq_n;
input a_rd_n;
input a_wr_n;
input [14:0] a_addr;
output a_wait_n;
input [7:0] a_wdata;
output [7:0] a_rdata;
reg a_wait_n;
 
// read port B
input b_mreq_n;
input b_wr_n;
input [12:0] b_addr;
output b_wait_n;
input [31:0] b_wdata;
output [31:0] b_rdata;
reg b_wait_n;
 
input lcfg_init;
 
// incoming config interface to
// read/write processor memory
input cfgi_irdy;
output cfgi_trdy;
input [14:0] cfgi_addr;
input cfgi_write;
input [31:0] cfgi_wr_data;
output [31:0] cfgi_rd_data;
reg cfgi_trdy, nxt_cfgi_trdy;
 
input test_resume_h;
reg ram_nwrt;
reg ram_nce;
reg [31:0] ram_din;
reg [12:0] ram_addr;
wire [31:0] dout;
reg [7:0] a_rdata;
 
reg [12:0] ca_addr, nxt_ca_addr;
reg [31:0] ca_data, nxt_ca_data;
reg [12:0] wc_addr, nxt_wc_addr;
reg [31:0] wc_data, nxt_wc_data;
reg cvld, nxt_cvld;
reg wcvld, nxt_wcvld;
 
reg a_prio, nxt_a_prio;
reg a_rip, nxt_a_rip; // read in progress by A
reg a_wip, nxt_a_wip; // write (read-cache-fill) in progress by A
reg b_rip, nxt_b_rip; // read in progress by B
wire t_ram_nwrt, t_ram_nce;
wire [35:0] t_ram_din;
wire c_rip = lcfg_data_rd_ack;
wire a_cache_hit, b_cache_hit;
wire [12:0] t_ram_addr;
 
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] d_out; // From mem of behave1p_mem.v
// End of automatics
 
assign #1 t_ram_nwrt = ram_nwrt;
assign #1 t_ram_nce = ram_nce;
assign #1 t_ram_addr = ram_addr;
assign #1 t_ram_din = ram_din;
 
assign lcfg_data_rd_data = dout;
assign b_rdata = dout;
 
assign a_cache_hit = cvld & (ca_addr == a_addr[14:2]);
assign b_cache_hit = wcvld & (wc_addr == a_addr[14:2]);
/* behave1p_mem AUTO_TEMPLATE
(
// Outputs
.rd_data (dout),
// Inputs
.wr_en (!t_ram_nce & !t_ram_nwrt),
.rd_en (!t_ram_nce & t_ram_nwrt),
.clk (clk),
.wr_data (t_ram_din[]),
.addr (t_ram_addr[]),
);
*/
 
behave1p_mem #(.width(32),
.depth (8192),
.addr_sz (13)) mem
(/*AUTOINST*/
// Outputs
.d_out (d_out[31:0]),
// Inputs
.wr_en (!t_ram_nce & !t_ram_nwrt), // Templated
.rd_en (!t_ram_nce & t_ram_nwrt), // Templated
.clk (clk), // Templated
.d_in (d_in[31:0]),
.addr (t_ram_addr[12:0])); // Templated
always @*
begin
nxt_ca_addr = ca_addr;
ram_nwrt = 1;
ram_nce = 1;
ram_din = 32'h0;
ram_addr = a_addr[14:2];
a_wait_n = 1;
b_wait_n = 1;
nxt_a_prio = a_prio;
nxt_a_rip = 0;
nxt_b_rip = 0;
nxt_a_wip = a_wip;
nxt_ca_data = ca_data;
nxt_cvld = cvld;
nxt_wcvld = wcvld;
nxt_wc_data = wc_data;
nxt_wc_addr = wc_addr;
nxt_cfgi_trdy = 0;
//nxt_lcfg_data_rd_ack = 0;
//nxt_lcfg_data_wr_ack = 0;
 
if (a_cache_hit)
begin
case (a_addr[1:0])
0 : a_rdata = ca_data[7:0];
1 : a_rdata = ca_data[15:8];
2 : a_rdata = ca_data[23:16];
3 : a_rdata = ca_data[31:24];
endcase // case(a_addr[1:0])
end
else if (b_cache_hit)
begin
case (a_addr[1:0])
0 : a_rdata = wc_data[7:0];
1 : a_rdata = wc_data[15:8];
2 : a_rdata = wc_data[23:16];
3 : a_rdata = wc_data[31:24];
endcase // case(a_addr[1:0])
end
else
a_rdata = 0;
 
if (lcfg_init)
begin
// repurpose the cache bits as FSM status bits
// cvld == done
if (!cvld)
begin
ram_nce = 0;
ram_addr = ca_addr;
ram_nwrt = 0;
ram_din = 32'h0;
if (ca_addr == 8191)
begin
nxt_ca_addr = ca_addr;
nxt_cvld = 1;
nxt_ca_data = 32'h0;
end
else
nxt_ca_addr = ca_addr + 1;
end
end
else
begin
if (!a_mreq_n)
begin
if (!a_rd_n)
begin
// check for cache hit
if (!a_cache_hit & !b_cache_hit)
begin
a_wait_n = 0;
if (a_rip)
begin
nxt_ca_addr = a_addr[14:2];
nxt_ca_data = dout;
nxt_cvld = 1;
end
else if (a_prio | b_mreq_n)
begin
ram_addr = a_addr[14:2];
nxt_a_prio = 0;
ram_nce = 0;
nxt_a_rip = 1;
end
end // if (ca_addr != a_addr[14:2])
end // if (!rd_n)
else if (!a_wr_n)
begin
if (a_prio | b_mreq_n)
begin
// if data is in our read cache, transfer it to the
// write cache, invalidate the read cache, update the
// appropriate data byte, and start the B cache
// write-back
if (a_cache_hit)
begin
nxt_cvld = 0;
case (a_addr[1:0])
0 : nxt_wc_data = { ca_data[31:8], a_wdata };
1 : nxt_wc_data = { ca_data[31:16], a_wdata, ca_data[7:0] };
2 : nxt_wc_data = { ca_data[31:24], a_wdata, ca_data[15:0] };
3 : nxt_wc_data = { a_wdata, ca_data[23:0] };
endcase // case(a_addr[1:0])
nxt_wc_addr = ca_addr;
nxt_a_wip = 1;
nxt_a_prio = 1;
end
 
// if read is in progress, we have the results of our
// cache fill. Store this in the write cache so next
// cycle we will get a cache hit.
else if (a_rip)
begin
a_wait_n = 0;
nxt_wc_data = dout;
nxt_wc_addr = a_addr[14:2];
nxt_wcvld = 1;
end
 
// if we get a write cache hit, we have the data we
// need. Change the data in the write cache and trigger
// a write-back next cycle.
else if (b_cache_hit)
begin
case (a_addr[1:0])
0 : nxt_wc_data[7:0] = a_wdata;
1 : nxt_wc_data[15:8] = a_wdata;
2 : nxt_wc_data[23:16] = a_wdata;
3 : nxt_wc_data[31:24] = a_wdata;
endcase // case(a_addr[1:0])
nxt_a_wip = 1;
nxt_a_prio = 1;
end
 
// otherwise we do not have the data in our write cache
// yet. Trigger a read to fill the write cache.
else if (a_prio | b_mreq_n)
begin
a_wait_n = 0;
ram_addr = a_addr[14:2];
nxt_a_prio = 0;
ram_nce = 0;
nxt_a_rip = 1;
end
end
else
a_wait_n = 0;
end
end // if (!a_mreq_n)
else
begin
if (a_wip & (a_prio|b_mreq_n))
begin
ram_addr = wc_addr;
nxt_a_prio = 0;
ram_nce = 0;
ram_nwrt = 0;
nxt_a_wip = 0;
ram_din = wc_data;
end
end
 
if (!b_mreq_n)
begin
if (!b_wr_n)
begin
if (!a_prio | a_mreq_n)
begin
ram_addr = b_addr;
nxt_a_prio = 1;
ram_nce = 0;
ram_nwrt = 0;
ram_din = b_wdata;
if (b_addr == ca_addr)
nxt_cvld = 0;
if (wc_addr == ca_addr)
nxt_wcvld = 0;
end
else
b_wait_n = 0;
end // if (!b_wr_n)
else
begin
if (b_rip)
begin
b_wait_n = 1;
end
else if (!a_prio | a_mreq_n)
begin
ram_addr = b_addr;
nxt_b_rip = 1;
nxt_a_prio = 1;
ram_nce = 0;
b_wait_n = 0;
end
end
end // if (!b_mreq_n)
 
if (cfgi_irdy)
begin
if ((!a_mreq_n | !b_mreq_n) & !c_rip)
begin
// access by A or B ports, stall until memory is free
end
else
begin
if (cfgi_write & !cfgi_trdy)
begin
nxt_cfgi_trdy = 1;
ram_nce = 0;
ram_nwrt = 0;
ram_addr = lcfg_cfg_addr;
ram_din = lcfg_data_wr_data;
// invalidate caches as precaution
nxt_cvld = 0;
nxt_wcvld = 0;
end
else if (!cfgi_write & !cfgi_trdy)
begin
ram_nce = 0;
ram_addr = lcfg_cfg_addr;
nxt_cfgi_trdy = 1;
end
end
end
end // if (lcfg_init)
end // always @ *
 
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
begin
ca_addr <= 13'h0;
cvld <= #1 0;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
a_prio <= 1'h0;
a_rip <= 1'h0;
a_wip <= 1'h0;
b_rip <= 1'h0;
ca_data <= 32'h0;
cfgi_trdy <= 1'h0;
wc_addr <= 13'h0;
wc_data <= 32'h0;
wcvld <= 1'h0;
// End of automatics
end
else
begin
cvld <= #1 nxt_cvld;
ca_addr <= #1 nxt_ca_addr;
ca_data <= #1 nxt_ca_data;
wcvld <= #1 nxt_wcvld;
wc_addr <= #1 nxt_wc_addr;
wc_data <= #1 nxt_wc_data;
a_prio <= #1 nxt_a_prio;
a_rip <= #1 nxt_a_rip;
b_rip <= #1 nxt_b_rip;
a_wip <= #1 nxt_a_wip;
cfgi_trdy <= #1 nxt_cfgi_trdy;
end
end
 
endmodule // memcontrol
 
// Local Variables:
// verilog-library-files:(".")
// End:
 
/rtl/app_localcfg/lcfg_cfgo_driver.v
0,0 → 1,173
/* Copyright (c) 2011, Guy Hutchison
All rights reserved.
 
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
 
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
* Neither the name of the author nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
 
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
module lcfg_cfgo_driver
(/*AUTOARG*/
// Outputs
cd_rdata, cfgo_wait_n, cfgo_irdy, cfgo_addr, cfgo_write,
cfgo_wr_data,
// Inputs
clk, reset_n, addr, cd_wdata, mreq_n, rd_n, wr_n, iorq_n, cfgo_trdy,
cfgo_rd_data
);
 
parameter io_base_addr = 0;
input clk;
input reset_n;
 
// TV80 processor interface
input [15:0] addr;
output [7:0] cd_rdata;
input [7:0] cd_wdata;
input mreq_n;
input rd_n, wr_n;
input iorq_n;
output cfgo_wait_n;
 
// outgoing config interface to system
// configuration bus
output cfgo_irdy;
input cfgo_trdy;
output [15:0] cfgo_addr;
output cfgo_write;
output [31:0] cfgo_wr_data;
input [31:0] cfgo_rd_data;
 
wire rf_irdy;
wire rf_write;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] cfg_addr0; // From cfgo_regs of lcfg_cfgo_regs.v
wire [7:0] cfg_addr1; // From cfgo_regs of lcfg_cfgo_regs.v
wire [7:0] cfg_data0_wr_data; // From cfgo_regs of lcfg_cfgo_regs.v
wire [7:0] cfg_data1_wr_data; // From cfgo_regs of lcfg_cfgo_regs.v
wire [7:0] cfg_data2_wr_data; // From cfgo_regs of lcfg_cfgo_regs.v
wire [7:0] cfg_data3_wr_data; // From cfgo_regs of lcfg_cfgo_regs.v
wire [3:0] rd_stb; // From cfgo_regs of lcfg_cfgo_regs.v, ...
wire [3:0] wr_stb; // From cfgo_regs of lcfg_cfgo_regs.v, ...
// End of automatics
 
parameter s_idle = 0, s_write = 1, s_read = 2, s_ack = 3;
reg [31:0] chold, nxt_chold;
reg [3:0] state, nxt_state;
assign rf_irdy = !mreq_n & !iorq_n & ((addr[7:0] & 8'hF8) == io_base_addr);
assign rf_write = ~wr_n;
assign cfgo_addr = { cfg_addr1, cfg_addr0 };
assign cfgo_wr_data = chold;
assign cfgo_irdy = state[s_write] | state[s_read];
assign cfgo_write = state[s_write];
 
always @*
begin
nxt_chold = chold;
nxt_state = state;
case (1'b1)
state[s_idle] :
begin
case (wr_stb)
4'b0001 : nxt_chold[7:0] = cfg_data0_wr_data;
4'b0010 : nxt_chold[15:8] = cfg_data1_wr_data;
4'b0100 : nxt_chold[23:16] = cfg_data2_wr_data;
4'b1000 : nxt_chold[31:24] = cfg_data3_wr_data;
endcase // case (wr_stb)
if (rd_stb[0])
nxt_state = 1 << s_read;
else if (wr_stb[3])
nxt_state = 1 << s_write;
end // case: state[s_idle]
 
state[s_write] :
begin
if (cfgo_trdy)
nxt_state = 1 << s_idle;
end
 
state[s_read] :
begin
if (cfgo_trdy)
begin
nxt_state = 1 << s_ack;
nxt_chold = cfgo_rd_data;
end
end
 
state[s_ack] :
begin
nxt_state = 1 << s_idle;
end
endcase // case (1'b1)
end // always @ *
/* lcfg_cfgo_regs AUTO_TEMPLATE
(
.rf_trdy (cfgo_wait_n),
.rf_rd_data (cd_rdata[]),
.rf_addr (addr[]),
.rf_wr_data (cd_wdata[]),
.cfg_data\([0-3]\)_rd_data (chold[@"(+ (* 8 @) 7)":@"(* 8 @)"]),
.cfg_data0_rd_data (chold[7:0]),
.cfg_data1_rd_data (chold[15:8]),
.cfg_data2_rd_data (chold[23:16]),
.cfg_data3_rd_data (chold[31:24]),
.cfg_data0_rd_ack (state[s_ack]),
.cfg_data[1-3]_rd_ack (1'b1),
.cfg_data[0-3]_wr_ack (state[s_idle]),
.cfg_data\([0-3]\)_wr_stb (wr_stb[\1]),
.cfg_data\([0-3]\)_rd_stb (rd_stb[\1]),
);
*/
lcfg_cfgo_regs cfgo_regs
(/*AUTOINST*/
// Outputs
.rf_trdy (cfgo_wait_n), // Templated
.rf_rd_data (cd_rdata[7:0]), // Templated
.cfg_addr0 (cfg_addr0[7:0]),
.cfg_addr1 (cfg_addr1[7:0]),
.cfg_data0_wr_stb (wr_stb[0]), // Templated
.cfg_data0_rd_stb (rd_stb[0]), // Templated
.cfg_data0_wr_data (cfg_data0_wr_data[7:0]),
.cfg_data1_wr_stb (wr_stb[1]), // Templated
.cfg_data1_rd_stb (rd_stb[1]), // Templated
.cfg_data1_wr_data (cfg_data1_wr_data[7:0]),
.cfg_data2_wr_stb (wr_stb[2]), // Templated
.cfg_data2_rd_stb (rd_stb[2]), // Templated
.cfg_data2_wr_data (cfg_data2_wr_data[7:0]),
.cfg_data3_wr_stb (wr_stb[3]), // Templated
.cfg_data3_rd_stb (rd_stb[3]), // Templated
.cfg_data3_wr_data (cfg_data3_wr_data[7:0]),
// Inputs
.clk (clk),
.reset_n (reset_n),
.rf_irdy (rf_irdy),
.rf_write (rf_write),
.rf_addr (addr[3:0]), // Templated
.rf_wr_data (cd_wdata[7:0]), // Templated
.cfg_data0_rd_data (chold[7:0]), // Templated
.cfg_data0_rd_ack (state[s_ack]), // Templated
.cfg_data0_wr_ack (state[s_idle]), // Templated
.cfg_data1_rd_data (chold[15:8]), // Templated
.cfg_data1_rd_ack (1'b1), // Templated
.cfg_data1_wr_ack (state[s_idle]), // Templated
.cfg_data2_rd_data (chold[23:16]), // Templated
.cfg_data2_rd_ack (1'b1), // Templated
.cfg_data2_wr_ack (state[s_idle]), // Templated
.cfg_data3_rd_data (chold[31:24]), // Templated
.cfg_data3_rd_ack (1'b1), // Templated
.cfg_data3_wr_ack (state[s_idle]), // Templated
.cfg_status (cfg_status[7:0]));
endmodule
/rtl/app_localcfg/lcfg_cfgo_regs.xml
0,0 → 1,35
<!--
Copyright (c) 2011, Guy Hutchison
All rights reserved.
 
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
 
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
* Neither the name of the author nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
 
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-->
 
<tv_registers name="lcfg_cfgo_regs" addr_sz="4" data_sz="8" base_addr="0">
<register name="cfg_addr0" type="config" width="8" default="8'h00">
</register>
<register name="cfg_addr1" type="config" width="8" default="8'h00">
</register>
 
<register name="cfg_data0" type="user" width="8">
Read this register first for read ops
</register>
<register name="cfg_data1" type="user" width="8">
</register>
<register name="cfg_data2" type="user" width="8">
</register>
<register name="cfg_data3" type="user" width="8">
Write this register last for write ops
</register>
 
<register name="cfg_status" type="status" width="8">
</register>
</tv_registers>
/rtl/app_localcfg/behave1p_mem.v
0,0 → 1,52
//----------------------------------------------------------------------
// Author: Guy Hutchison
//
// This block is uncopyrighted and released into the public domain.
//----------------------------------------------------------------------
 
module behave1p_mem
#(parameter width=8,
parameter depth=256,
parameter addr_sz=8) //log2(depth))
(/*AUTOARG*/
// Outputs
d_out,
// Inputs
wr_en, rd_en, clk, d_in, addr
);
input wr_en, rd_en, clk;
input [width-1:0] d_in;
input [addr_sz-1:0] addr;
 
output [width-1:0] d_out;
 
reg [addr_sz-1:0] r_addr;
 
reg [width-1:0] array[0:depth-1];
always @(posedge clk)
begin
if (wr_en)
begin
array[addr] <= #1 d_in;
end
else if (rd_en)
begin
r_addr <= #1 addr;
end
end // always @ (posedge clk)
 
assign d_out = array[r_addr];
 
genvar g;
 
generate
for (g=0; g<depth; g=g+1)
begin : breakout
wire [width-1:0] brk;
 
assign brk=array[g];
end
endgenerate
 
endmodule
/rtl/app_localcfg/lcfg_cfgo_regs.v
0,0 → 1,435
module lcfg_cfgo_regs (
clk,reset_n,rf_irdy,rf_trdy,rf_write,rf_addr,rf_wr_data,rf_rd_data,cfg_addr0,cfg_addr1,cfg_data0_wr_stb,cfg_data0_rd_stb,cfg_data0_wr_data,cfg_data0_rd_data,cfg_data0_rd_ack,cfg_data0_wr_ack,cfg_data1_wr_stb,cfg_data1_rd_stb,cfg_data1_wr_data,cfg_data1_rd_data,cfg_data1_rd_ack,cfg_data1_wr_ack,cfg_data2_wr_stb,cfg_data2_rd_stb,cfg_data2_wr_data,cfg_data2_rd_data,cfg_data2_rd_ack,cfg_data2_wr_ack,cfg_data3_wr_stb,cfg_data3_rd_stb,cfg_data3_wr_data,cfg_data3_rd_data,cfg_data3_rd_ack,cfg_data3_wr_ack,cfg_status);
input clk;
input reset_n;
input rf_irdy;
output rf_trdy;
input rf_write;
input [3:0] rf_addr;
input [7:0] rf_wr_data;
output [7:0] rf_rd_data;
output [7:0] cfg_addr0;
output [7:0] cfg_addr1;
output cfg_data0_wr_stb;
output cfg_data0_rd_stb;
output [7:0] cfg_data0_wr_data;
input [7:0] cfg_data0_rd_data;
input cfg_data0_rd_ack;
input cfg_data0_wr_ack;
output cfg_data1_wr_stb;
output cfg_data1_rd_stb;
output [7:0] cfg_data1_wr_data;
input [7:0] cfg_data1_rd_data;
input cfg_data1_rd_ack;
input cfg_data1_wr_ack;
output cfg_data2_wr_stb;
output cfg_data2_rd_stb;
output [7:0] cfg_data2_wr_data;
input [7:0] cfg_data2_rd_data;
input cfg_data2_rd_ack;
input cfg_data2_wr_ack;
output cfg_data3_wr_stb;
output cfg_data3_rd_stb;
output [7:0] cfg_data3_wr_data;
input [7:0] cfg_data3_rd_data;
input cfg_data3_rd_ack;
input cfg_data3_wr_ack;
input [7:0] cfg_status;
reg [7:0] rf_rd_data;
reg nxt_rf_trdy;
reg rf_trdy;
reg [7:0] cfg_addr0;
reg [7:0] nxt_cfg_addr0;
reg cfg_addr0_rd_sel;
reg cfg_addr0_wr_sel;
reg [7:0] cfg_addr1;
reg [7:0] nxt_cfg_addr1;
reg cfg_addr1_rd_sel;
reg cfg_addr1_wr_sel;
reg cfg_data0_rd_sel;
reg cfg_data0_wr_sel;
reg cfg_data0_rd_stb;
reg cfg_data0_wr_stb;
reg cfg_data0_wait_n;
reg [7:0] cfg_data0;
reg [7:0] cfg_data0_wr_data;
reg [1:0] sm_cfg_data0_state;
reg [1:0] nxt_sm_cfg_data0_state;
reg cfg_data1_rd_sel;
reg cfg_data1_wr_sel;
reg cfg_data1_rd_stb;
reg cfg_data1_wr_stb;
reg cfg_data1_wait_n;
reg [7:0] cfg_data1;
reg [7:0] cfg_data1_wr_data;
reg [1:0] sm_cfg_data1_state;
reg [1:0] nxt_sm_cfg_data1_state;
reg cfg_data2_rd_sel;
reg cfg_data2_wr_sel;
reg cfg_data2_rd_stb;
reg cfg_data2_wr_stb;
reg cfg_data2_wait_n;
reg [7:0] cfg_data2;
reg [7:0] cfg_data2_wr_data;
reg [1:0] sm_cfg_data2_state;
reg [1:0] nxt_sm_cfg_data2_state;
reg cfg_data3_rd_sel;
reg cfg_data3_wr_sel;
reg cfg_data3_rd_stb;
reg cfg_data3_wr_stb;
reg cfg_data3_wait_n;
reg [7:0] cfg_data3;
reg [7:0] cfg_data3_wr_data;
reg [1:0] sm_cfg_data3_state;
reg [1:0] nxt_sm_cfg_data3_state;
reg cfg_status_rd_sel;
always @*
begin
cfg_addr0_rd_sel = (rf_addr[3:0] == 0) & rf_irdy & !rf_write;
cfg_addr0_wr_sel = (rf_addr[3:0] == 0) & rf_irdy & rf_write;
 
cfg_addr1_rd_sel = (rf_addr[3:0] == 1) & rf_irdy & !rf_write;
cfg_addr1_wr_sel = (rf_addr[3:0] == 1) & rf_irdy & rf_write;
 
cfg_data0_rd_sel = (rf_addr[3:0] == 2) & rf_irdy & !rf_write;
cfg_data0_wr_sel = (rf_addr[3:0] == 2) & rf_irdy & rf_write;
 
cfg_data1_rd_sel = (rf_addr[3:0] == 3) & rf_irdy & !rf_write;
cfg_data1_wr_sel = (rf_addr[3:0] == 3) & rf_irdy & rf_write;
 
cfg_data2_rd_sel = (rf_addr[3:0] == 4) & rf_irdy & !rf_write;
cfg_data2_wr_sel = (rf_addr[3:0] == 4) & rf_irdy & rf_write;
 
cfg_data3_rd_sel = (rf_addr[3:0] == 5) & rf_irdy & !rf_write;
cfg_data3_wr_sel = (rf_addr[3:0] == 5) & rf_irdy & rf_write;
 
cfg_status_rd_sel = (rf_addr[3:0] == 6) & rf_irdy & !rf_write;
end
always @*
begin
case (1'b1)
cfg_addr0_rd_sel : rf_rd_data = cfg_addr0;
cfg_addr1_rd_sel : rf_rd_data = cfg_addr1;
cfg_data0_rd_sel : rf_rd_data = cfg_data0;
cfg_data1_rd_sel : rf_rd_data = cfg_data1;
cfg_data2_rd_sel : rf_rd_data = cfg_data2;
cfg_data3_rd_sel : rf_rd_data = cfg_data3;
cfg_status_rd_sel : rf_rd_data = cfg_status;
default : rf_rd_data = 8'b0;
endcase
end
always @*
begin
if (rf_trdy) nxt_rf_trdy = 0;
else if (rf_irdy) nxt_rf_trdy = cfg_data0_wait_n & cfg_data1_wait_n & cfg_data2_wait_n & cfg_data3_wait_n;
else nxt_rf_trdy = 0;
end
always @(posedge clk or negedge reset_n)
begin
if (~reset_n) rf_trdy <= #1 0;
else rf_trdy <= #1 nxt_rf_trdy;
end
// config: cfg_addr0
always @*
begin
if (cfg_addr0_wr_sel) nxt_cfg_addr0 = rf_wr_data;
else nxt_cfg_addr0 = cfg_addr0;
end
always @(posedge clk or negedge reset_n)
begin
if (~reset_n) cfg_addr0 <= #1 8'h0;
else cfg_addr0 <= #1 nxt_cfg_addr0;
end
// config: cfg_addr1
always @*
begin
if (cfg_addr1_wr_sel) nxt_cfg_addr1 = rf_wr_data;
else nxt_cfg_addr1 = cfg_addr1;
end
always @(posedge clk or negedge reset_n)
begin
if (~reset_n) cfg_addr1 <= #1 8'h0;
else cfg_addr1 <= #1 nxt_cfg_addr1;
end
// state machine sm_cfg_data0
parameter st_sm_cfg_data0_w_clear = 0;
parameter st_sm_cfg_data0_idle = 1;
parameter st_sm_cfg_data0_wr_req = 2;
parameter st_sm_cfg_data0_rd_req = 3;
always @*
begin
cfg_data0_rd_stb = 0;
cfg_data0_wr_stb = 0;
cfg_data0_wait_n = 1;
nxt_sm_cfg_data0_state = sm_cfg_data0_state;
case (sm_cfg_data0_state)
st_sm_cfg_data0_w_clear :
begin
if (~(cfg_data0_rd_sel | cfg_data0_wr_sel))
begin
nxt_sm_cfg_data0_state = st_sm_cfg_data0_idle;
end
end
st_sm_cfg_data0_idle :
begin
if (cfg_data0_rd_sel)
begin
nxt_sm_cfg_data0_state = st_sm_cfg_data0_rd_req;
cfg_data0_wait_n = 0;
end
else if (cfg_data0_wr_sel)
begin
nxt_sm_cfg_data0_state = st_sm_cfg_data0_wr_req;
cfg_data0_wait_n = 0;
end
end
st_sm_cfg_data0_wr_req :
begin
if (cfg_data0_wr_ack)
begin
nxt_sm_cfg_data0_state = st_sm_cfg_data0_w_clear;
end
else if (!cfg_data0_wr_ack)
begin
cfg_data0_wait_n = 0;
end
cfg_data0_wr_stb = 1;
end
st_sm_cfg_data0_rd_req :
begin
if (cfg_data0_rd_ack)
begin
nxt_sm_cfg_data0_state = st_sm_cfg_data0_w_clear;
end
else if (!cfg_data0_rd_ack)
begin
cfg_data0_wait_n = 0;
end
cfg_data0_rd_stb = 1;
end
endcase
end
always @(posedge clk or negedge reset_n)
begin
if(~reset_n)
sm_cfg_data0_state <= #1 st_sm_cfg_data0_idle;
else
sm_cfg_data0_state <= #1 nxt_sm_cfg_data0_state;
end
always @*
begin
cfg_data0_wr_data = rf_wr_data;
cfg_data0 = cfg_data0_rd_data;
end
// state machine sm_cfg_data1
parameter st_sm_cfg_data1_w_clear = 0;
parameter st_sm_cfg_data1_idle = 1;
parameter st_sm_cfg_data1_wr_req = 2;
parameter st_sm_cfg_data1_rd_req = 3;
always @*
begin
cfg_data1_rd_stb = 0;
cfg_data1_wr_stb = 0;
cfg_data1_wait_n = 1;
nxt_sm_cfg_data1_state = sm_cfg_data1_state;
case (sm_cfg_data1_state)
st_sm_cfg_data1_w_clear :
begin
if (~(cfg_data1_rd_sel | cfg_data1_wr_sel))
begin
nxt_sm_cfg_data1_state = st_sm_cfg_data1_idle;
end
end
st_sm_cfg_data1_idle :
begin
if (cfg_data1_rd_sel)
begin
nxt_sm_cfg_data1_state = st_sm_cfg_data1_rd_req;
cfg_data1_wait_n = 0;
end
else if (cfg_data1_wr_sel)
begin
nxt_sm_cfg_data1_state = st_sm_cfg_data1_wr_req;
cfg_data1_wait_n = 0;
end
end
st_sm_cfg_data1_wr_req :
begin
if (cfg_data1_wr_ack)
begin
nxt_sm_cfg_data1_state = st_sm_cfg_data1_w_clear;
end
else if (!cfg_data1_wr_ack)
begin
cfg_data1_wait_n = 0;
end
cfg_data1_wr_stb = 1;
end
st_sm_cfg_data1_rd_req :
begin
if (cfg_data1_rd_ack)
begin
nxt_sm_cfg_data1_state = st_sm_cfg_data1_w_clear;
end
else if (!cfg_data1_rd_ack)
begin
cfg_data1_wait_n = 0;
end
cfg_data1_rd_stb = 1;
end
endcase
end
always @(posedge clk or negedge reset_n)
begin
if(~reset_n)
sm_cfg_data1_state <= #1 st_sm_cfg_data1_idle;
else
sm_cfg_data1_state <= #1 nxt_sm_cfg_data1_state;
end
always @*
begin
cfg_data1_wr_data = rf_wr_data;
cfg_data1 = cfg_data1_rd_data;
end
// state machine sm_cfg_data2
parameter st_sm_cfg_data2_w_clear = 0;
parameter st_sm_cfg_data2_idle = 1;
parameter st_sm_cfg_data2_wr_req = 2;
parameter st_sm_cfg_data2_rd_req = 3;
always @*
begin
cfg_data2_rd_stb = 0;
cfg_data2_wr_stb = 0;
cfg_data2_wait_n = 1;
nxt_sm_cfg_data2_state = sm_cfg_data2_state;
case (sm_cfg_data2_state)
st_sm_cfg_data2_w_clear :
begin
if (~(cfg_data2_rd_sel | cfg_data2_wr_sel))
begin
nxt_sm_cfg_data2_state = st_sm_cfg_data2_idle;
end
end
st_sm_cfg_data2_idle :
begin
if (cfg_data2_rd_sel)
begin
nxt_sm_cfg_data2_state = st_sm_cfg_data2_rd_req;
cfg_data2_wait_n = 0;
end
else if (cfg_data2_wr_sel)
begin
nxt_sm_cfg_data2_state = st_sm_cfg_data2_wr_req;
cfg_data2_wait_n = 0;
end
end
st_sm_cfg_data2_wr_req :
begin
if (cfg_data2_wr_ack)
begin
nxt_sm_cfg_data2_state = st_sm_cfg_data2_w_clear;
end
else if (!cfg_data2_wr_ack)
begin
cfg_data2_wait_n = 0;
end
cfg_data2_wr_stb = 1;
end
st_sm_cfg_data2_rd_req :
begin
if (cfg_data2_rd_ack)
begin
nxt_sm_cfg_data2_state = st_sm_cfg_data2_w_clear;
end
else if (!cfg_data2_rd_ack)
begin
cfg_data2_wait_n = 0;
end
cfg_data2_rd_stb = 1;
end
endcase
end
always @(posedge clk or negedge reset_n)
begin
if(~reset_n)
sm_cfg_data2_state <= #1 st_sm_cfg_data2_idle;
else
sm_cfg_data2_state <= #1 nxt_sm_cfg_data2_state;
end
always @*
begin
cfg_data2_wr_data = rf_wr_data;
cfg_data2 = cfg_data2_rd_data;
end
// state machine sm_cfg_data3
parameter st_sm_cfg_data3_w_clear = 0;
parameter st_sm_cfg_data3_idle = 1;
parameter st_sm_cfg_data3_wr_req = 2;
parameter st_sm_cfg_data3_rd_req = 3;
always @*
begin
cfg_data3_rd_stb = 0;
cfg_data3_wr_stb = 0;
cfg_data3_wait_n = 1;
nxt_sm_cfg_data3_state = sm_cfg_data3_state;
case (sm_cfg_data3_state)
st_sm_cfg_data3_w_clear :
begin
if (~(cfg_data3_rd_sel | cfg_data3_wr_sel))
begin
nxt_sm_cfg_data3_state = st_sm_cfg_data3_idle;
end
end
st_sm_cfg_data3_idle :
begin
if (cfg_data3_rd_sel)
begin
nxt_sm_cfg_data3_state = st_sm_cfg_data3_rd_req;
cfg_data3_wait_n = 0;
end
else if (cfg_data3_wr_sel)
begin
nxt_sm_cfg_data3_state = st_sm_cfg_data3_wr_req;
cfg_data3_wait_n = 0;
end
end
st_sm_cfg_data3_wr_req :
begin
if (cfg_data3_wr_ack)
begin
nxt_sm_cfg_data3_state = st_sm_cfg_data3_w_clear;
end
else if (!cfg_data3_wr_ack)
begin
cfg_data3_wait_n = 0;
end
cfg_data3_wr_stb = 1;
end
st_sm_cfg_data3_rd_req :
begin
if (cfg_data3_rd_ack)
begin
nxt_sm_cfg_data3_state = st_sm_cfg_data3_w_clear;
end
else if (!cfg_data3_rd_ack)
begin
cfg_data3_wait_n = 0;
end
cfg_data3_rd_stb = 1;
end
endcase
end
always @(posedge clk or negedge reset_n)
begin
if(~reset_n)
sm_cfg_data3_state <= #1 st_sm_cfg_data3_idle;
else
sm_cfg_data3_state <= #1 nxt_sm_cfg_data3_state;
end
always @*
begin
cfg_data3_wr_data = rf_wr_data;
cfg_data3 = cfg_data3_rd_data;
end
// status: cfg_status
endmodule

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