URL
https://opencores.org/ocsvn/tv80/tv80/trunk
Subversion Repositories tv80
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- This comparison shows the changes necessary to convert path
/tv80/trunk
- from Rev 102 to Rev 103
- ↔ Reverse comparison
Rev 102 → Rev 103
/rtl/app_localcfg/lcfg.v
19,9 → 19,8
module lcfg |
(input clk, |
input reset_n, |
input lcfg_init, // initialize memory to all 0 |
input lcfg_proc_reset, |
input scan_mode, |
input scan_enable, |
|
// incoming config interface to |
// read/write processor memory |
84,7 → 83,7
wire ram_mreq_n; |
|
assign ram_mreq_n = ~ (~mreq_n & ~addr[15]); |
assign proc_reset_n = (scan_mode) ? 1'b1 : ~lcfg_proc_reset; |
assign proc_reset_n = ~lcfg_proc_reset; |
|
tv80s tv80 ( |
// Outputs |
/rtl/app_localcfg/lcfg_memctl.v
82,7 → 82,7
reg b_rip, nxt_b_rip; // read in progress by B |
wire t_ram_nwrt, t_ram_nce; |
wire [35:0] t_ram_din; |
wire c_rip = lcfg_data_rd_ack; |
wire c_rip = cfgi_trdy; |
wire a_cache_hit, b_cache_hit; |
wire [12:0] t_ram_addr; |
|
106,12 → 106,12
/* behave1p_mem AUTO_TEMPLATE |
( |
// Outputs |
.rd_data (dout), |
.rd_data (dout), |
// Inputs |
.wr_en (!t_ram_nce & !t_ram_nwrt), |
.rd_en (!t_ram_nce & t_ram_nwrt), |
.clk (clk), |
.wr_data (t_ram_din[]), |
.wr_en (!t_ram_nce & !t_ram_nwrt), |
.rd_en (!t_ram_nce & t_ram_nwrt), |
.clk (clk), |
.d_in (t_ram_din[]), |
.addr (t_ram_addr[]), |
); |
*/ |
126,7 → 126,7
.wr_en (!t_ram_nce & !t_ram_nwrt), // Templated |
.rd_en (!t_ram_nce & t_ram_nwrt), // Templated |
.clk (clk), // Templated |
.d_in (d_in[31:0]), |
.d_in (t_ram_din[31:0]), // Templated |
.addr (t_ram_addr[12:0])); // Templated |
|
always @* |
148,8 → 148,6
nxt_wc_data = wc_data; |
nxt_wc_addr = wc_addr; |
nxt_cfgi_trdy = 0; |
//nxt_lcfg_data_rd_ack = 0; |
//nxt_lcfg_data_wr_ack = 0; |
|
if (a_cache_hit) |
begin |
346,8 → 344,8
nxt_cfgi_trdy = 1; |
ram_nce = 0; |
ram_nwrt = 0; |
ram_addr = lcfg_cfg_addr; |
ram_din = lcfg_data_wr_data; |
ram_addr = cfgi_addr; |
ram_din = cfgi_wr_data; |
// invalidate caches as precaution |
nxt_cvld = 0; |
nxt_wcvld = 0; |
355,7 → 353,7
else if (!cfgi_write & !cfgi_trdy) |
begin |
ram_nce = 0; |
ram_addr = lcfg_cfg_addr; |
ram_addr = cfgi_addr; |
nxt_cfgi_trdy = 1; |
end |
end |
/rtl/app_localcfg/lcfg_cfgo_driver.v
129,6 → 129,7
.cfg_data[0-3]_wr_ack (state[s_idle]), |
.cfg_data\([0-3]\)_wr_stb (wr_stb[\1]), |
.cfg_data\([0-3]\)_rd_stb (rd_stb[\1]), |
.cfg_status ({4'h0,state}), |
); |
*/ |
lcfg_cfgo_regs cfgo_regs |
169,5 → 170,5
.cfg_data3_rd_data (chold[31:24]), // Templated |
.cfg_data3_rd_ack (1'b1), // Templated |
.cfg_data3_wr_ack (state[s_idle]), // Templated |
.cfg_status (cfg_status[7:0])); |
.cfg_status ({4'h0,state})); // Templated |
endmodule |
/rtl/app_localcfg/behave1p_mem.v
38,15 → 38,4
|
assign d_out = array[r_addr]; |
|
genvar g; |
|
generate |
for (g=0; g<depth; g=g+1) |
begin : breakout |
wire [width-1:0] brk; |
|
assign brk=array[g]; |
end |
endgenerate |
|
endmodule |