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URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

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  • This comparison shows the changes necessary to convert path
    /tv80/trunk
    from Rev 108 to Rev 109
    Reverse comparison

Rev 108 → Rev 109

/rtl/app_localcfg/lcfg.v
73,7 → 73,6
wire [7:0] dma_rd_data;
reg [31:0] read_hold;
reg read_latch;
wire dma_int_n; // From dma of mx_lcfg_dma.v
wire proc_reset_n;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
101,7 → 100,7
.reset_n (proc_reset_n),
.clk (clk),
.wait_n (wait_n),
.int_n (dma_int_n),
.int_n (1'b1),
.nmi_n (1'b1),
.busrq_n (1'b1),
.di (di));
208,7 → 207,6
.reset_n (reset_n),
.addr (addr[15:0]),
.cd_wdata (dout[7:0]), // Templated
.mreq_n (mreq_n),
.rd_n (rd_n),
.wr_n (wr_n),
.iorq_n (iorq_n),
/rtl/app_localcfg/lcfg_cfgo_driver.v
16,7 → 16,7
cd_rdata, cfgo_wait_n, cfgo_irdy, cfgo_addr, cfgo_write,
cfgo_wr_data,
// Inputs
clk, reset_n, addr, cd_wdata, mreq_n, rd_n, wr_n, iorq_n, cfgo_trdy,
clk, reset_n, addr, cd_wdata, rd_n, wr_n, iorq_n, cfgo_trdy,
cfgo_rd_data
);
 
29,7 → 29,6
output [7:0] cd_rdata;
input [7:0] cd_wdata;
input mreq_n;
input rd_n, wr_n;
input iorq_n;
output cfgo_wait_n;
62,7 → 61,7
reg [31:0] chold, nxt_chold;
reg [3:0] state, nxt_state;
assign rf_irdy = !mreq_n & !iorq_n & ((addr[7:0] & 8'hF8) == io_base_addr);
assign rf_irdy = !iorq_n & ((addr[7:0] & 8'hF8) == io_base_addr);
assign rf_write = ~wr_n;
assign cfgo_addr = { cfg_addr1, cfg_addr0 };
assign cfgo_wr_data = chold;
184,5 → 183,5
.cfg_data3_rd_data (chold[31:24]), // Templated
.cfg_data3_rd_ack (1'b1), // Templated
.cfg_data3_wr_ack (state[s_idle]), // Templated
.cfg_status ({4'h0, state})); // Templated
.cfg_status ({4'h0,state})); // Templated
endmodule

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