URL
https://opencores.org/ocsvn/uart16750/uart16750/trunk
Subversion Repositories uart16750
Compare Revisions
- This comparison shows the changes necessary to convert path
/uart16750/trunk
- from Rev 22 to Rev 23
- ↔ Reverse comparison
Rev 22 → Rev 23
/sim/rtl_sim/run/Makefile
7,9 → 7,10
PERL = perl |
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# Directories |
SRCDIR = vhdl |
TBDIR = tbench |
SIMDIR = sim |
SRCDIR = ../../../rtl/vhdl |
TBDIR = ../../../bench/vhdl |
SIMDIR = ../bin |
LOGDIR = ../log |
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# UART16750 sources |
SRC = slib_clock_div.vhd |
32,13 → 33,13
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# Testbench stimuli and log |
TBSTIMGEN = $(SIMDIR)/uart_test_stim.pl |
TBSTIMDAT = $(SIMDIR)/uart_stim.dat |
TBLOG = $(SIMDIR)/uart_log.txt |
TBVCD = $(SIMDIR)/uart_log.vcd |
TBSTIMDAT = uart_stim.dat |
TBLOG = $(LOGDIR)/uart_log.txt |
TBVCD = $(LOGDIR)/uart_log.vcd |
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# Simulation entity and options |
SIMPROG = uart_transactor |
SIMOPTS = --stop-time=140ms |
SIMOPTS = --stop-time=160ms |
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all: $(SIMPROG) |
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51,6 → 52,7
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sim: $(SIMPROG) $(TBSTIMDAT) |
$(GHDL) -r $(SIMPROG) $(SIMOPTS) |
cp uart_log.txt $(TBLOG) |
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vcd: $(SIMPROG) $(TBSTIMDAT) |
$(GHDL) -r $(SIMPROG) $(SIMOPTS) --vcd=$(TBVCD) |
/sim/rtl_sim/bin/uart_test_stim.pl
800,6 → 800,8
if (TEST_AFC) { |
uart_check_afc (); |
} |
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logmessage ("UART: Test end"); |
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################################################################## |
# End main process |