URL
https://opencores.org/ocsvn/uart2bus/uart2bus/trunk
Subversion Repositories uart2bus
Compare Revisions
- This comparison shows the changes necessary to convert path
/uart2bus/trunk/verilog/bench
- from Rev 4 to Rev 12
- ↔ Reverse comparison
Rev 4 → Rev 12
/tb_txt_uart2bus_top.v
55,10 → 55,6
#100; |
send_serial (8'h20, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0); |
#100; |
send_serial (8'h34, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0); |
#100; |
send_serial (8'h63, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0); |
#100; |
send_serial (8'h64, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0); |
#100; |
send_serial (8'h39, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0); |
136,6 → 132,8
wire int_write; // write control to register file |
wire int_read; // read control to register file |
wire [7:0] int_rd_data; // data read from register file |
wire int_req; // bus access request signal |
wire int_gnt; // bus access grant signal |
wire ser_in; // DUT serial input |
wire ser_out; // DUT serial output |
|
150,8 → 148,12
.int_wr_data(int_wr_data), |
.int_write(int_write), |
.int_rd_data(int_rd_data), |
.int_read(int_read) |
.int_read(int_read), |
.int_req(int_req), |
.int_gnt(int_gnt) |
); |
// bus grant is always active |
assign int_gnt = 1'b1; |
|
// serial interface to test bench |
assign ser_in = serial_out; |
/tb_uart2bus_top.v
137,6 → 137,8
wire int_write; // write control to register file |
wire int_read; // read control to register file |
wire [7:0] int_rd_data; // data read from register file |
wire int_req; // bus access request signal |
wire int_gnt; // bus access grant signal |
wire ser_in; // DUT serial input |
wire ser_out; // DUT serial output |
|
146,8 → 148,11
.clock(clock), .reset(reset), |
.ser_in(ser_in), .ser_out(ser_out), |
.int_address(int_address), .int_wr_data(int_wr_data), .int_write(int_write), |
.int_rd_data(int_rd_data), .int_read(int_read) |
.int_rd_data(int_rd_data), .int_read(int_read), |
.int_req(int_req), .int_gnt(int_gnt) |
); |
// bus grant is always active |
assign int_gnt = 1'b1; |
|
// serial interface to test bench |
assign ser_in = serial_out; |
/uart_tasks.v
238,7 → 238,6
if (serial_in != 1) |
get_serial_status = get_serial_status | `RECEIVE_RESULT_BADSTOP; |
end |
#(bit_time/2); |
end |
end |
end |
/tb_bin_uart2bus_top.v
191,6 → 191,8
wire int_write; // write control to register file |
wire int_read; // read control to register file |
wire [7:0] int_rd_data; // data read from register file |
wire int_req; // bus access request signal |
wire int_gnt; // bus access grant signal |
wire ser_in; // DUT serial input |
wire ser_out; // DUT serial output |
|
205,8 → 207,12
.int_wr_data(int_wr_data), |
.int_write(int_write), |
.int_rd_data(int_rd_data), |
.int_read(int_read) |
.int_read(int_read), |
.int_req(int_req), |
.int_gnt(int_gnt) |
); |
// bus grant is always active |
assign int_gnt = 1'b1; |
|
// serial interface to test bench |
assign ser_in = serial_out; |