URL
https://opencores.org/ocsvn/uart2bus/uart2bus/trunk
Subversion Repositories uart2bus
Compare Revisions
- This comparison shows the changes necessary to convert path
/uart2bus/trunk/verilog/rtl
- from Rev 4 to Rev 9
- ↔ Reverse comparison
Rev 4 → Rev 9
/uart_rx.v
69,7 → 69,7
rx_busy <= 1'b0; |
else if (~rx_busy & ce_1_mid) |
rx_busy <= 1'b1; |
else if (rx_busy & (bit_count == 4'h9) & ce_1) |
else if (rx_busy & (bit_count == 4'h8) & ce_1_mid) |
rx_busy <= 1'b0; |
end |
|
/uart_tx.v
51,7 → 51,7
tx_busy <= 1'b0; |
else if (~tx_busy & new_tx_data) |
tx_busy <= 1'b1; |
else if (tx_busy & (bit_count == 4'ha) & ce_1) |
else if (tx_busy & (bit_count == 4'h9) & ce_1) |
tx_busy <= 1'b0; |
end |
|