OpenCores
URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /uart2bus/trunk/verilog/sim
    from Rev 2 to Rev 4
    ↔ Reverse comparison
  •

Rev 2 → Rev 4

/icarus/compile.bat File deleted
/icarus/block.cfg File deleted
/icarus/block_bin.cfg
0,0 → 1,9
+incdir+../../bench
../../rtl/baud_gen.v
../../rtl/uart_tx.v
../../rtl/uart_rx.v
../../rtl/uart_top.v
../../rtl/uart_parser.v
../../rtl/uart2bus_top.v
../../bench/reg_file_model.v
../../bench/tb_bin_uart2bus_top.v
/icarus/compile_bin.bat
0,0 → 1,9
iverilog -o test.vvp -cblock_bin.cfg
/icarus/block_txt.cfg
0,0 → 1,9
+incdir+../../bench
../../rtl/baud_gen.v
../../rtl/uart_tx.v
../../rtl/uart_rx.v
../../rtl/uart_top.v
../../rtl/uart_parser.v
../../rtl/uart2bus_top.v
../../bench/reg_file_model.v
../../bench/tb_txt_uart2bus_top.v
/icarus/compile_txt.bat
0,0 → 1,9
iverilog -o test.vvp -cblock_txt.cfg

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.