URL
https://opencores.org/ocsvn/uart2bus/uart2bus/trunk
Subversion Repositories uart2bus
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/uart2bus/trunk/verilog
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/rtl/baud_gen.v
7,6 → 7,7
// baud_freq = 16*baud_rate / gcd(global_clock_freq, 16*baud_rate) |
// second register: |
// baud_limit = (global_clock_freq / gcd(global_clock_freq, 16*baud_rate)) - baud_freq |
// |
//--------------------------------------------------------------------------------------- |
|
module baud_gen |