URL
https://opencores.org/ocsvn/uart2bus/uart2bus/trunk
Subversion Repositories uart2bus
Compare Revisions
- This comparison shows the changes necessary to convert path
/uart2bus/trunk/vhdl/rtl
- from Rev 11 to Rev 13
- ↔ Reverse comparison
Rev 11 → Rev 13
/baudGen.vhd
11,7 → 11,7
----------------------------------------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.numeric_std.all; |
|
entity baudGen is |
port ( clr : in std_logic; -- global reset input |
37,10 → 37,10
ce16 <= '0'; |
elsif (rising_edge(clk)) then |
if (counter >= baudLimit) then |
counter <= counter - baudLimit; |
counter <= std_logic_vector(unsigned(counter) - unsigned(baudLimit)); |
ce16 <= '1'; |
else |
counter <= counter + baudFreq; |
counter <= std_logic_vector(unsigned(counter) + unsigned(baudFreq)); |
ce16 <= '0'; |
end if; |
end if; |
/uartRx.vhd
4,7 → 4,7
----------------------------------------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.ALL; |
use ieee.std_logic_unsigned.ALL; |
use ieee.numeric_std.ALL; |
|
entity uartRx is |
port ( clr : in std_logic; -- global reset input |
45,7 → 45,7
elsif (rising_edge(clk)) then |
if (ce16 = '1') then |
if ((rxBusy = '1') or (inSync(1) = '0')) then |
count16 <= count16 + 1; |
count16 <= std_logic_vector(unsigned(count16) + 1); |
else |
count16 <= (others => '0'); |
end if; |
74,7 → 74,7
if (rxBusy = '0') then |
bitCount <= (others => '0'); |
elsif ((rxBusy = '1') and (ce1Mid = '1')) then |
bitCount <= bitCount + 1; |
bitCount <= std_logic_vector(unsigned(bitCount) + 1); |
end if; |
end if; |
end process; |
/uartTx.vhd
4,7 → 4,7
----------------------------------------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.numeric_std.all; |
|
entity uartTx is |
port ( clr : in std_logic; -- global reset input |
32,7 → 32,7
count16 <= (others => '0'); |
elsif (rising_edge(clk)) then |
if ((iTxBusy = '1') and (ce16 = '1')) then |
count16 <= count16 + 1; |
count16 <= std_logic_vector(unsigned(count16) + 1); |
elsif (iTxBusy = '0') then |
count16 <= (others => '0'); |
end if; |
58,7 → 58,7
bitCount <= (others => '0'); |
elsif (rising_edge(clk)) then |
if ((iTxBusy = '1') and (ce1 = '1')) then |
bitCount <= bitCount + 1; |
bitCount <= std_logic_vector(unsigned(bitCount) + 1); |
elsif (iTxBusy = '0') then |
bitCount <= (others => '0'); |
end if; |
/uartParser.vhd
4,7 → 4,7
----------------------------------------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.ALL; |
use ieee.std_logic_unsigned.ALL; |
use ieee.numeric_std.ALL; |
|
entity uartParser is |
generic ( -- parameters |
351,7 → 351,7
elsif (((mainSm = mainBinData) and (binWriteOp = '1') and (newRxData = '1')) or ((binReadOp = '1') and (txEndP = '1'))) then |
-- byte counter is updated on every new data received in write operations and for every |
-- byte transmitted for read operations. |
binByteCount <= binByteCount - 1; |
binByteCount <= std_logic_vector(unsigned(binByteCount) - 1); |
end if; |
end if; |
end process; |
411,7 → 411,7
iIntAddress <= addrParam(AW - 1 downto 0); |
elsif ((addrAutoInc = '1') and (((binReadOp = '1') and (txEndP = '1') and (binLastByte = '0')) or ((binWriteOp = '1') and (iIntWrite = '1')))) then |
-- address is incremented on every read or write if enabled |
iIntAddress <= iIntAddress + 1; |
iIntAddress <= std_logic_vector(unsigned(iIntAddress) + 1); |
end if; |
end if; |
end process; |