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URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

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  • This comparison shows the changes necessary to convert path 
    /uart2bus
    from Rev 12 to Rev 13
    ↔ Reverse comparison
  •

Rev 12 → Rev 13

/trunk/vhdl/bench/helpers/helpers_pkg.vhd
1,8 → 1,12
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
package helpers_pkg is
 
procedure sendSerial(data : integer; baud : in real; parity : in integer; stopbit : in real; bitnumber : in integer; baudError : in real; signal txd : inout std_logic);
procedure recvSerial( signal rxd : in std_logic; baud : in real; parity : in integer; stopbit : in real; bitnumber : in integer; baudError : in real; signal data : inout std_logic_vector(7 downto 0));
 
component regFileModel
port
(
16,3 → 20,41
end component;
 
end helpers_pkg;
 
package body helpers_pkg is
 
procedure sendSerial(data : integer; baud : in real; parity : in integer; stopbit : in real; bitnumber : in integer; baudError : in real; signal txd : inout std_logic) is
 
variable shiftreg : std_logic_vector(7 downto 0);
variable bitTime : time;
 
begin
bitTime := 1000 ms / (baud + baud * baudError / 100.0);
shiftreg := std_logic_vector(to_unsigned(data, shiftreg'length));
txd <= '0';
wait for bitTime;
for index in 0 to bitnumber loop
txd <= shiftreg(index);
wait for bitTime;
end loop;
txd <= '1';
wait for stopbit * bitTime;
end procedure;
 
procedure recvSerial( signal rxd : in std_logic; baud : in real; parity : in integer; stopbit : in real; bitnumber : in integer; baudError : in real; signal data : inout std_logic_vector(7 downto 0)) is
 
variable bitTime : time;
 
begin
bitTime := 1000 ms / (baud + baud * baudError / 100.0);
wait until (rxd = '0');
wait for bitTime / 2;
wait for bitTime;
for index in 0 to bitnumber loop
data <= rxd & data(7 downto 1);
wait for bitTime;
end loop;
wait for stopbit * bitTime;
end procedure;
 
end;
/trunk/vhdl/bench/helpers/regFileModel.vhd
4,7 → 4,7
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
 
entity regFileModel is
port ( -- global signals
33,7 → 33,7
end loop;
elsif (rising_edge(clk)) then
if (intWrite = '1') then
regFile(conv_integer(intAddress)) <= intWrData;
regFile(to_integer(unsigned(intAddress))) <= intWrData;
end if;
end if;
end process;
44,7 → 44,7
intRdData <= (others => '0');
elsif (rising_edge(clk)) then
if (intRead = '1') then
intRdData <= regFile(conv_integer(intAddress));
intRdData <= regFile(to_integer(unsigned(intAddress)));
end if;
end if;
end process;
/trunk/vhdl/bench/uart2BusTop_bin_tb.vhd
6,9 → 6,7
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
 
library work;
use work.uart2BusTop_pkg.all;
/trunk/vhdl/bench/uart2BusTop_txt_tb.vhd
6,9 → 6,6
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
 
library work;
use work.uart2BusTop_pkg.all;
21,40 → 18,6
 
architecture behavior of uart2BusTop_txt_tb is
 
procedure sendSerial(data : integer; baud : in real; parity : in integer; stopbit : in real; bitnumber : in integer; baudError : in real; signal txd : inout std_logic) is
 
variable shiftreg : std_logic_vector(7 downto 0);
variable bitTime : time;
 
begin
bitTime := 1000 ms / (baud + baud * baudError / 100.0);
shiftreg := std_logic_vector(to_unsigned(data, shiftreg'length));
txd <= '0';
wait for bitTime;
for index in 0 to bitnumber loop
txd <= shiftreg(index);
wait for bitTime;
end loop;
txd <= '1';
wait for stopbit * bitTime;
end procedure;
 
procedure recvSerial( signal rxd : in std_logic; baud : in real; parity : in integer; stopbit : in real; bitnumber : in integer; baudError : in real; signal data : inout std_logic_vector(7 downto 0)) is
 
variable bitTime : time;
 
begin
bitTime := 1000 ms / (baud + baud * baudError / 100.0);
wait until (rxd = '0');
wait for bitTime / 2;
wait for bitTime;
for index in 0 to bitnumber loop
data <= rxd & data(7 downto 1);
wait for bitTime;
end loop;
wait for stopbit * bitTime;
end procedure;
 
-- Inputs
signal clr : std_logic := '0';
signal clk : std_logic := '0';
/trunk/vhdl/rtl/baudGen.vhd
11,7 → 11,7
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
 
entity baudGen is
port ( clr : in std_logic; -- global reset input
37,10 → 37,10
ce16 <= '0';
elsif (rising_edge(clk)) then
if (counter >= baudLimit) then
counter <= counter - baudLimit;
counter <= std_logic_vector(unsigned(counter) - unsigned(baudLimit));
ce16 <= '1';
else
counter <= counter + baudFreq;
counter <= std_logic_vector(unsigned(counter) + unsigned(baudFreq));
ce16 <= '0';
end if;
end if;
/trunk/vhdl/rtl/uartRx.vhd
4,7 → 4,7
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.ALL;
 
entity uartRx is
port ( clr : in std_logic; -- global reset input
45,7 → 45,7
elsif (rising_edge(clk)) then
if (ce16 = '1') then
if ((rxBusy = '1') or (inSync(1) = '0')) then
count16 <= count16 + 1;
count16 <= std_logic_vector(unsigned(count16) + 1);
else
count16 <= (others => '0');
end if;
74,7 → 74,7
if (rxBusy = '0') then
bitCount <= (others => '0');
elsif ((rxBusy = '1') and (ce1Mid = '1')) then
bitCount <= bitCount + 1;
bitCount <= std_logic_vector(unsigned(bitCount) + 1);
end if;
end if;
end process;
/trunk/vhdl/rtl/uartTx.vhd
4,7 → 4,7
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
 
entity uartTx is
port ( clr : in std_logic; -- global reset input
32,7 → 32,7
count16 <= (others => '0');
elsif (rising_edge(clk)) then
if ((iTxBusy = '1') and (ce16 = '1')) then
count16 <= count16 + 1;
count16 <= std_logic_vector(unsigned(count16) + 1);
elsif (iTxBusy = '0') then
count16 <= (others => '0');
end if;
58,7 → 58,7
bitCount <= (others => '0');
elsif (rising_edge(clk)) then
if ((iTxBusy = '1') and (ce1 = '1')) then
bitCount <= bitCount + 1;
bitCount <= std_logic_vector(unsigned(bitCount) + 1);
elsif (iTxBusy = '0') then
bitCount <= (others => '0');
end if;
/trunk/vhdl/rtl/uartParser.vhd
4,7 → 4,7
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.ALL;
 
entity uartParser is
generic ( -- parameters
351,7 → 351,7
elsif (((mainSm = mainBinData) and (binWriteOp = '1') and (newRxData = '1')) or ((binReadOp = '1') and (txEndP = '1'))) then
-- byte counter is updated on every new data received in write operations and for every
-- byte transmitted for read operations.
binByteCount <= binByteCount - 1;
binByteCount <= std_logic_vector(unsigned(binByteCount) - 1);
end if;
end if;
end process;
411,7 → 411,7
iIntAddress <= addrParam(AW - 1 downto 0);
elsif ((addrAutoInc = '1') and (((binReadOp = '1') and (txEndP = '1') and (binLastByte = '0')) or ((binWriteOp = '1') and (iIntWrite = '1')))) then
-- address is incremented on every read or write if enabled
iIntAddress <= iIntAddress + 1;
iIntAddress <= std_logic_vector(unsigned(iIntAddress) + 1);
end if;
end if;
end process;
/trunk/vhdl/sim/ghdl/uart2BusTop_bin_tb.sav
0,0 → 1,43
[*]
[*] GTKWave Analyzer v3.3.45 (w)1999-2012 BSI
[*] Mon Jul 22 09:26:49 2013
[*]
[dumpfile] "/dev/shm/uart2BusTop_bin_tb.fst"
[dumpfile_mtime] "Mon Jul 22 09:26:41 2013"
[dumpfile_size] 146929
[savefile] "/run/media/smuller/DATA/Projects/uart2bus/sim/ghdl/uart2BusTop_bin_tb.sav"
[timestart] 0
[size] 1680 974
[pos] -1 -1
*-38.645287 83900000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 210
[signals_width] 255
[sst_expanded] 1
[sst_vpaned_height] 286
@28
uut.clr
uut.clk
@200
-Asynchronous serial link
@28
uut.serin
uut.serout
@200
-Internal bus
@22
intaddress[7:0]
intrddata[7:0]
@28
intread
@22
intwrdata[7:0]
@28
intwrite
@200
-Other internal signals
@28
newrxdata
@23
recvdata[7:0]
[pattern_trace] 1
[pattern_trace] 0
trunk/vhdl/sim/ghdl/uart2BusTop_bin_tb.sav Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/vhdl/sim/ghdl/shell_tools.sh =================================================================== --- trunk/vhdl/sim/ghdl/shell_tools.sh (nonexistent) +++ trunk/vhdl/sim/ghdl/shell_tools.sh (revision 13) @@ -0,0 +1,16 @@ +# !/bin/bash + +RED='\e[1;31m' +GREEN='\e[1;32m' +YELLOW='\e[1;33m' +NORMAL='\e[0;m' + +run() +{ + echo -e "${GREEN}'$*'${NORMAL}" + $@ + if [ $? -ne 0 ] ; then + echo -e "${RED}Script stopped due to '$*' at error at '$( caller )'${NORMAL}" + exit 1 + fi +}
trunk/vhdl/sim/ghdl/shell_tools.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/vhdl/sim/ghdl/uart2BusTop_txt_tb.sav =================================================================== --- trunk/vhdl/sim/ghdl/uart2BusTop_txt_tb.sav (nonexistent) +++ trunk/vhdl/sim/ghdl/uart2BusTop_txt_tb.sav (revision 13) @@ -0,0 +1,43 @@ +[*] +[*] GTKWave Analyzer v3.3.45 (w)1999-2012 BSI +[*] Mon Jul 22 09:25:59 2013 +[*] +[dumpfile] "/dev/shm/uart2BusTop_txt_tb.fst" +[dumpfile_mtime] "Mon Jul 22 09:24:50 2013" +[dumpfile_size] 2827856 +[savefile] "/run/media/smuller/DATA/Projects/uart2bus/sim/ghdl/uart2BusTop_txt_tb.sav" +[timestart] 0 +[size] 1680 974 +[pos] -1 -1 +*-42.967213 83900000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 210 +[signals_width] 255 +[sst_expanded] 1 +[sst_vpaned_height] 286 +@28 +uut.clr +uut.clk +@200 +-Asynchronous serial link +@28 +uut.serin +uut.serout +@200 +-Internal bus +@22 +intaddress[7:0] +intrddata[7:0] +@28 +intread +@22 +intwrdata[7:0] +@28 +intwrite +@200 +-Other internal signals +@28 +newrxdata +@23 +recvdata[7:0] +[pattern_trace] 1 +[pattern_trace] 0
trunk/vhdl/sim/ghdl/uart2BusTop_txt_tb.sav Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/vhdl/sim/ghdl/uart2bus_bin_build.sh =================================================================== --- trunk/vhdl/sim/ghdl/uart2bus_bin_build.sh (nonexistent) +++ trunk/vhdl/sim/ghdl/uart2bus_bin_build.sh (revision 13) @@ -0,0 +1,32 @@ +# !/bin/bash +source ./shell_tools.sh + +TEST_BENCH=uart2BusTop_bin_tb +SIM_TIME=2500us + +TEMP_DIR=/dev/shm +VCD=${TEMP_DIR}/${TEST_BENCH}.vcd +FST=${TEMP_DIR}/${TEST_BENCH}.fst +SAV=${TEST_BENCH}.sav + +run ghdl -a --workdir="${TEMP_DIR}" "../../rtl/uart2BusTop_pkg.vhd" +run ghdl -a --workdir="${TEMP_DIR}" "../../rtl/baudGen.vhd" +run ghdl -a --workdir="${TEMP_DIR}" "../../rtl/uart2BusTop.vhd" +run ghdl -a --workdir="${TEMP_DIR}" "../../rtl/uartParser.vhd" +run ghdl -a --workdir="${TEMP_DIR}" "../../rtl/uartRx.vhd" +run ghdl -a --workdir="${TEMP_DIR}" "../../rtl/uartTop.vhd" +run ghdl -a --workdir="${TEMP_DIR}" "../../rtl/uartTx.vhd" + +run ghdl -a --workdir="${TEMP_DIR}" "../../bench/helpers/helpers_pkg.vhd" +run ghdl -a --workdir="${TEMP_DIR}" "../../bench/helpers/regFileModel.vhd" +run ghdl -a --workdir="${TEMP_DIR}" "../../bench/uart2BusTop_bin_tb.vhd" + +run ghdl -e --workdir=${TEMP_DIR} ${TEST_BENCH} +run ghdl -r --workdir=${TEMP_DIR} ${TEST_BENCH} --vcd=${VCD} --stop-time=${SIM_TIME} + +(cd ${TEMP_DIR} ; run ghdl --clean) + +run vcd2fst ${VCD} ${FST} +rm ${VCD} + +gtkwave -a ${SAV} ${FST}
trunk/vhdl/sim/ghdl/uart2bus_bin_build.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/vhdl/sim/ghdl/uart2bus_txt_build.sh =================================================================== --- trunk/vhdl/sim/ghdl/uart2bus_txt_build.sh (nonexistent) +++ trunk/vhdl/sim/ghdl/uart2bus_txt_build.sh (revision 13) @@ -0,0 +1,32 @@ +# !/bin/bash +source ./shell_tools.sh + +TEST_BENCH=uart2BusTop_txt_tb +SIM_TIME=50ms + +TEMP_DIR=/dev/shm +VCD=${TEMP_DIR}/${TEST_BENCH}.vcd +FST=${TEMP_DIR}/${TEST_BENCH}.fst +SAV=${TEST_BENCH}.sav + +run ghdl -a --workdir="${TEMP_DIR}" "../../rtl/uart2BusTop_pkg.vhd" +run ghdl -a --workdir="${TEMP_DIR}" "../../rtl/baudGen.vhd" +run ghdl -a --workdir="${TEMP_DIR}" "../../rtl/uart2BusTop.vhd" +run ghdl -a --workdir="${TEMP_DIR}" "../../rtl/uartParser.vhd" +run ghdl -a --workdir="${TEMP_DIR}" "../../rtl/uartRx.vhd" +run ghdl -a --workdir="${TEMP_DIR}" "../../rtl/uartTop.vhd" +run ghdl -a --workdir="${TEMP_DIR}" "../../rtl/uartTx.vhd" + +run ghdl -a --workdir="${TEMP_DIR}" "../../bench/helpers/helpers_pkg.vhd" +run ghdl -a --workdir="${TEMP_DIR}" "../../bench/helpers/regFileModel.vhd" +run ghdl -a --workdir="${TEMP_DIR}" "../../bench/uart2BusTop_txt_tb.vhd" + +run ghdl -e --workdir=${TEMP_DIR} ${TEST_BENCH} +run ghdl -r --workdir=${TEMP_DIR} ${TEST_BENCH} --vcd=${VCD} --stop-time=${SIM_TIME} + +(cd ${TEMP_DIR} ; run ghdl --clean) + +run vcd2fst ${VCD} ${FST} +rm ${VCD} + +gtkwave -a ${SAV} ${FST}
trunk/vhdl/sim/ghdl/uart2bus_txt_build.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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