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https://opencores.org/ocsvn/uart2bus_testbench/uart2bus_testbench/trunk
Subversion Repositories uart2bus_testbench
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/trunk/buad_rate_calculation/buad_rate_calculations/bin/Debug/buad_rate_calculations.exe
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trunk/buad_rate_calculation/buad_rate_calculations/bin/Debug/buad_rate_calculations.exe
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Index: trunk/buad_rate_calculation/buad_rate_calculations/buad_rate_calculations.cbp
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--- trunk/buad_rate_calculation/buad_rate_calculations/buad_rate_calculations.cbp (revision 2)
+++ trunk/buad_rate_calculation/buad_rate_calculations/buad_rate_calculations.cbp (nonexistent)
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trunk/buad_rate_calculation/buad_rate_calculations/buad_rate_calculations.cbp
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Index: trunk/buad_rate_calculation/buad_rate_calculations/buad_rate_calculations.layout
===================================================================
--- trunk/buad_rate_calculation/buad_rate_calculations/buad_rate_calculations.layout (revision 2)
+++ trunk/buad_rate_calculation/buad_rate_calculations/buad_rate_calculations.layout (nonexistent)
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trunk/buad_rate_calculation/buad_rate_calculations/buad_rate_calculations.layout
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Index: trunk/buad_rate_calculation/buad_rate_calculations/buad_rate_calculations.depend
===================================================================
--- trunk/buad_rate_calculation/buad_rate_calculations/buad_rate_calculations.depend (revision 2)
+++ trunk/buad_rate_calculation/buad_rate_calculations/buad_rate_calculations.depend (nonexistent)
@@ -1,4 +0,0 @@
-# depslib dependency file v1.0
-1452501572 source:c:\users\pc2\uart2bus\uvm_testbench\buad_rate_calculation\buad_rate_calculations\main.cpp
-
-
trunk/buad_rate_calculation/buad_rate_calculations/buad_rate_calculations.depend
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Index: trunk/buad_rate_calculation/buad_rate_calculations/main.cpp
===================================================================
--- trunk/buad_rate_calculation/buad_rate_calculations/main.cpp (revision 2)
+++ trunk/buad_rate_calculation/buad_rate_calculations/main.cpp (nonexistent)
@@ -1,47 +0,0 @@
-#include
-
-using namespace std;
-
-int gcd_calc (int x, int y);
-
-int main()
-{
- unsigned int gcd_result;
- unsigned int buad_rate,buad_freq,global_clock;
- cout << "enter buad rate" << endl;
- cin >> buad_rate ;
- cout << "enter global clock" << endl;
- cin >> global_clock ;
- gcd_result = gcd_calc(global_clock,(16*buad_rate));
- buad_freq = (16*buad_rate)/gcd_result;
- cout << "buad_freq = " << buad_freq << endl;
-
- return 0;
-}
-
-int gcd_calc(int x, int y)
-{
- int result =1;
- bool break_loop = false;
- int div;
- div =2;
- while (break_loop == false)
- {
- if ((x%div == 0) && (y%div ==0))
- {
- result = result*div;
- x=x/div;
- y=y/div;
- }
- else
- {
- div++;
- }
- if((div > x)|| (div > y))
- {
- break_loop = true;
- }
- }
- return result;
-}
-
trunk/buad_rate_calculation/buad_rate_calculations/main.cpp
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Index: trunk/svn-commit.tmp
===================================================================
--- trunk/svn-commit.tmp (revision 2)
+++ trunk/svn-commit.tmp (nonexistent)
@@ -1,64 +0,0 @@
-
---This line, and those below, will be ignored--
-
-A buad_rate_calculation
-A buad_rate_calculation/buad_rate_calculations
-A buad_rate_calculation/buad_rate_calculations/bin
-A buad_rate_calculation/buad_rate_calculations/bin/Debug
-AM buad_rate_calculation/buad_rate_calculations/bin/Debug/buad_rate_calculations.exe
-AM buad_rate_calculation/buad_rate_calculations/buad_rate_calculations.cbp
-AM buad_rate_calculation/buad_rate_calculations/buad_rate_calculations.depend
-AM buad_rate_calculation/buad_rate_calculations/buad_rate_calculations.layout
-AM buad_rate_calculation/buad_rate_calculations/main.cpp
-A buad_rate_calculation/buad_rate_calculations/obj
-A buad_rate_calculation/buad_rate_calculations/obj/Debug
-A doc
-AM doc/.~lock.uart2bus_verification_plan.odt#
-AM doc/UART to Bus Core Specifications.pdf
-AM doc/uart2bus_core.dia
-AM doc/uart2bus_core.jpeg
-AM doc/uart2bus_core.png
-AM doc/uart2bus_tb.dia
-AM doc/uart2bus_tb.jpeg
-AM doc/uart2bus_tb.png
-AM doc/uart2bus_tb.svg
-AM doc/uart2bus_verification_plan.docx
-AM doc/uart2bus_verification_plan.odt
-AM doc/uart2bus_verification_plan.pdf
-A rtl
-AM rtl/baud_gen.v
-AM rtl/uart2bus_top.v
-AM rtl/uart_parser.v
-AM rtl/uart_rx.v
-AM rtl/uart_top.v
-AM rtl/uart_tx.v
-A tb
-A tb/agent
-AM tb/agent/agent_pkg.sv
-A tb/agent/configuration
-AM tb/agent/configuration/uart_config.svh
-A tb/agent/driver
-AM tb/agent/driver/uart_driver.svh
-A tb/agent/monitor
-AM tb/agent/monitor/uart_monitor.svh
-A tb/agent/sequence
-AM tb/agent/sequence/uart_sequence.svh
-A tb/agent/transaction
-AM tb/agent/transaction/uart_transaction.svh
-AM tb/agent/uart_agent.svh
-A tb/analysis
-AM tb/analysis/uart_scoreboard.svh
-AM tb/defin_lib.svh
-AM tb/draft
-A tb/env
-AM tb/env/env_pkg.sv
-AM tb/env/uart_env.svh
-A tb/interfaces
-AM tb/interfaces/rf_interface.sv
-AM tb/interfaces/uart_arbiter.sv
-AM tb/interfaces/uart_interface.sv
-AM tb/run.do
-A tb/test
-AM tb/test/uart_test.svh
-AM tb/uart_pkg.sv
-AM tb/uart_top.sv
Index: trunk/rtl/baud_gen.v
===================================================================
--- trunk/rtl/baud_gen.v (revision 2)
+++ trunk/rtl/baud_gen.v (nonexistent)
@@ -1,56 +0,0 @@
-//---------------------------------------------------------------------------------------
-// baud rate generator for uart
-//
-// this module has been changed to receive the baud rate dividing counter from registers.
-// the two registers should be calculated as follows:
-// first register:
-// baud_freq = 16*baud_rate / gcd(global_clock_freq, 16*baud_rate)
-// second register:
-// baud_limit = (global_clock_freq / gcd(global_clock_freq, 16*baud_rate)) - baud_freq
-//
-//---------------------------------------------------------------------------------------
-
-module baud_gen
-(
- clock, reset,
- ce_16, baud_freq, baud_limit
-);
-//---------------------------------------------------------------------------------------
-// modules inputs and outputs
-input clock; // global clock input
-input reset; // global reset input
-output ce_16; // baud rate multiplyed by 16
-input [11:0] baud_freq; // baud rate setting registers - see header description
-input [15:0] baud_limit;
-
-// internal registers
-reg ce_16;
-reg [15:0] counter;
-//---------------------------------------------------------------------------------------
-// module implementation
-// baud divider counter
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- counter <= 16'b0;
- else if (counter >= baud_limit)
- counter <= counter - baud_limit;
- else
- counter <= counter + baud_freq;
-end
-
-// clock divider output
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- ce_16 <= 1'b0;
- else if (counter >= baud_limit)
- ce_16 <= 1'b1;
- else
- ce_16 <= 1'b0;
-end
-
-endmodule
-//---------------------------------------------------------------------------------------
-// Th.. Th.. Th.. Thats all folks !!!
-//---------------------------------------------------------------------------------------
trunk/rtl/baud_gen.v
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Index: trunk/rtl/uart_rx.v
===================================================================
--- trunk/rtl/uart_rx.v (revision 2)
+++ trunk/rtl/uart_rx.v (nonexistent)
@@ -1,116 +0,0 @@
-//---------------------------------------------------------------------------------------
-// uart receive module
-//
-//---------------------------------------------------------------------------------------
-
-module uart_rx
-(
- clock, reset,
- ce_16, ser_in,
- rx_data, new_rx_data
-);
-//---------------------------------------------------------------------------------------
-// modules inputs and outputs
-input clock; // global clock input
-input reset; // global reset input
-input ce_16; // baud rate multiplyed by 16 - generated by baud module
-input ser_in; // serial data input
-output [7:0] rx_data; // data byte received
-output new_rx_data; // signs that a new byte was received
-
-// internal wires
-wire ce_1; // clock enable at bit rate
-wire ce_1_mid; // clock enable at the middle of each bit - used to sample data
-
-// internal registers
-reg [7:0] rx_data;
-reg new_rx_data;
-reg [1:0] in_sync;
-reg rx_busy;
-reg [3:0] count16;
-reg [3:0] bit_count;
-reg [7:0] data_buf;
-//---------------------------------------------------------------------------------------
-// module implementation
-// input async input is sampled twice
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- in_sync <= 2'b11;
- else
- in_sync <= {in_sync[0], ser_in};
-end
-
-// a counter to count 16 pulses of ce_16 to generate the ce_1 and ce_1_mid pulses.
-// this counter is used to detect the start bit while the receiver is not receiving and
-// signs the sampling cycle during reception.
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- count16 <= 4'b0;
- else if (ce_16)
- begin
- if (rx_busy | (in_sync[1] == 1'b0))
- count16 <= count16 + 4'b1;
- else
- count16 <= 4'b0;
- end
-end
-
-// ce_1 pulse indicating expected end of current bit
-assign ce_1 = (count16 == 4'b1111) & ce_16;
-// ce_1_mid pulse indication the sampling clock cycle of the current data bit
-assign ce_1_mid = (count16 == 4'b0111) & ce_16;
-
-// receiving busy flag
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- rx_busy <= 1'b0;
- else if (~rx_busy & ce_1_mid)
- rx_busy <= 1'b1;
- else if (rx_busy & (bit_count == 4'h8) & ce_1_mid)
- rx_busy <= 1'b0;
-end
-
-// bit counter
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- bit_count <= 4'h0;
- else if (~rx_busy)
- bit_count <= 4'h0;
- else if (rx_busy & ce_1_mid)
- bit_count <= bit_count + 4'h1;
-end
-
-// data buffer shift register
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- data_buf <= 8'h0;
- else if (rx_busy & ce_1_mid)
- data_buf <= {in_sync[1], data_buf[7:1]};
-end
-
-// data output and flag
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- begin
- rx_data <= 8'h0;
- new_rx_data <= 1'b0;
- end
- else if (rx_busy & (bit_count == 4'h8) & ce_1)
- begin
- rx_data <= data_buf;
- new_rx_data <= 1'b1;
- end
- else
- new_rx_data <= 1'b0;
-end
-
-endmodule
-//---------------------------------------------------------------------------------------
-// Th.. Th.. Th.. Thats all folks !!!
-//---------------------------------------------------------------------------------------
trunk/rtl/uart_rx.v
Property changes :
Deleted: svn:executable
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\ No newline at end of property
Index: trunk/rtl/uart_tx.v
===================================================================
--- trunk/rtl/uart_tx.v (revision 2)
+++ trunk/rtl/uart_tx.v (nonexistent)
@@ -1,94 +0,0 @@
-//---------------------------------------------------------------------------------------
-// uart transmit module
-//
-//---------------------------------------------------------------------------------------
-
-module uart_tx
-(
- clock, reset,
- ce_16, tx_data, new_tx_data,
- ser_out, tx_busy
-);
-//---------------------------------------------------------------------------------------
-// modules inputs and outputs
-input clock; // global clock input
-input reset; // global reset input
-input ce_16; // baud rate multiplyed by 16 - generated by baud module
-input [7:0] tx_data; // data byte to transmit
-input new_tx_data; // asserted to indicate that there is a new data byte for transmission
-output ser_out; // serial data output
-output tx_busy; // signs that transmitter is busy
-
-// internal wires
-wire ce_1; // clock enable at bit rate
-
-// internal registers
-reg ser_out;
-reg tx_busy;
-reg [3:0] count16;
-reg [3:0] bit_count;
-reg [8:0] data_buf;
-//---------------------------------------------------------------------------------------
-// module implementation
-// a counter to count 16 pulses of ce_16 to generate the ce_1 pulse
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- count16 <= 4'b0;
- else if (tx_busy & ce_16)
- count16 <= count16 + 4'b1;
- else if (~tx_busy)
- count16 <= 4'b0;
-end
-
-// ce_1 pulse indicating output data bit should be updated
-assign ce_1 = (count16 == 4'b1111) & ce_16;
-
-// tx_busy flag
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- tx_busy <= 1'b0;
- else if (~tx_busy & new_tx_data)
- tx_busy <= 1'b1;
- else if (tx_busy & (bit_count == 4'h9) & ce_1)
- tx_busy <= 1'b0;
-end
-
-// output bit counter
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- bit_count <= 4'h0;
- else if (tx_busy & ce_1)
- bit_count <= bit_count + 4'h1;
- else if (~tx_busy)
- bit_count <= 4'h0;
-end
-
-// data shift register
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- data_buf <= 9'b0;
- else if (~tx_busy)
- data_buf <= {tx_data, 1'b0};
- else if (tx_busy & ce_1)
- data_buf <= {1'b1, data_buf[8:1]};
-end
-
-// output data bit
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- ser_out <= 1'b1;
- else if (tx_busy)
- ser_out <= data_buf[0];
- else
- ser_out <= 1'b1;
-end
-
-endmodule
-//---------------------------------------------------------------------------------------
-// Th.. Th.. Th.. Thats all folks !!!
-//---------------------------------------------------------------------------------------
trunk/rtl/uart_tx.v
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Index: trunk/rtl/uart_parser.v
===================================================================
--- trunk/rtl/uart_parser.v (revision 2)
+++ trunk/rtl/uart_parser.v (nonexistent)
@@ -1,667 +0,0 @@
-//---------------------------------------------------------------------------------------
-// uart parser module
-//
-//---------------------------------------------------------------------------------------
-
-module uart_parser
-(
- // global signals
- clock, reset,
- // transmit and receive internal interface signals from uart interface
- rx_data, new_rx_data,
- tx_data, new_tx_data, tx_busy,
- // internal bus to register file
- int_address, int_wr_data, int_write,
- int_rd_data, int_read,
- int_req, int_gnt
-);
-//---------------------------------------------------------------------------------------
-// parameters
-parameter AW = 8; // address bus width parameter
-
-// modules inputs and outputs
-input clock; // global clock input
-input reset; // global reset input
-output [7:0] tx_data; // data byte to transmit
-output new_tx_data; // asserted to indicate that there is a new data byte for
- // transmission
-input tx_busy; // signs that transmitter is busy
-input [7:0] rx_data; // data byte received
-input new_rx_data; // signs that a new byte was received
-output [AW-1:0] int_address; // address bus to register file
-output [7:0] int_wr_data; // write data to register file
-output int_write; // write control to register file
-output int_read; // read control to register file
-input [7:0] int_rd_data; // data read from register file
-output int_req; // bus access request signal
-input int_gnt; // bus access grant signal
-
-// registered outputs
-reg [7:0] tx_data;
-reg new_tx_data;
-reg [AW-1:0] int_address;
-reg [7:0] int_wr_data;
-reg write_req, read_req, int_write, int_read;
-
-// internal constants
-// define characters used by the parser
-`define CHAR_CR 8'h0d
-`define CHAR_LF 8'h0a
-`define CHAR_SPACE 8'h20
-`define CHAR_TAB 8'h09
-`define CHAR_COMMA 8'h2C
-`define CHAR_R_UP 8'h52
-`define CHAR_r_LO 8'h72
-`define CHAR_W_UP 8'h57
-`define CHAR_w_LO 8'h77
-`define CHAR_0 8'h30
-`define CHAR_1 8'h31
-`define CHAR_2 8'h32
-`define CHAR_3 8'h33
-`define CHAR_4 8'h34
-`define CHAR_5 8'h35
-`define CHAR_6 8'h36
-`define CHAR_7 8'h37
-`define CHAR_8 8'h38
-`define CHAR_9 8'h39
-`define CHAR_A_UP 8'h41
-`define CHAR_B_UP 8'h42
-`define CHAR_C_UP 8'h43
-`define CHAR_D_UP 8'h44
-`define CHAR_E_UP 8'h45
-`define CHAR_F_UP 8'h46
-`define CHAR_a_LO 8'h61
-`define CHAR_b_LO 8'h62
-`define CHAR_c_LO 8'h63
-`define CHAR_d_LO 8'h64
-`define CHAR_e_LO 8'h65
-`define CHAR_f_LO 8'h66
-
-// main (receive) state machine states
-`define MAIN_IDLE 4'b0000
-`define MAIN_WHITE1 4'b0001
-`define MAIN_DATA 4'b0010
-`define MAIN_WHITE2 4'b0011
-`define MAIN_ADDR 4'b0100
-`define MAIN_EOL 4'b0101
-// binary mode extension states
-`define MAIN_BIN_CMD 4'b1000
-`define MAIN_BIN_ADRH 4'b1001
-`define MAIN_BIN_ADRL 4'b1010
-`define MAIN_BIN_LEN 4'b1011
-`define MAIN_BIN_DATA 4'b1100
-
-// transmit state machine
-`define TX_IDLE 3'b000
-`define TX_HI_NIB 3'b001
-`define TX_LO_NIB 3'b100
-`define TX_CHAR_CR 3'b101
-`define TX_CHAR_LF 3'b110
-
-// binary extension mode commands - the command is indicated by bits 5:4 of the command byte
-`define BIN_CMD_NOP 2'b00
-`define BIN_CMD_READ 2'b01
-`define BIN_CMD_WRITE 2'b10
-
-// internal wires and registers
-reg [3:0] main_sm; // main state machine
-reg read_op; // read operation flag
-reg write_op; // write operation flag
-reg data_in_hex_range; // indicates that the received data is in the range of hex number
-reg [7:0] data_param; // operation data parameter
-reg [15:0] addr_param; // operation address parameter
-reg [3:0] data_nibble; // data nibble from received character
-reg read_done; // internally generated read done flag
-reg read_done_s; // sampled read done
-reg [7:0] read_data_s; // sampled read data
-reg [3:0] tx_nibble; // nibble value for transmission
-reg [7:0] tx_char; // transmit byte from nibble to character conversion
-reg [2:0] tx_sm; // transmit state machine
-reg s_tx_busy; // sampled tx_busy for falling edge detection
-reg bin_read_op; // binary mode read operation flag
-reg bin_write_op; // binary mode write operation flag
-reg addr_auto_inc; // address auto increment mode
-reg send_stat_flag; // send status flag
-reg [7:0] bin_byte_count; // binary mode byte counter
-wire bin_last_byte; // last byte flag indicates that the current byte in the command is the last
-wire tx_end_p; // transmission end pulse
-
-//---------------------------------------------------------------------------------------
-// module implementation
-// main state machine
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- main_sm <= `MAIN_IDLE;
- else if (new_rx_data)
- begin
- case (main_sm)
- // wait for a read ('r') or write ('w') command
- // binary extension - an all zeros byte enabled binary commands
- `MAIN_IDLE:
- // check received character
- if (rx_data == 8'h0)
- // an all zeros received byte enters binary mode
- main_sm <= `MAIN_BIN_CMD;
- else if ((rx_data == `CHAR_r_LO) | (rx_data == `CHAR_R_UP))
- // on read wait to receive only address field
- main_sm <= `MAIN_WHITE2;
- else if ((rx_data == `CHAR_w_LO) | (rx_data == `CHAR_W_UP))
- // on write wait to receive data and address
- main_sm <= `MAIN_WHITE1;
- else if ((rx_data == `CHAR_CR) | (rx_data == `CHAR_LF))
- // on new line sta in idle
- main_sm <= `MAIN_IDLE;
- else
- // any other character wait to end of line (EOL)
- main_sm <= `MAIN_EOL;
-
- // wait for white spaces till first data nibble
- `MAIN_WHITE1:
- // wait in this case until any white space character is received. in any
- // valid character for data value switch to data state. a new line or carriage
- // return should reset the state machine to idle.
- // any other character transitions the state machine to wait for EOL.
- if ((rx_data == `CHAR_SPACE) | (rx_data == `CHAR_TAB))
- main_sm <= `MAIN_WHITE1;
- else if (data_in_hex_range)
- main_sm <= `MAIN_DATA;
- else if ((rx_data == `CHAR_CR) | (rx_data == `CHAR_LF))
- main_sm <= `MAIN_IDLE;
- else
- main_sm <= `MAIN_EOL;
-
- // receive data field
- `MAIN_DATA:
- // wait while data in hex range. white space transition to wait white 2 state.
- // CR and LF resets the state machine. any other value cause state machine to
- // wait til end of line.
- if (data_in_hex_range)
- main_sm <= `MAIN_DATA;
- else if ((rx_data == `CHAR_SPACE) | (rx_data == `CHAR_TAB))
- main_sm <= `MAIN_WHITE2;
- else if ((rx_data == `CHAR_CR) | (rx_data == `CHAR_LF))
- main_sm <= `MAIN_IDLE;
- else
- main_sm <= `MAIN_EOL;
-
- // wait for white spaces till first address nibble
- `MAIN_WHITE2:
- // similar to MAIN_WHITE1
- if ((rx_data == `CHAR_SPACE) | (rx_data == `CHAR_TAB))
- main_sm <= `MAIN_WHITE2;
- else if (data_in_hex_range)
- main_sm <= `MAIN_ADDR;
- else if ((rx_data == `CHAR_CR) | (rx_data == `CHAR_LF))
- main_sm <= `MAIN_IDLE;
- else
- main_sm <= `MAIN_EOL;
-
- // receive address field
- `MAIN_ADDR:
- // similar to MAIN_DATA
- if (data_in_hex_range)
- main_sm <= `MAIN_ADDR;
- else if ((rx_data == `CHAR_CR) | (rx_data == `CHAR_LF))
- main_sm <= `MAIN_IDLE;
- else
- main_sm <= `MAIN_EOL;
-
- // wait to EOL
- `MAIN_EOL:
- // wait for CR or LF to move back to idle
- if ((rx_data == `CHAR_CR) | (rx_data == `CHAR_LF))
- main_sm <= `MAIN_IDLE;
-
- // binary extension
- // wait for command - one byte
- `MAIN_BIN_CMD:
- // check if command is a NOP command
- if (rx_data[5:4] == `BIN_CMD_NOP)
- // if NOP command then switch back to idle state
- main_sm <= `MAIN_IDLE;
- else
- // not a NOP command, continue receiving parameters
- main_sm <= `MAIN_BIN_ADRH;
-
- // wait for address parameter - two bytes
- // high address byte
- `MAIN_BIN_ADRH:
- // switch to next state
- main_sm <= `MAIN_BIN_ADRL;
-
- // low address byte
- `MAIN_BIN_ADRL:
- // switch to next state
- main_sm <= `MAIN_BIN_LEN;
-
- // wait for length parameter - one byte
- `MAIN_BIN_LEN:
- // check if write command else command reception ended
- if (bin_write_op)
- // wait for write data
- main_sm <= `MAIN_BIN_DATA;
- else
- // command reception has ended
- main_sm <= `MAIN_IDLE;
-
- // on write commands wait for data till end of buffer as specified by length parameter
- `MAIN_BIN_DATA:
- // if this is the last data byte then return to idle
- if (bin_last_byte)
- main_sm <= `MAIN_IDLE;
-
- // go to idle
- default:
- main_sm <= `MAIN_IDLE;
- endcase
- end
-end
-
-// indicates that the received data is in the range of hex number
-always @ (rx_data)
-begin
- if (((rx_data >= `CHAR_0 ) && (rx_data <= `CHAR_9 )) ||
- ((rx_data >= `CHAR_A_UP) && (rx_data <= `CHAR_F_UP)) ||
- ((rx_data >= `CHAR_a_LO) && (rx_data <= `CHAR_f_LO)))
- data_in_hex_range <= 1'b1;
- else
- data_in_hex_range <= 1'b0;
-end
-
-// read operation flag
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- read_op <= 1'b0;
- else if ((main_sm == `MAIN_IDLE) && new_rx_data)
- begin
- // the read operation flag is set when a read command is received in idle state and cleared
- // if any other character is received during that state.
- if ((rx_data == `CHAR_r_LO) | (rx_data == `CHAR_R_UP))
- read_op <= 1'b1;
- else
- read_op <= 1'b0;
- end
-end
-
-// write operation flag
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- write_op <= 1'b0;
- else if ((main_sm == `MAIN_IDLE) & new_rx_data)
- begin
- // the write operation flag is set when a write command is received in idle state and cleared
- // if any other character is received during that state.
- if ((rx_data == `CHAR_w_LO) | (rx_data == `CHAR_W_UP))
- write_op <= 1'b1;
- else
- write_op <= 1'b0;
- end
-end
-
-// binary mode read operation flag
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- bin_read_op <= 1'b0;
- else if ((main_sm == `MAIN_BIN_CMD) && new_rx_data && (rx_data[5:4] == `BIN_CMD_READ))
- // read command is started on reception of a read command
- bin_read_op <= 1'b1;
- else if (bin_read_op && tx_end_p && bin_last_byte)
- // read command ends on transmission of the last byte read
- bin_read_op <= 1'b0;
-end
-
-// binary mode write operation flag
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- bin_write_op <= 1'b0;
- else if ((main_sm == `MAIN_BIN_CMD) && new_rx_data && (rx_data[5:4] == `BIN_CMD_WRITE))
- // write command is started on reception of a write command
- bin_write_op <= 1'b1;
- else if ((main_sm == `MAIN_BIN_DATA) && new_rx_data && bin_last_byte)
- bin_write_op <= 1'b0;
-end
-
-// send status flag - used only in binary extension mode
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- send_stat_flag <= 1'b0;
- else if ((main_sm == `MAIN_BIN_CMD) && new_rx_data)
- begin
- // check if a status byte should be sent at the end of the command
- if (rx_data[0] == 1'b1)
- send_stat_flag <= 1'b1;
- else
- send_stat_flag <= 1'b0;
- end
-end
-
-// address auto increment - used only in binary extension mode
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- addr_auto_inc <= 1'b0;
- else if ((main_sm == `MAIN_BIN_CMD) && new_rx_data)
- begin
- // check if address should be automatically incremented or not.
- // Note that when rx_data[1] is set, address auto increment is disabled.
- if (rx_data[1] == 1'b0)
- addr_auto_inc <= 1'b1;
- else
- addr_auto_inc <= 1'b0;
- end
-end
-
-// operation data parameter
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- data_param <= 8'h0;
- else if ((main_sm == `MAIN_WHITE1) & new_rx_data & data_in_hex_range)
- data_param <= {4'h0, data_nibble};
- else if ((main_sm == `MAIN_DATA) & new_rx_data & data_in_hex_range)
- data_param <= {data_param[3:0], data_nibble};
-end
-
-// operation address parameter
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- addr_param <= 0;
- else if ((main_sm == `MAIN_WHITE2) & new_rx_data & data_in_hex_range)
- addr_param <= {12'b0, data_nibble};
- else if ((main_sm == `MAIN_ADDR) & new_rx_data & data_in_hex_range)
- addr_param <= {addr_param[11:0], data_nibble};
- // binary extension
- else if (main_sm == `MAIN_BIN_ADRH)
- addr_param[15:8] <= rx_data;
- else if (main_sm == `MAIN_BIN_ADRL)
- addr_param[7:0] <= rx_data;
-end
-
-// binary mode command byte counter is loaded with the length parameter and counts down to zero.
-// NOTE: a value of zero for the length parameter indicates a command of 256 bytes.
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- bin_byte_count <= 8'b0;
- else if ((main_sm == `MAIN_BIN_LEN) && new_rx_data)
- bin_byte_count <= rx_data;
- else if ((bin_write_op && (main_sm == `MAIN_BIN_DATA) && new_rx_data) ||
- (bin_read_op && tx_end_p))
- // byte counter is updated on every new data received in write operations and for every
- // byte transmitted for read operations.
- bin_byte_count <= bin_byte_count - 1;
-end
-// last byte in command flag
-assign bin_last_byte = (bin_byte_count == 8'h01) ? 1'b1 : 1'b0;
-
-// internal write control and data
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- begin
- write_req <= 1'b0;
- int_write <= 1'b0;
- int_wr_data <= 0;
- end
- else if (write_op && (main_sm == `MAIN_ADDR) && new_rx_data && !data_in_hex_range)
- begin
- write_req <= 1'b1;
- int_wr_data <= data_param;
- end
- // binary extension mode
- else if (bin_write_op && (main_sm == `MAIN_BIN_DATA) && new_rx_data)
- begin
- write_req <= 1'b1;
- int_wr_data <= rx_data;
- end
- else if (int_gnt && write_req)
- begin
- // set internal bus write and clear the write request flag
- int_write <= 1'b1;
- write_req <= 1'b0;
- end
- else
- int_write <= 1'b0;
-end
-
-// internal read control
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- begin
- int_read <= 1'b0;
- read_req <= 1'b0;
- end
- else if (read_op && (main_sm == `MAIN_ADDR) && new_rx_data && !data_in_hex_range)
- read_req <= 1'b1;
- // binary extension
- else if (bin_read_op && (main_sm == `MAIN_BIN_LEN) && new_rx_data)
- // the first read request is issued on reception of the length byte
- read_req <= 1'b1;
- else if (bin_read_op && tx_end_p && !bin_last_byte)
- // the next read requests are issued after the previous read value was transmitted and
- // this is not the last byte to be read.
- read_req <= 1'b1;
- else if (int_gnt && read_req)
- begin
- // set internal bus read and clear the read request flag
- int_read <= 1'b1;
- read_req <= 1'b0;
- end
- else
- int_read <= 1'b0;
-end
-
-// external request signal is active on read or write request
-assign int_req = write_req | read_req;
-
-// internal address
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- int_address <= 0;
- else if ((main_sm == `MAIN_ADDR) && new_rx_data && !data_in_hex_range)
- int_address <= addr_param[AW-1:0];
- // binary extension
- else if ((main_sm == `MAIN_BIN_LEN) && new_rx_data)
- // sample address parameter on reception of length byte
- int_address <= addr_param[AW-1:0];
- else if (addr_auto_inc &&
- ((bin_read_op && tx_end_p && !bin_last_byte) ||
- (bin_write_op && int_write)))
- // address is incremented on every read or write if enabled
- int_address <= int_address + 1;
-end
-
-// read done flag and sampled data read
-always @ (posedge clock or posedge reset)
-begin
- if (reset) begin
- read_done <= 1'b0;
- read_done_s <= 1'b0;
- read_data_s <= 8'h0;
- end
- else
- begin
- // read done flag
- if (int_read)
- read_done <= 1'b1;
- else
- read_done <= 1'b0;
-
- // sampled read done
- read_done_s <= read_done;
-
- // sampled data read
- if (read_done)
- read_data_s <= int_rd_data;
- end
-end
-
-// transmit state machine and control
-always @ (posedge clock or posedge reset)
-begin
- if (reset) begin
- tx_sm <= `TX_IDLE;
- tx_data <= 8'h0;
- new_tx_data <= 1'b0;
- end
- else
- case (tx_sm)
- // wait for read done indication
- `TX_IDLE:
- // on end of every read operation check how the data read should be transmitted
- // according to read type: ascii or binary.
- if (read_done_s)
- // on binary mode read transmit byte value
- if (bin_read_op)
- begin
- // note that there is no need to change state
- tx_data <= read_data_s;
- new_tx_data <= 1'b1;
- end
- else
- begin
- tx_sm <= `TX_HI_NIB;
- tx_data <= tx_char;
- new_tx_data <= 1'b1;
- end
- // check if status byte should be transmitted
- else if ((send_stat_flag && bin_read_op && tx_end_p && bin_last_byte) || // end of read command
- (send_stat_flag && bin_write_op && new_rx_data && bin_last_byte) || // end of write command
- ((main_sm == `MAIN_BIN_CMD) && new_rx_data && (rx_data[5:4] == `BIN_CMD_NOP))) // NOP
- begin
- // send status byte - currently a constant
- tx_data <= 8'h5a;
- new_tx_data <= 1'b1;
- end
- else
- new_tx_data <= 1'b0;
-
- // wait for transmit to end
- `TX_HI_NIB:
- if (tx_end_p)
- begin
- tx_sm <= `TX_LO_NIB;
- tx_data <= tx_char;
- new_tx_data <= 1'b1;
- end
- else
- new_tx_data <= 1'b0;
-
- // wait for transmit to end
- `TX_LO_NIB:
- if (tx_end_p)
- begin
- tx_sm <= `TX_CHAR_CR;
- tx_data <= `CHAR_CR;
- new_tx_data <= 1'b1;
- end
- else
- new_tx_data <= 1'b0;
-
- // wait for transmit to end
- `TX_CHAR_CR:
- if (tx_end_p)
- begin
- tx_sm <= `TX_CHAR_LF;
- tx_data <= `CHAR_LF;
- new_tx_data <= 1'b1;
- end
- else
- new_tx_data <= 1'b0;
-
- // wait for transmit to end
- `TX_CHAR_LF:
- begin
- if (tx_end_p)
- tx_sm <= `TX_IDLE;
- // clear tx new data flag
- new_tx_data <= 1'b0;
- end
-
- // return to idle
- default:
- tx_sm <= `TX_IDLE;
- endcase
-end
-
-// select the nibble to the nibble to character conversion
-always @ (tx_sm or read_data_s)
-begin
- case (tx_sm)
- `TX_IDLE: tx_nibble = read_data_s[7:4];
- `TX_HI_NIB: tx_nibble = read_data_s[3:0];
- default: tx_nibble = read_data_s[7:4];
- endcase
-end
-
-// sampled tx_busy
-always @ (posedge clock or posedge reset)
-begin
- if (reset)
- s_tx_busy <= 1'b0;
- else
- s_tx_busy <= tx_busy;
-end
-// tx end pulse
-assign tx_end_p = ~tx_busy & s_tx_busy;
-
-// character to nibble conversion
-always @ (rx_data)
-begin
- case (rx_data)
- `CHAR_0: data_nibble = 4'h0;
- `CHAR_1: data_nibble = 4'h1;
- `CHAR_2: data_nibble = 4'h2;
- `CHAR_3: data_nibble = 4'h3;
- `CHAR_4: data_nibble = 4'h4;
- `CHAR_5: data_nibble = 4'h5;
- `CHAR_6: data_nibble = 4'h6;
- `CHAR_7: data_nibble = 4'h7;
- `CHAR_8: data_nibble = 4'h8;
- `CHAR_9: data_nibble = 4'h9;
- `CHAR_A_UP, `CHAR_a_LO: data_nibble = 4'ha;
- `CHAR_B_UP, `CHAR_b_LO: data_nibble = 4'hb;
- `CHAR_C_UP, `CHAR_c_LO: data_nibble = 4'hc;
- `CHAR_D_UP, `CHAR_d_LO: data_nibble = 4'hd;
- `CHAR_E_UP, `CHAR_e_LO: data_nibble = 4'he;
- `CHAR_F_UP, `CHAR_f_LO: data_nibble = 4'hf;
- default: data_nibble = 4'hf;
- endcase
-end
-
-// nibble to character conversion
-always @ (tx_nibble)
-begin
- case (tx_nibble)
- 4'h0: tx_char = `CHAR_0;
- 4'h1: tx_char = `CHAR_1;
- 4'h2: tx_char = `CHAR_2;
- 4'h3: tx_char = `CHAR_3;
- 4'h4: tx_char = `CHAR_4;
- 4'h5: tx_char = `CHAR_5;
- 4'h6: tx_char = `CHAR_6;
- 4'h7: tx_char = `CHAR_7;
- 4'h8: tx_char = `CHAR_8;
- 4'h9: tx_char = `CHAR_9;
- 4'ha: tx_char = `CHAR_A_UP;
- 4'hb: tx_char = `CHAR_B_UP;
- 4'hc: tx_char = `CHAR_C_UP;
- 4'hd: tx_char = `CHAR_D_UP;
- 4'he: tx_char = `CHAR_E_UP;
- default: tx_char = `CHAR_F_UP;
- endcase
-end
-
-endmodule
-//---------------------------------------------------------------------------------------
-// Th.. Th.. Th.. Thats all folks !!!
-//---------------------------------------------------------------------------------------
trunk/rtl/uart_parser.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/rtl/uart2bus_top.v
===================================================================
--- trunk/rtl/uart2bus_top.v (revision 2)
+++ trunk/rtl/uart2bus_top.v (nonexistent)
@@ -1,83 +0,0 @@
-//---------------------------------------------------------------------------------------
-// uart to internal bus top module
-//
-//---------------------------------------------------------------------------------------
-
-module uart2bus_top
-(
- // global signals
- clock, reset,
- // uart serial signals
- ser_in, ser_out,
- // internal bus to register file
- int_address, int_wr_data, int_write,
- int_rd_data, int_read,
- int_req, int_gnt
-);
-//---------------------------------------------------------------------------------------
-// modules inputs and outputs
-input clock; // global clock input
-input reset; // global reset input
-input ser_in; // serial data input
-output ser_out; // serial data output
-output [15:0] int_address; // address bus to register file
-output [7:0] int_wr_data; // write data to register file
-output int_write; // write control to register file
-output int_read; // read control to register file
-input [7:0] int_rd_data; // data read from register file
-output int_req; // bus access request signal
-input int_gnt; // bus access grant signal
-
-// baud rate configuration, see baud_gen.v for more details.
-// baud rate generator parameters for 115200 baud on 40MHz clock
-`define D_BAUD_FREQ 12'h90
-`define D_BAUD_LIMIT 16'h0ba5
-// baud rate generator parameters for 115200 baud on 44MHz clock
-// `define D_BAUD_FREQ 12'd23
-// `define D_BAUD_LIMIT 16'd527
-// baud rate generator parameters for 9600 baud on 66MHz clock
-//`define D_BAUD_FREQ 12'h10
-//`define D_BAUD_LIMIT 16'h1ACB
-
-// internal wires
-wire [7:0] tx_data; // data byte to transmit
-wire new_tx_data; // asserted to indicate that there is a new data byte for transmission
-wire tx_busy; // signs that transmitter is busy
-wire [7:0] rx_data; // data byte received
-wire new_rx_data; // signs that a new byte was received
-wire [11:0] baud_freq;
-wire [15:0] baud_limit;
-wire baud_clk;
-
-//---------------------------------------------------------------------------------------
-// module implementation
-// uart top module instance
-uart_top uart1
-(
- .clock(clock), .reset(reset),
- .ser_in(ser_in), .ser_out(ser_out),
- .rx_data(rx_data), .new_rx_data(new_rx_data),
- .tx_data(tx_data), .new_tx_data(new_tx_data), .tx_busy(tx_busy),
- .baud_freq(baud_freq), .baud_limit(baud_limit),
- .baud_clk(baud_clk)
-);
-
-// assign baud rate default values
-assign baud_freq = `D_BAUD_FREQ;
-assign baud_limit = `D_BAUD_LIMIT;
-
-// uart parser instance
-uart_parser #(16) uart_parser1
-(
- .clock(clock), .reset(reset),
- .rx_data(rx_data), .new_rx_data(new_rx_data),
- .tx_data(tx_data), .new_tx_data(new_tx_data), .tx_busy(tx_busy),
- .int_address(int_address), .int_wr_data(int_wr_data), .int_write(int_write),
- .int_rd_data(int_rd_data), .int_read(int_read),
- .int_req(int_req), .int_gnt(int_gnt)
-);
-
-endmodule
-//---------------------------------------------------------------------------------------
-// Th.. Th.. Th.. Thats all folks !!!
-//---------------------------------------------------------------------------------------
trunk/rtl/uart2bus_top.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/rtl/uart_top.v
===================================================================
--- trunk/rtl/uart_top.v (revision 2)
+++ trunk/rtl/uart_top.v (nonexistent)
@@ -1,66 +0,0 @@
-//---------------------------------------------------------------------------------------
-// uart top level module
-//
-//---------------------------------------------------------------------------------------
-
-module uart_top
-(
- // global signals
- clock, reset,
- // uart serial signals
- ser_in, ser_out,
- // transmit and receive internal interface signals
- rx_data, new_rx_data,
- tx_data, new_tx_data, tx_busy,
- // baud rate configuration register - see baud_gen.v for details
- baud_freq, baud_limit,
- baud_clk
-);
-//---------------------------------------------------------------------------------------
-// modules inputs and outputs
-input clock; // global clock input
-input reset; // global reset input
-input ser_in; // serial data input
-output ser_out; // serial data output
-input [7:0] tx_data; // data byte to transmit
-input new_tx_data; // asserted to indicate that there is a new data byte for transmission
-output tx_busy; // signs that transmitter is busy
-output [7:0] rx_data; // data byte received
-output new_rx_data; // signs that a new byte was received
-input [11:0] baud_freq; // baud rate setting registers - see header description
-input [15:0] baud_limit;
-output baud_clk;
-
-// internal wires
-wire ce_16; // clock enable at bit rate
-
-assign baud_clk = ce_16;
-//---------------------------------------------------------------------------------------
-// module implementation
-// baud rate generator module
-baud_gen baud_gen_1
-(
- .clock(clock), .reset(reset),
- .ce_16(ce_16), .baud_freq(baud_freq), .baud_limit(baud_limit)
-);
-
-// uart receiver
-uart_rx uart_rx_1
-(
- .clock(clock), .reset(reset),
- .ce_16(ce_16), .ser_in(ser_in),
- .rx_data(rx_data), .new_rx_data(new_rx_data)
-);
-
-// uart transmitter
-uart_tx uart_tx_1
-(
- .clock(clock), .reset(reset),
- .ce_16(ce_16), .tx_data(tx_data), .new_tx_data(new_tx_data),
- .ser_out(ser_out), .tx_busy(tx_busy)
-);
-
-endmodule
-//---------------------------------------------------------------------------------------
-// Th.. Th.. Th.. Thats all folks !!!
-//---------------------------------------------------------------------------------------
trunk/rtl/uart_top.v
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## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/doc/uart2bus_verification_plan.docx
===================================================================
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Index: trunk/doc/uart2bus_verification_plan.docx
===================================================================
--- trunk/doc/uart2bus_verification_plan.docx (revision 2)
+++ trunk/doc/uart2bus_verification_plan.docx (nonexistent)
trunk/doc/uart2bus_verification_plan.docx
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## -1 +0,0 ##
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Index: trunk/doc/uart2bus_tb.png
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--- trunk/doc/uart2bus_tb.png (revision 2)
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trunk/doc/uart2bus_tb.png
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Index: trunk/doc/uart2bus_tb.jpeg
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Index: trunk/doc/uart2bus_tb.jpeg
===================================================================
--- trunk/doc/uart2bus_tb.jpeg (revision 2)
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trunk/doc/uart2bus_tb.jpeg
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Index: trunk/doc/uart2bus_core.png
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--- trunk/doc/uart2bus_core.png (revision 2)
+++ trunk/doc/uart2bus_core.png (nonexistent)
trunk/doc/uart2bus_core.png
Property changes :
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## -1 +0,0 ##
-*
\ No newline at end of property
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## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: trunk/doc/uart2bus_core.jpeg
===================================================================
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svn:mime-type = application/octet-stream
Index: trunk/doc/uart2bus_core.jpeg
===================================================================
--- trunk/doc/uart2bus_core.jpeg (revision 2)
+++ trunk/doc/uart2bus_core.jpeg (nonexistent)
trunk/doc/uart2bus_core.jpeg
Property changes :
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## -1 +0,0 ##
-*
\ No newline at end of property
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## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: trunk/doc/uart2bus_verification_plan.odt
===================================================================
Cannot display: file marked as a binary type.
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Index: trunk/doc/uart2bus_verification_plan.odt
===================================================================
--- trunk/doc/uart2bus_verification_plan.odt (revision 2)
+++ trunk/doc/uart2bus_verification_plan.odt (nonexistent)
trunk/doc/uart2bus_verification_plan.odt
Property changes :
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## -1 +0,0 ##
-*
\ No newline at end of property
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## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: trunk/doc/uart2bus_tb.dia
===================================================================
Cannot display: file marked as a binary type.
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Index: trunk/doc/uart2bus_tb.dia
===================================================================
--- trunk/doc/uart2bus_tb.dia (revision 2)
+++ trunk/doc/uart2bus_tb.dia (nonexistent)
trunk/doc/uart2bus_tb.dia
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
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## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: trunk/doc/uart2bus_tb.svg
===================================================================
--- trunk/doc/uart2bus_tb.svg (revision 2)
+++ trunk/doc/uart2bus_tb.svg (nonexistent)
@@ -1,386 +0,0 @@
-
-
trunk/doc/uart2bus_tb.svg
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/doc/uart2bus_verification_plan.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/doc/uart2bus_verification_plan.pdf
===================================================================
--- trunk/doc/uart2bus_verification_plan.pdf (revision 2)
+++ trunk/doc/uart2bus_verification_plan.pdf (nonexistent)
trunk/doc/uart2bus_verification_plan.pdf
Property changes :
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## -1 +0,0 ##
-*
\ No newline at end of property
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## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: trunk/doc/uart2bus_core.dia
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/doc/uart2bus_core.dia
===================================================================
--- trunk/doc/uart2bus_core.dia (revision 2)
+++ trunk/doc/uart2bus_core.dia (nonexistent)
trunk/doc/uart2bus_core.dia
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
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## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: trunk/doc/UART to Bus Core Specifications.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/doc/UART to Bus Core Specifications.pdf
===================================================================
--- trunk/doc/UART to Bus Core Specifications.pdf (revision 2)
+++ trunk/doc/UART to Bus Core Specifications.pdf (nonexistent)
trunk/doc/UART to Bus Core Specifications.pdf
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
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## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: trunk/doc/.~lock.uart2bus_verification_plan.odt#
===================================================================
--- trunk/doc/.~lock.uart2bus_verification_plan.odt# (revision 2)
+++ trunk/doc/.~lock.uart2bus_verification_plan.odt# (nonexistent)
@@ -1 +0,0 @@
-,hany,hany-Inspiron-3542,24.01.2016 23:03,file:///home/hany/.config/libreoffice/4;
\ No newline at end of file
trunk/doc/.~lock.uart2bus_verification_plan.odt#
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/tb/draft
===================================================================
--- trunk/tb/draft (revision 2)
+++ trunk/tb/draft (nonexistent)
@@ -1,14 +0,0 @@
-view wave
-
-add wave \
-sim:/uart_top_tb/uart_inf/ser_in \
-sim:/uart_top_tb/uart_inf/ser_out \
-sim:/uart_top_tb/uart_inf/clock \
-sim:/uart_top_tb/uart_inf/start_trans \
-sim:/uart_top_tb/rf_inf/int_address \
-sim:/uart_top_tb/rf_inf/int_wr_data \
-sim:/uart_top_tb/rf_inf/int_write \
-sim:/uart_top_tb/rf_inf/int_rd_data \
-sim:/uart_top_tb/rf_inf/int_read \
-sim:/uart_top_tb/rf_inf/int_gnt \
-sim:/uart_top_tb/rf_inf/int_req
\ No newline at end of file
trunk/tb/draft
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/tb/uart_pkg.sv
===================================================================
--- trunk/tb/uart_pkg.sv (revision 2)
+++ trunk/tb/uart_pkg.sv (nonexistent)
@@ -1,33 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// UART2BUS VERIFICATION
-//
-//-----------------------------------------------------------------------------
-// CREATOR : HANY SALAH
-// PROJECT : UART2BUS UVM TEST BENCH
-// UNIT : TOP MODULE
-//-----------------------------------------------------------------------------
-// TITLE : UART Package
-// DESCRIPTION: This file
-//-----------------------------------------------------------------------------
-// LOG DETAILS
-//-------------
-// VERSION NAME DATE DESCRIPTION
-// 1 HANY SALAH 11012016 FILE CREATION
-//-----------------------------------------------------------------------------
-// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
-// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
-// CREATOR'S PERMISSION
-//-----------------------------------------------------------------------------
-package uart_pkg;
-
- import uvm_pkg::*;
- import agent_pkg::*;
- import env_pkg::*;
-
- `include "uvm_macros.svh"
-
- `include "uart_test.svh"
-
-
-endpackage:uart_pkg
\ No newline at end of file
trunk/tb/uart_pkg.sv
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/tb/interfaces/uart_interface.sv
===================================================================
--- trunk/tb/interfaces/uart_interface.sv (revision 2)
+++ trunk/tb/interfaces/uart_interface.sv (nonexistent)
@@ -1,1307 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// UART2BUS VERIFICATION
-//
-//-----------------------------------------------------------------------------
-// CREATOR : HANY SALAH
-// PROJECT : UART2BUS UVM TEST BENCH
-// UNIT : BUS FUNCTIONAL MODEL
-//-----------------------------------------------------------------------------
-// TITLE : UART Interface
-// DESCRIPTION: This
-//-----------------------------------------------------------------------------
-// LOG DETAILS
-//-------------
-// VERSION NAME DATE DESCRIPTION
-// 1 HANY SALAH 25122015 FILE CREATION
-// 2 HANY SALAH 07012016 ADD USER ROUTINE, TEXT MODE ROUTINES.
-// 3 HANY SALAH 21012016 REPLACE PUSH BYTE WITH PUSH FIELD
-//-----------------------------------------------------------------------------
-// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
-// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
-// CREATOR'S PERMISSION
-//-----------------------------------------------------------------------------
-`include "defin_lib.svh"
-interface uart_interface (input bit clock, // Global Clock Signal
- input bit reset); // Global Asynchronous Reset Signal
-
-//-----------------------------------------------
-//
-// BFM Parameter
-//
-//-----------------------------------------------
-
- int act_edge; // 2: negative edge 1: positive edge
- int start_bit; // 2: LSB first 1: MSB first
- int num_stop_bits;// 2: two stop bits 1: one stop bits
- int num_bits; // 7: seven bits data 8: eight bits data
- int data_rep; // 2: binarry 1: ASCII
- int parity; // 3: parity odd 2: parity even 1: parity off
- time response_time;
-
-
-//-----------------------------------------------
-//
-// UART Signals
-//
-//-----------------------------------------------
-
- logic ser_in; // Serial Data Input
- logic ser_out; // Serial Data Ouptut
- wire serial_out;
-
-//-----------------------------------------------
-//
-// USER Variables Declarations
-//
-//-----------------------------------------------
-
- event start_trans;
-
- assign serial_out = 1'bz;
- assign serial_out = ser_out;
-
-//-----------------------------------------------
-//
-// USER Routines
-//
-//-----------------------------------------------
-
- // Through This routine, the uart bfm is initialize its configuration parameters
- // BFM should know through which edge it will either capture or force the data.
- // Also should know whether the sent or received data will start with most sign-
- // ificant bit or least significant bit.
- function void set_configuration ( int _edge,
- int first_bit,
- int _numstopbits,
- int _numbits,
- int _datarep,
- int _paritymode,
- time _resp);
- act_edge = _edge;
- start_bit = first_bit;
- num_stop_bits = _numstopbits;
- num_bits = _numbits;
- data_rep = _datarep;
- parity = _paritymode;
- response_time = _resp;
- endfunction: set_configuration
-
-
- // Through the following routine, the uart bfm make an event that some transact-
- // -ion would be forced on UART signals
- function void set_event ();
- -> start_trans ;
- endfunction:set_event
-
-
- function void force_sout(bit x);
- case (x)
- 1'b1:
- begin
- //ser_out = `one;
- ser_out = 1'b1;
- end
- 1'b0:
- begin
- //ser_out = `zero;
- ser_out = 1'b0;
- end
- endcase
- endfunction:force_sout
-
- // Through this routine, the uart bfm push bit on the serial ouptut port ser_out
- // based on the configured active edge field, UART will push bit on data. BFM
- // will assign testbench error in case of un-configured active edge.
- task push_bit_serout (input bit data);
- case (act_edge)
- `_negedge:
- begin
- @(negedge clock)
- begin
- force_sout(data);
- end
- end
- `_posedge:
- begin
- @(posedge clock)
- begin
- force_sout(data);
- end
- end
- default:
- begin
- $error("undefined active edge");
- end
- endcase
- endtask:push_bit_serout
-
- // Through this routine, the uart bfm push bit on the serial input port ser_in
- // based on the configured active edge field, UART will push bit on data. BFM
- // will assign testbench error in case of un-configured active edge.
- /*task push_bit_serin (input bit data);
- case (act_edge)
- `_negedge:
- begin
- @(negedge clock)
- begin
- ser_in = data;
- end
- end
- `_posedge:
- begin
- @(posedge clock)
- begin
- ser_in = data;
- end
- end
- default:
- begin
- $error("undefined active edge");
- end
- endcase
- endtask:push_bit_serin*/
-
- // The following task will catch single bit from serial output port ser_out based
- // on the configured active edge field, UART will capture data bit. BFM will
- // assign testbench error in case of un-configured active edge.
- task catch_bit_serout (output bit data);
- case (act_edge)
- `_negedge:
- begin
- @(negedge clock)
- begin
- #(`buad_clk_period/4) data = ser_out;
- end
- end
- `_posedge:
- begin
- @(posedge clock)
- begin
- #(`buad_clk_period/4) data = ser_out;
- end
- end
- default:
- begin
- $error("undefined active edge");
- end
- endcase
- endtask:catch_bit_serout
-
- // The following task will catch single bit from serial input port ser_in based
- // on the configured active edge field, UART will capture data bit. BFM will
- // assign testbench error in case of un-configured active edge.
- task catch_bit_serin (output bit data);
- case (act_edge)
- `_negedge:
- begin
- @(negedge clock)
- begin
- #(`buad_clk_period/4) data = ser_in;
- end
- end
- `_posedge:
- begin
- @(posedge clock)
- begin
- #(`buad_clk_period/4)data = ser_in;
- end
- end
- default:
- begin
- $error("undefined active edge");
- end
- endcase
- endtask:catch_bit_serin
-
- // Through the following task, UART BFM will force data byte on serial output
- // port based on the configured start_bit field. BFM will assign testbench err-
- // or in case of un-configured start_bit field.
- task push_field_serout (input byte data);
- // start bit
- push_bit_serout(1'b0);
-
- // data fields
- case (start_bit)
- `lsb_first:
- begin
- for (int index=0;index<8;index++)
- begin
- push_bit_serout(data[index]);
- end
- end
- `msb_first:
- begin
- for (int index=7;index>=0;index--)
- begin
- push_bit_serout(data[index]);
- end
- end
- default:
- begin
- $error("Undefined serial mode");
- end
- endcase
-
- // Stop bit(s)
- repeat (num_stop_bits)
- begin
- push_bit_serout(1'b1);
- end
-
- endtask:push_field_serout
-
- // Through the following task, UART BFM will force data byte on serial output
- // port based on the configured start_bit field. BFM will assign testbench err-
- // or in case of un-configured start_bit field.
- /*task push_byte_serin (input byte data);
- case (start_bit)
- `lsb_first:
- begin
- for (int index=0;index<8;index++)
- begin
- push_bit_serin(data[index]);
- end
- end
- `msb_first:
- begin
- for (int index=7;index>=0;index--)
- begin
- push_bit_serin(data[index]);
- end
- end
- default:
- begin
- $error("Undefined serial mode");
- end
- endcase
- endtask:push_byte_serin*/
-
-
- // Through the following task, UART BFM will catpure data byte from serial out-
- // put port based on the configured start_bit field. BFM will assign testbench
- // error in case of un-configured start_bit field.
- task catch_field_serout (output byte data);
- bit end_bit;
-
- // wait start bit
- wait(ser_out == 1'b0);
- case(start_bit)
- `lsb_first:
- begin
- for (int index=0;index<8;index++)
- begin
- catch_bit_serout(data[index]);
- end
- end
- `msb_first:
- begin
- for (int index=7;index>=0;index--)
- begin
- catch_bit_serout(data[index]);
- end
- end
- default:
- begin
- $error("Undefined serial mode");
- end
- endcase
- catch_bit_serout(end_bit);
- if(end_bit != 1'b1)
- begin
- $error("at time =%0t ,, the first end bit = %0b",$time,end_bit);
- $stop;
- end
- if (num_stop_bits == 2)
- begin
- catch_bit_serout(end_bit);
- if(end_bit != 1'b1)
- begin
- $error("at time =%0t ,, the first end bit = %0b",$time,end_bit);
- $stop;
- end
- end
- endtask:catch_field_serout
-
- // Through the following task, UART BFM will catpure data byte from serial out-
- // put port based on the configured start_bit field. BFM will assign testbench
- // error in case of un-configured start_bit field.
- task catch_field_serin (output byte data);
- bit end_bit;
-
- // wait start bit
-
- wait (ser_in == 1'b0);
- #(`buad_clk_period/2);
- case(start_bit)
- `lsb_first:
- begin
- for (int index=0;index<8;index++)
- begin
- catch_bit_serin(data[index]);
- end
- end
- `msb_first:
- begin
- for (int index=7;index>=0;index--)
- begin
- catch_bit_serin(data[index]);
- end
- end
- default:
- begin
- $error("Undefined serial mode");
- end
- endcase
- catch_bit_serin(end_bit);
- if(end_bit != 1'b1)
- begin
- $error("at time =%0t ,, the first end bit = %0b",$time,end_bit);
- $stop;
- end
- if (num_stop_bits == 2)
- begin
- catch_bit_serin(end_bit);
- if(end_bit != 1'b1)
- begin
- $error("at time =%0t ,, the first end bit = %0b",$time,end_bit);
- $stop;
- end
- end
- endtask:catch_field_serin
-
-
- // Through the following function, the byte is reversed in the manner that the
- // byte is merrored
- function byte reverse_byte (byte data);
- byte tmp;
- for (int index=0;index<8;index++)
- begin
- tmp[index] = data[7-index];
- end
- return tmp;
- endfunction:reverse_byte
-
-//-----------------------------------------------
-//
-// UART Routines
-//
-//-----------------------------------------------
-
- // Through the following method, UART BFM will initialize write request in UART
- // text mode. This task is accomplished with known of either the request chara-
- // cter is capital or small, and also the used white space type is either single
- // space or tab, and finally the end of line mechanism.
- task write_text_mode(input int alph,
- input int scp_type1,
- input byte space_wrong1,
- input int scp_type2,
- input byte space_wrong2,
- input int eol,
- input byte eol_wrong,
- input bit [`size-1:0] address,
- input byte data);
- // Write procedures
- // First Field
- if (alph == `small_let)
- begin
- push_field_serout(`w);
- end
- else if (alph == `capital_let)
- begin
- push_field_serout(`W);
- end
- else
- $error("Testbench error .. No capitar or small letter is choosed");
-
- // Second Field
- if (scp_type1 == `single_space)
- begin
- push_field_serout(`space);
- end
- else if (scp_type1 == `tab_space)
- begin
- push_field_serout(`tab);
- end
- else if (scp_type1 == `space_wrong)
- begin
- push_field_serout(space_wrong1);
- end
- else
- $error("Testbench error .. No single space or multiple space is choosed");
-
- // third field
- case (data_rep)
- `binary_rep:
- begin
- push_field_serout(data);
- end
- `ascii_rep:
- begin
- push_field_serout(bin_asci_conv(data[7:4]));
- push_field_serout(bin_asci_conv(data[3:0]));
- end
- default:$error("undefined data representation");
- endcase
-
- // forth field
- if (scp_type2 == `single_space)
- begin
- push_field_serout(`space);
- end
- else if (scp_type2 == `tab_space)
- begin
- push_field_serout(`tab);
- end
- else if (scp_type2 == `space_wrong)
- begin
- push_field_serout(space_wrong2);
- end
- else
- $error("Testbench error .. No single or multiple space is choosed");
- // fivth field
- case (data_rep)
- `binary_rep:
- begin
- push_field_serout(address[15:08]);
- push_field_serout(address[07:00]);
- end
- `ascii_rep:
- begin
- push_field_serout(bin_asci_conv(address[15:12]));
- push_field_serout(bin_asci_conv(address[11:08]));
- push_field_serout(bin_asci_conv(address[07:04]));
- push_field_serout(bin_asci_conv(address[03:00]));
- end
- default:$error("undefined data representation");
- endcase
-
- // sixth Field
- if (eol == `cr_eol)
- begin
- push_field_serout(`CR);
- end
- else if (eol == `lf_eol)
- begin
- push_field_serout(`LF);
- end
- else if (eol == `eol_wrong)
- begin
- push_field_serout(eol_wrong);
- end
- else
- $error("Testbench error .. either CR or LF isn't choosed as eol");
- endtask:write_text_mode
-
- // Through the following method, UART BFM will initialize read request in UART
- // text mode and receive the response as defined in UART specification standard
- // This task is accomplished with known of either the request character is cap-
- // ital or small, and also the used white space type is either single space or
- // tab, and finally the end of line mechanism. This methed includes two main se-
- // ctions; the first one includes the four successive fields of defined read re-
- // quest. And the another one includes the response.
- task read_text_mode (input int alph,
- input int scp_type,
- input byte space_wrong,
- input int eol,
- input byte eol_wrong,
- input bit [`size-1:0] address);
- byte data;
- byte temp;
- byte char1,char2;
- bit miss;
- time prope1;
- // Read Request
- // First Field
- if (alph == `small_let)
- begin
- push_field_serout(`r);
- end
- else if (alph == `capital_let)
- begin
- push_field_serout(`R);
- end
- else
- $error("Testbench error .. No capitar or small letter is choosed");
- // Second Field
- if (scp_type == `single_space)
- begin
- push_field_serout(`space);
- end
- else if (scp_type == `tab_space)
- begin
- push_field_serout(`tab);
- end
- else if (scp_type == `space_wrong)
- begin
- push_field_serout(space_wrong);
- end
- else
- $error("Testbench error .. No single or multiple white space is choosed");
-
- // Third Field
- case (data_rep)
- `binary_rep:
- begin
- push_field_serout(address[15:08]);
- push_field_serout(address[07:00]);
- end
- `ascii_rep:
- begin
- push_field_serout(bin_asci_conv(address[15:12]));
- push_field_serout(bin_asci_conv(address[11:08]));
- push_field_serout(bin_asci_conv(address[07:04]));
- push_field_serout(bin_asci_conv(address[03:00]));
- end
- default:$error("undefined data representation");
- endcase
-
- // Forth Field
- if (eol == `cr_eol)
- begin
- push_field_serout(`CR);
- end
- else if (eol == `lf_eol)
- begin
- push_field_serout(`LF);
- end
- else if (eol == `eol_wrong)
- begin
- push_field_serout(eol_wrong);
- end
- else
- $error("Testbench error .. No CR or LF is choosed");
-
- miss = 1'b0;
- prope1 = $time;
- fork
- begin: miss_response_thread
- while (($time-prope1)
trunk/tb/interfaces/uart_interface.sv
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/tb/interfaces/uart_arbiter.sv
===================================================================
--- trunk/tb/interfaces/uart_arbiter.sv (revision 2)
+++ trunk/tb/interfaces/uart_arbiter.sv (nonexistent)
@@ -1,50 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// UART2BUS VERIFICATION
-//
-//-----------------------------------------------------------------------------
-// CREATOR : HANY SALAH
-// PROJECT : UART2BUS UVM TEST BENCH
-// UNIT : INTERFACE
-//-----------------------------------------------------------------------------
-// TITLE : UART Arbiter
-// DESCRIPTION: This
-//-----------------------------------------------------------------------------
-// LOG DETAILS
-//-------------
-// VERSION NAME DATE DESCRIPTION
-// 1 HANY SALAH 29122015 FILE CREATION
-//-----------------------------------------------------------------------------
-// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
-// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
-// CREATOR'S PERMISSION
-//-----------------------------------------------------------------------------
-interface uart_arbiter (input bit clock,
- input bit reset);
-
-//--------------------------------
-//
-// Bus Control Signals
-//
-//--------------------------------
-
- logic int_req; // Request Internal Bus Access
- logic int_gnt; // Grant Internal Bus Access
-
-//--------------------------------
-//
-// Arbiter Control Signals
-//
-//--------------------------------
-
- task accept_req ();
- wait (int_req);
- int_gnt = 1'b1;
- endtask:accept_req
-
- task declain_req ();
- wait (int_req);
- int_gnt = 1'b0;
- endtask:declain_req
-
-endinterface:uart_arbiter
\ No newline at end of file
trunk/tb/interfaces/uart_arbiter.sv
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/tb/interfaces/rf_interface.sv
===================================================================
--- trunk/tb/interfaces/rf_interface.sv (revision 2)
+++ trunk/tb/interfaces/rf_interface.sv (nonexistent)
@@ -1,167 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// UART2BUS VERIFICATION
-//
-//-----------------------------------------------------------------------------
-// CREATOR : HANY SALAH
-// PROJECT : UART2BUS UVM TEST BENCH
-// UNIT : INTERFACE
-//-----------------------------------------------------------------------------
-// TITLE : UART Interface
-// DESCRIPTION: This
-//-----------------------------------------------------------------------------
-// LOG DETAILS
-//-------------
-// VERSION NAME DATE DESCRIPTION
-// 1 HANY SALAH 25122015 FILE CREATION
-//-----------------------------------------------------------------------------
-// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
-// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
-// CREATOR'S PERMISSION
-//-----------------------------------------------------------------------------
-`include "defin_lib.svh"
-interface rf_interface (input bit clock, // Global Clock Signal
- input bit reset); // Global Asynchronous Reset Signal
-
-
-
-//--------------------------------
-//
-// Register File Side Signals
-//
-//--------------------------------
-
- logic [15:0] int_address; // Address Bus To Register File
-
- logic [7:0] int_wr_data; // Write Data To Register File
- logic int_write; // Write Contorl To Register File
-
- logic [7:0] int_rd_data; // Read Data From Register File
- logic int_read; // Read Control To Register File
-
-//--------------------------------
-//
-// CONTROL SIGNALS
-//
-//--------------------------------
-
- logic int_gnt;
- logic int_req;
-//--------------------------------
-//
-// Internal Variables
-//
-//--------------------------------
-
- // Memory of 64K bytes as Register File
- byte register_file [`mem_size-1:0];
-
-//--------------------------------
-//
-// Operation Blocks
-//
-//--------------------------------
-
- always
- begin
- @(posedge clock or posedge reset);
- begin
- if (reset)
- begin
- reset_mem();
- end
- else if (int_write)
- begin
- fill_byte(int_address,int_wr_data);
- end
- else if (int_read)
- begin
- int_rd_data = read_mem_data(int_address);
- end
- end
- end
-
-//--------------------------------
-//
-// Non Standard Routines
-//
-//--------------------------------
-
- // fill_byte routine is a function that fill only single byte in the register
- // file
-function void fill_byte (bit [`size-1:0] address,
- byte data);
-
- register_file[address] = data;
-endfunction:fill_byte
-
- // fill_block routine is a function that fill continuous block of locations
- // in the register file
-function automatic void fill_block(bit [`size-1:0] address,
- ref byte data [],
- int unsigned block_length);
-
- for (int unsigned index = 0; index < block_length; index++)
- begin
- register_file[address+index] = data [index];
- end
-endfunction:fill_block
-
- // reset_mem routine is a function that fill reset the register file to contents
- // zero
- function void reset_mem();
- for (int unsigned index = 0; index < `mem_size; index++)
- begin
- register_file[index] = 8'b0;
- end
-endfunction:reset_mem
-
- // read_mem_data routine is a function that load bus with the data content
- function byte read_mem_data(bit [`size-1:0] address);
- return register_file[address];
- endfunction: read_mem_data
-
- task automatic read_block(input int unsigned data_length,
- input bit [15:0] address,
- ref byte data []);
- data = new [data_length];
- for (int unsigned index=0;index
trunk/tb/interfaces/rf_interface.sv
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/tb/analysis/uart_scoreboard.svh
===================================================================
--- trunk/tb/analysis/uart_scoreboard.svh (revision 2)
+++ trunk/tb/analysis/uart_scoreboard.svh (nonexistent)
@@ -1,164 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// UART2BUS VERIFICATION
-//
-//-----------------------------------------------------------------------------
-// CREATOR : HANY SALAH
-// PROJECT : UART2BUS UVM TEST BENCH
-// UNIT : ANALYSIS
-//-----------------------------------------------------------------------------
-// TITLE : UART ANALYSIS
-// DESCRIPTION: This
-//-----------------------------------------------------------------------------
-// LOG DETAILS
-//-------------
-// VERSION NAME DATE DESCRIPTION
-// 1 HANY SALAH 22012016 FILE CREATION
-//-----------------------------------------------------------------------------
-// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
-// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
-// CREATOR'S PERMISSION
-//-----------------------------------------------------------------------------
-class uart_scoreboard extends uvm_scoreboard;
-
- uvm_tlm_analysis_fifo #(uart_transaction) mon_fifo;
-
- uvm_analysis_export #(uart_transaction) scbd_mon;
-
- uvm_tlm_analysis_fifo #(uart_transaction) drv_fifo;
-
- uvm_analysis_export #(uart_transaction) scbd_drv;
-
- uart_transaction frm_drv,frm_drv_tmp;
-
- uart_transaction frm_mon,frm_mon_tmp;
-
- `uvm_component_utils(uart_scoreboard)
-
- function new (string name , uvm_component parent);
- super.new(name,parent);
- endfunction:new
-
- extern function void build_phase (uvm_phase phase);
-
- extern function void connect_phase (uvm_phase phase);
-
- extern task run_phase (uvm_phase phase);
-endclass:uart_scoreboard
-
-
-function void uart_scoreboard::build_phase (uvm_phase phase);
- super.build_phase(phase);
-
- frm_drv = uart_transaction::type_id::create("frm_drv");
- frm_drv_tmp = uart_transaction::type_id::create("frm_drv_tmp");
-
- frm_mon = uart_transaction::type_id::create("frm_mon");
- frm_mon_tmp = uart_transaction::type_id::create("frm_mon_tmp");
-
- mon_fifo = new ("mon_fifo",this);
- scbd_mon = new ("scbd_mon",this);
-
- drv_fifo = new ("drv_fifo",this);
- scbd_drv = new ("scbd_drv",this);
-
-endfunction:build_phase
-
-function void uart_scoreboard::connect_phase (uvm_phase phase);
- scbd_mon.connect(mon_fifo.analysis_export);
- scbd_drv.connect(drv_fifo.analysis_export);
-endfunction:connect_phase
-
-task uart_scoreboard::run_phase (uvm_phase phase);
- int iteration;
- iteration = 0;
- forever
- begin
- iteration++;
- drv_fifo.get(frm_drv_tmp);
- $cast(frm_drv,frm_drv_tmp.clone());
- mon_fifo.get(frm_mon_tmp);
- $cast(frm_mon,frm_mon_tmp.clone());
-
- if (frm_drv._mode != frm_mon._mode)
- begin
- `uvm_fatal("Testbench Bug",$sformatf("Modes aren't similiar .. @time=%0t, It was requested to use %p mode and the applied mode is %p ",$time,frm_drv._mode,frm_mon._mode))
- end
- else
- begin
- case (frm_drv._mode)
- text:
- begin
- if(frm_drv._command != frm_mon._command)
- begin
- `uvm_fatal("Testbench Bug",$sformatf("Commands aren't identical .. @time=%0t, It was requested to drive %p command and the applied command is %p ",$time,frm_drv._command,frm_mon._command))
- end
- else
- begin
- case(frm_drv._command)
- read:
- begin
- if (frm_drv._data != frm_mon._data)
- begin
- `uvm_error("Failed Read Text Mode",$sformatf("Data fields aren't identical ,, @time=%0t It was requested to drive %p and dut reply with the data %p",$time,frm_drv._data,frm_mon._data))
- end
- else if((frm_drv._data == frm_mon._data) &&
- (frm_drv.address == frm_mon.address) &&
- (frm_drv._spacetype1 == frm_mon._spacetype1) &&
- (frm_drv._eoltype == frm_mon._eoltype) &&
- (frm_drv._chartype == frm_mon._chartype))
- begin
- `uvm_info("Passed Read Text Mode",$sformatf("Data fields are identical ,, @time=%0t It was requested to read from the address %h and dut reply with the data %p using white space = %p and %p prefix character and %p as end of line character",$time,frm_drv.address,frm_mon._data,frm_drv._spacetype1,frm_drv._chartype,
- frm_drv._eoltype),UVM_NONE)
- end
- else
- begin
- `uvm_error("Failed Read Text Mode",$sformatf("@time=%0t .. It is Requested to request to read data = %p address of %h with character prefix : %p using white space = %p and end of line character %p .. and found data = %p and address=%h with character prefix : %p using white space = %p and end of line character %p",$time, frm_drv._data,frm_drv.address,frm_drv._chartype,frm_drv._spacetype1,frm_drv._eoltype,
- frm_mon._data,frm_mon.address,frm_mon._chartype,frm_mon._spacetype1,frm_mon._eoltype))
- end
- end
- write:
- begin
- if (frm_drv._data != frm_mon._data)
- begin
- `uvm_error("Failed Write Text Mode",$sformatf("Data fields aren't identical ,, @time=%0t It was requested to drive %p and dut register the data %p",$time,frm_drv._data,frm_mon._data))
- end
- else if((frm_drv._data == frm_mon._data) &&
- (frm_drv.address == frm_mon.address) &&
- (frm_drv._spacetype1 == frm_mon._spacetype1) &&
- (frm_drv._eoltype == frm_mon._eoltype) &&
- (frm_drv._chartype == frm_mon._chartype))
- begin
- `uvm_info("Passed write Text Mode",$sformatf("Data fields are identical ,, @time=%0t It was requested to write to the address %h and dut register the data %p using white space = %p and %p prefix character and %p as end of line character",$time,frm_drv.address,frm_mon._data,frm_drv._spacetype1,frm_drv._chartype,
- frm_drv._eoltype),UVM_NONE)
- end
- else
- begin
- `uvm_error("Failed write Text Mode",$sformatf("@time=%0t .. It is Requested to request to write data = %p address of %h with character prefix : %p using white space = %p and end of line character %p .. and found data = %p and address=%h with character prefix : %p using white space = %p and end of line character %p",$time, frm_drv._data,frm_drv.address,frm_drv._chartype,frm_drv._spacetype1,frm_drv._eoltype,
- frm_mon._data,frm_mon.address,frm_mon._chartype,frm_mon._spacetype1,frm_mon._eoltype))
- end
-
- end
- default:
- begin
- `uvm_fatal("Testbench Bug",$sformatf("@time = %0t .. It isn't allowablt to drive %p command through text mode",$time,frm_drv._command))
- end
- endcase
- end
- end
- binary:
- begin
-
- end
- wrong_mode:
- begin
-
- end
- default:
- begin
- `uvm_fatal("Testbench Bug",$sformatf("Mode is undefined = %p",frm_drv._mode))
- end
- endcase
- end
- end
-endtask:run_phase
\ No newline at end of file
trunk/tb/analysis/uart_scoreboard.svh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/tb/uart_top.sv
===================================================================
--- trunk/tb/uart_top.sv (revision 2)
+++ trunk/tb/uart_top.sv (nonexistent)
@@ -1,113 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// UART2BUS VERIFICATION
-//
-//-----------------------------------------------------------------------------
-// CREATOR : HANY SALAH
-// PROJECT : UART2BUS UVM TEST BENCH
-// UNIT : TOP MODULE
-//-----------------------------------------------------------------------------
-// TITLE : UART Top
-// DESCRIPTION: This
-//-----------------------------------------------------------------------------
-// LOG DETAILS
-//-------------
-// VERSION NAME DATE DESCRIPTION
-// 1 HANY SALAH 11012016 FILE CREATION
-//-----------------------------------------------------------------------------
-// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
-// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
-// CREATOR'S PERMISSION
-//-----------------------------------------------------------------------------
- `include "defin_lib.svh"
- `include "uart2bus_top.v"
-
-module uart_top_tb;
-
- import uvm_pkg::*;
- import uart_pkg::*;
-
- `include "uvm_macros.svh"
-
- logic clk_glob;
-
- logic clk_uart;
-
- logic reset;
-
- assign rf_inf.int_req = arb_inf.int_req;
- assign rf_inf.int_gnt = arb_inf.int_gnt;
-
- uart_interface uart_inf (.reset(reset),
- .clock(clk_uart));
-
- rf_interface rf_inf (.reset(reset),
- .clock(clk_glob));
-
- uart_arbiter arb_inf (.reset (reset),
- .clock(clk_glob));
-
- uart2bus_top dut( .clock(clk_glob),
- .reset(reset),
- //.ser_in(serial_out),
- .ser_in(uart_inf.ser_out),
- .ser_out(uart_inf.ser_in),
- .int_address(rf_inf.int_address),
- .int_wr_data(rf_inf.int_wr_data),
- .int_write(rf_inf.int_write),
- .int_rd_data(rf_inf.int_rd_data),
- .int_read(rf_inf.int_read),
- .int_req(arb_inf.int_req),
- //.int_gnt(arb_inf.int_gnt));
- .int_gnt(1'b1));
-
-
-
- initial
- begin
- reset = 1'b1;
- clk_glob = 1'b0;
- clk_uart = 1'b0;
- #100;
- reset = 1'b0;
- end
-
- initial
- begin
- fork
- forever
- begin
- #(`glob_clk_period/2) clk_glob = ~clk_glob;
- #((`glob_clk_period/2)+1) clk_glob = ~clk_glob;
- end
- forever
- begin
- #(`buad_clk_period/2) clk_uart = ~clk_uart;
- #((`buad_clk_period/2)+1) clk_uart = ~clk_uart;
- end
- begin
- #(500000000);
- $error("Exceed the maximum limited time for simulation ..");
- $finish;
- end
- join
- end
-
-
- initial
- begin
- uvm_config_db#(virtual uart_interface)::set(uvm_root::get(), "*", "uart_inf",uart_inf);
-
- uvm_config_db#(virtual rf_interface)::set(uvm_root::get(), "*", "rf_inf",rf_inf);
-
- uvm_config_db#(virtual uart_arbiter)::set(uvm_root::get(),"*","arb_inf",arb_inf);
-
- run_test("write_text_mode");
- //run_test("read_text_mode");
- //run_test("nop_command_mode");
- //run_test("read_command_mode");
- //run_test("write_command_mode");
- end
-
-
-endmodule:uart_top_tb
\ No newline at end of file
trunk/tb/uart_top.sv
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/tb/run.do
===================================================================
--- trunk/tb/run.do (revision 2)
+++ trunk/tb/run.do (nonexistent)
@@ -1,63 +0,0 @@
-vlib work
-#vlog -novopt ../../../uvm-1.2/src/uvm.sv +incdir+../../../uvm-1.2/src/
-vlog -novopt interfaces/uart_interface.sv +incdir+../
-vlog -novopt interfaces/rf_interface.sv +incdir+../
-vlog -novopt interfaces/uart_arbiter.sv +incdir+../
-#vlog -novopt agent/agent_pkg.sv +incdir+agent/
-
-
-#vlog -novopt agent/agent_pkg.sv +incdir+agent +incdir+agent/driver +incdir+./ +incdir+agent/configuration +incdir+agent/sequence +incdir+agent/transaction +incdir+../../../uvm-1.2/src/
-
-vlog -novopt agent/agent_pkg.sv +incdir+agent +incdir+agent/driver +incdir+./ +incdir+agent/configuration +incdir+agent/sequence +incdir+agent/transaction +incdir+agent/monitor
-
-vlog -novopt env/env_pkg.sv +incdir+env +incdir+analysis
-#vlog -novopt env/env_pkg.sv +incdir+env +incdir+../../../uvm-1.2/src/
-
-vlog -novopt uart_pkg.sv +incdir+test/ +incdir+agent/ +incdir+env/ +incdir+./ +incdir+../
-#vlog -novopt uart_pkg.sv +incdir+test/ +incdir+agent/ +incdir+env/ +incdir+../../../uvm-1.2/src/ +incdir+./
-
-
-
-vlog ../rtl/uart_tx.v +incdir+../rtl
-vlog ../rtl/uart_rx.v +incdir+../rtl
-vlog ../rtl/baud_gen.v +incdir+../rtl
-vlog ../rtl/uart_top.v +incdir+../rtl
-vlog ../rtl/uart_parser.v +incdir+../rtl
-vlog ../rtl/uart2bus_top.v +incdir+../rtl
-
-vlog -novopt uart_top.sv +incdir+../../rtl/i2c/ +incdir+./ +incdir+../rtl
-#vlog -novopt uart_top.sv +incdir+../../rtl/i2c/ +incdir+../../../uvm-1.2/src/
-
-vsim -novopt uart_top_tb
-view wave
-
-add wave \
-sim:/uart_top_tb/uart_inf/ser_in \
-sim:/uart_top_tb/uart_inf/ser_out \
-sim:/uart_top_tb/uart_inf/serial_out \
-sim:/uart_top_tb/serial_out \
-sim:/uart_top_tb/uart_inf/clock \
-sim:/uart_top_tb/uart_inf/start_trans \
-sim:/uart_top_tb/rf_inf/int_address \
-sim:/uart_top_tb/rf_inf/int_wr_data \
-sim:/uart_top_tb/rf_inf/int_write \
-sim:/uart_top_tb/rf_inf/int_rd_data \
-sim:/uart_top_tb/rf_inf/int_read \
-sim:/uart_top_tb/rf_inf/int_gnt \
-sim:/uart_top_tb/rf_inf/int_req \
-sim:/uart_top_tb/dut/int_gnt \
-sim:/uart_top_tb/dut/int_req \
-sim:/uart_top_tb/dut/ser_in \
-sim:/uart_top_tb/dut/ser_out \
-sim:/uart_top_tb/dut/reset \
-sim:/uart_top_tb/dut/clock
-run -all
-
-
-
-
-
-
-
-#vsim i2c_top +UVM_CONFIG_DB_TRACE
-#run -all
\ No newline at end of file
trunk/tb/run.do
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/tb/env/env_pkg.sv
===================================================================
--- trunk/tb/env/env_pkg.sv (revision 2)
+++ trunk/tb/env/env_pkg.sv (nonexistent)
@@ -1,34 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// UART2BUS VERIFICATION
-//
-//-----------------------------------------------------------------------------
-// CREATOR : HANY SALAH
-// PROJECT : UART2BUS UVM TEST BENCH
-// UNIT : ENVIRONEMNT
-//-----------------------------------------------------------------------------
-// TITLE : UART ENVIRONMENT PKG
-// DESCRIPTION: This
-//-----------------------------------------------------------------------------
-// LOG DETAILS
-//-------------
-// VERSION NAME DATE DESCRIPTION
-// 1 HANY SALAH 10012016 FILE CREATION
-//-----------------------------------------------------------------------------
-// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
-// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
-// CREATOR'S PERMISSION
-//-----------------------------------------------------------------------------
-
-package env_pkg;
-
- import agent_pkg::*;
- import uvm_pkg::*;
-
- `include "uvm_macros.svh"
-
-
- `include "uart_scoreboard.svh"
- `include "uart_env.svh"
-
-endpackage:env_pkg
\ No newline at end of file
trunk/tb/env/env_pkg.sv
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/tb/env/uart_env.svh
===================================================================
--- trunk/tb/env/uart_env.svh (revision 2)
+++ trunk/tb/env/uart_env.svh (nonexistent)
@@ -1,52 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// UART2BUS VERIFICATION
-//
-//-----------------------------------------------------------------------------
-// CREATOR : HANY SALAH
-// PROJECT : UART2BUS UVM TEST BENCH
-// UNIT : AGENT
-//-----------------------------------------------------------------------------
-// TITLE : UART ENVIRONMENT
-// DESCRIPTION: This
-//-----------------------------------------------------------------------------
-// LOG DETAILS
-//-------------
-// VERSION NAME DATE DESCRIPTION
-// 1 HANY SALAH 10012016 FILE CREATION
-//-----------------------------------------------------------------------------
-// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
-// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
-// CREATOR'S PERMISSION
-//-----------------------------------------------------------------------------
-class uart_env extends uvm_env;
-
- uart_agent agent;
-
- uart_scoreboard scbd;
-
- `uvm_component_utils(uart_env)
-
- function new (string name,uvm_component parent);
- super.new(name,parent);
- endfunction:new
-
- extern function void build_phase (uvm_phase phase);
-
- extern function void connect_phase (uvm_phase phase);
-endclass:uart_env
-
-function void uart_env::build_phase (uvm_phase phase);
- super.build_phase(phase);
- agent = uart_agent::type_id::create("agent",this);
- scbd = uart_scoreboard::type_id::create("uart_scoreboard",this);
-
-endfunction:build_phase
-
-function void uart_env::connect_phase (uvm_phase phase);
- super.connect_phase(phase);
-
- agent.drv_port.connect(scbd.scbd_drv);
- agent.mon_port.connect(scbd.scbd_mon);
-
-endfunction:connect_phase
\ No newline at end of file
trunk/tb/env/uart_env.svh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/tb/defin_lib.svh
===================================================================
--- trunk/tb/defin_lib.svh (revision 2)
+++ trunk/tb/defin_lib.svh (nonexistent)
@@ -1,380 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// UART2BUS VERIFICATION
-//
-//-----------------------------------------------------------------------------
-// CREATOR : HANY SALAH
-// PROJECT : UART2BUS UVM TEST BENCH
-// UNIT : DEFINITION LIBRARY
-//-----------------------------------------------------------------------------
-// TITLE : UART Definition Library
-// DESCRIPTION: This
-//-----------------------------------------------------------------------------
-// LOG DETAILS
-//-------------
-// VERSION NAME DATE DESCRIPTION
-// 1 HANY SALAH 25122015 FILE CREATION
-// 2 HANY SALAH 31122015 ADD DATA TYPE DEFINITIONS
-// 3 HANY SALAH 11012016 ADD TIMING PARAMETERS DEFINITION
-//-----------------------------------------------------------------------------
-// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
-// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
-// CREATOR'S PERMISSION
-//-----------------------------------------------------------------------------
-`timescale 1ns/1ns
-//------------------------------------------
-//
-// Definition Identifiers
-//
-//------------------------------------------
-
- // Define size of address line
- `define size 16
-
- // 2 power size
- `define mem_size 65536
-
- // ASCII of 'r'
- `define r 8'h72
-
- // ASCII of 'R'
- `define R 8'h52
-
- // ASCII of 'w'
- `define w 8'h77
-
- // ASCII of 'W'
- `define W 8'h57
-
- // BINARY COMMAND PREFIX
- `define bin_prfx 8'h0
-
- // Single Space
- `define space 8'h20
-
- // Signel Tab
- `define tab 8'h09
-
- // LF
- `define LF 8'h0A
-
- // CR
- `define CR 8'h0D
-
- //UNIFIED ACK
- `define ACK 8'h5A
-
- // work on positive edge
- `define _posedge 1
-
- // work on negative edge
- `define _negedge 2
-
- // start with MSB
- `define msb_first 1
-
- // start with LSB
- `define lsb_first 2
-
- // Text Mode Command
- `define text_mode 1
-
- // Binary Mode Command
- `define binary_mode 2
-
- // Wrong Mode Command
- `define wrong_mode 3
-
- // Read Command
- `define read_comm 1
-
- // write Command
- `define write_comm 2
-
- // nop Command
- `define nop_comm 3
-
- // wrong Command
- `define wrong_comm 4
-
- // Use single white space
- `define single_space 1
-
- // Use multiple white space
- `define tab_space 2
-
- // Use wrong space character
- `define space_wrong 3
-
- // use cr as eol
- `define cr_eol 1
-
- // use lf as eol
- `define lf_eol 2
-
- // Use wrong eol
- `define eol_wrong 3
-
- // request either address increment or acknowledge
- `define _yes 1
-
- // don't request either address increment or acknowledge
- `define _no 2
-
- // Use capital Leter
- `define capital_let 1
-
- // Use small letter
- `define small_let 2
-
- // accept arbitration
- `define accept 1
-
- // declain arbitration
- `define declain 2
-
- // Binary represnetation
- `define binary_rep 1
-
- // ASCII Representation
- `define ascii_rep 2
-
- // NOP Control
- `define nop_ctrl 2'b00
-
- // Read Control
- `define read_ctrl 2'b01
-
- // Write Control
- `define write_ctrl 2'b10
-//------------------------------------------
-//
-// Timing Defines
-//
-//------------------------------------------
- // Define stability time
- `define stab 10
-
- // Define the period of global clock in terms of ns
- `define glob_clk_period 25
-
- // Define the period of baud clock in terms of ns
- `define buad_clk_period 8680
-//------------------------------------------
-//
-// Configuration Data Type
-//
-//------------------------------------------
-
-// Represents the active edge
-typedef enum {pos_edge=1, // Based on positive edge
- neg_edge=2} act_edge; // Based on negative edge
-
-// Represent the starting bit
-typedef enum {msb=1, // Most Significant bit first
- lsb=2} start_bit; // Least Significant bit first
-
-//------------------------------------------
-//
-// New Data Type Definitions
-//
-//------------------------------------------
-
- // Represents the mode of command to be one of the following options {text, command, wrong}. Wrong
- // command mode is used to send a tricky fault command to test our DUT.
- typedef enum {text=1, // Communicate using text mode
- binary=2, // Communicate using command mode
- wrong_mode=3} mode; // Communicate using wrong prefix
-
- // Represents the type of the used white space to be one of the following options {single, tab, wrong}.
- // Wrong type also is used to push tricky byte in the text mode.
- typedef enum {single=1, // Using single space as a white space
- tab=2, // Using tab as a white space
- wrong_space=3} space_type; // Using wrong white space
-
- // Represents the type of end of line used to be one of the following choices{cr, lf, wrong}.
- // Wrong type is also used to push DUT in tricky manner.
- typedef enum {cr=1, // Using CR as EOL
- lf=2, // Using LF as EOL
- wrong_eol=3} eol_type; // Using wrong EOL
-
- // Represents the command either to be one of the following choices {read, write, NOP}
- typedef enum {read=1, // Read Command
- write=2, // Write Command
- nop=3, // Make No Operation
- invalid=4} command; // Invalid command value
-
- // Represents both acknowledge and incremental address request{yes, no}
- typedef enum {yes=1, // Request Acknowledge
- no=2} req; // Request No Acknowledge
-
- // Represents the type of prefix in text mode either to be {capital, small}.
- typedef enum {cap=1, // Capital Letter
- smal=2} char_type; // Small Letter
-
- // Represents the internal bus state either {accept, refuse}
- typedef enum {accept=1, // Accept Bus Grant
- declain=2} arbit; // Refuse Bus Grant
-
- // Define mode of data {ascii or binary}
- typedef enum {bin=1,
- ascii=2} data_mode;
-
- // Define mode of the used parity
- typedef enum {parity_off=1,
- parity_even=2,
- parity_odd=3} parity_mode ;
-
-//-------------------------------------------------------
-//
-// GLOBAL FUNCTION
-//
-//-------------------------------------------------------
-
-// Binary To ASCII Conversion to convert nibble into ASCII byte through the following look-up-table
-function byte bin_asci_conv (bit[3:0] data);
- byte temp;
- case (data)
- 4'h0:
- begin
- temp = 8'h30;
- end
- 4'h1:
- begin
- temp = 8'h31;
- end
- 4'h2:
- begin
- temp = 8'h32;
- end
- 4'h3:
- begin
- temp = 8'h33;
- end
- 4'h4:
- begin
- temp = 8'h34;
- end
- 4'h5:
- begin
- temp = 8'h35;
- end
- 4'h6:
- begin
- temp = 8'h36;
- end
- 4'h7:
- begin
- temp = 8'h37;
- end
- 4'h8:
- begin
- temp = 8'h38;
- end
- 4'h9:
- begin
- temp = 8'h39;
- end
- 4'hA:
- begin
- temp = 8'h41;
- end
- 4'hB:
- begin
- temp = 8'h42;
- end
- 4'hC:
- begin
- temp = 8'h43;
- end
- 4'hD:
- begin
- temp = 8'h44;
- end
- 4'hE:
- begin
- temp = 8'h45;
- end
- 4'hF:
- begin
- temp = 8'h46;
- end
- endcase
- return temp;
-endfunction:bin_asci_conv
-
-// ASCII To Binary Conversion is to convert ASCII byte into Binary nibble through the following Look-Up-Table
-function bit [3:0] asci_bin_conv (byte data);
- bit [3:0] temp;
- case (data)
- 8'h30:
- begin
- temp = 4'h0;
- end
- 8'h31:
- begin
- temp = 4'h1;
- end
- 8'h32:
- begin
- temp = 4'h2;
- end
- 8'h33:
- begin
- temp = 4'h3;
- end
- 8'h34:
- begin
- temp = 4'h4;
- end
- 8'h35:
- begin
- temp = 4'h5;
- end
- 8'h36:
- begin
- temp = 4'h6;
- end
- 8'h37:
- begin
- temp = 4'h7;
- end
- 8'h38:
- begin
- temp = 4'h8;
- end
- 8'h39:
- begin
- temp = 4'h9;
- end
- 8'h41:
- begin
- temp = 4'hA;
- end
- 8'h42:
- begin
- temp = 4'hB;
- end
- 8'h43:
- begin
- temp = 4'hC;
- end
- 8'h44:
- begin
- temp = 4'hD;
- end
- 8'h45:
- begin
- temp = 4'hE;
- end
- 8'h46:
- begin
- temp = 4'hF;
- end
- default:
- begin
- $error("undefined ascii symbol");
- end
- endcase
- return temp;
-endfunction:asci_bin_conv
\ No newline at end of file
trunk/tb/defin_lib.svh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/tb/agent/transaction/uart_transaction.svh
===================================================================
--- trunk/tb/agent/transaction/uart_transaction.svh (revision 2)
+++ trunk/tb/agent/transaction/uart_transaction.svh (nonexistent)
@@ -1,116 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// UART2BUS VERIFICATION
-//
-//-----------------------------------------------------------------------------
-// CREATOR : HANY SALAH
-// PROJECT : UART2BUS UVM TEST BENCH
-// UNIT : TRANSACTION
-//-----------------------------------------------------------------------------
-// TITLE : UART Transaction
-// DESCRIPTION: This
-//-----------------------------------------------------------------------------
-// LOG DETAILS
-//-------------
-// VERSION NAME DATE DESCRIPTION
-// 1 HANY SALAH 31122015 FILE CREATION
-// 2 HANY SALAH 01012016 COMPLETE ATTRIBUTES
-//-----------------------------------------------------------------------------
-// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
-// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
-// CREATOR'S PERMISSION
-//-----------------------------------------------------------------------------
-class uart_transaction extends uvm_sequence_item;
-
- // Represent the mode of operation either to be text or command mode
- rand mode _mode;
-
- // Represent the type of space either to be single space or tab
- rand space_type _spacetype1,_spacetype2;
-
- // Represent the wrong character used as a white space [Refer To Verification Plan For More Information]
- rand byte space_wrong1;
-
- // Represent the wrong character used as a white space [Refer To Verification Plan For More Information]
- rand byte space_wrong2;
-
- // Represent the used data through the stimulus
- rand byte _data [];
-
- // Represent the length of data used through the stimulus
- rand int unsigned length_data;
-
- // Represent the type of end of line used
- rand eol_type _eoltype;
-
- // Represent the wrong character used as an end of line [Refer To Verification Plan For More Information]
- rand byte eol_wrong;
-
- // Represent the used address through the stimulus
- rand bit [15:0] address;
-
- // Represent the type of command either read, write or no operation
- rand command _command;
-
- // Represent the acknowledge request
- rand req _reqack;
-
- // Represent the incremental address request
- rand req _reqinc;
-
- // Represent the character type of prefix in text mode command
- rand char_type _chartype;
-
- // Represent the internal bus state either free or busy
- rand arbit _arbit;
-
- // Represents random idle time
- rand time time_before,time_after;
-
- byte acknowledge;
-
- int unsigned scale = 100;
-
- `uvm_object_utils(uart_transaction)
-
- function new (string name ="uart_transaction");
- super.new(name);
- endfunction: new
-
- constraint data_length {
- _data.size == length_data;
- length_data <= 10;
- time_before inside {200,300,400,500,600,700,800,900,1000};
- time_after inside {200,300,400,500,600,700,800,900,1000};
- }
-
- extern function void do_copy (uvm_object rhs);
-endclass:uart_transaction
-
-
-function void uart_transaction::do_copy (uvm_object rhs);
- uart_transaction _trans;
- if (!$cast(_trans,rhs))
- begin
- `uvm_fatal("TYPE MISMATCH", "Type mismatch through do_copy method")
- end
- super.do_copy (_trans);
- _mode =_trans._mode;
- _spacetype1 =_trans._spacetype1;
- _spacetype2 =_trans._spacetype2;
- space_wrong1=_trans.space_wrong1;
- space_wrong2=_trans.space_wrong2;
- _data =_trans._data;
- length_data =_trans.length_data;
- _eoltype =_trans._eoltype;
- eol_wrong =_trans.eol_wrong;
- address =_trans.address;
- _command =_trans._command;
- _reqack =_trans._reqack;
- _reqinc =_trans._reqinc;
- _chartype =_trans._chartype;
- _arbit =_trans._arbit;
- time_before =_trans.time_before;
- time_after =_trans.time_after;
- acknowledge = _trans.acknowledge;
-endfunction:do_copy
\ No newline at end of file
trunk/tb/agent/transaction/uart_transaction.svh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/tb/agent/agent_pkg.sv
===================================================================
--- trunk/tb/agent/agent_pkg.sv (revision 2)
+++ trunk/tb/agent/agent_pkg.sv (nonexistent)
@@ -1,38 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// UART2BUS VERIFICATION
-//
-//-----------------------------------------------------------------------------
-// CREATOR : HANY SALAH
-// PROJECT : UART2BUS UVM TEST BENCH
-// UNIT : AGENT
-//-----------------------------------------------------------------------------
-// TITLE : UART AGENT PKG
-// DESCRIPTION: This
-//-----------------------------------------------------------------------------
-// LOG DETAILS
-//-------------
-// VERSION NAME DATE DESCRIPTION
-// 1 HANY SALAH 10012016 FILE CREATION
-//-----------------------------------------------------------------------------
-// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
-// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
-// CREATOR'S PERMISSION
-//-----------------------------------------------------------------------------
-
-package agent_pkg;
-
- `include "defin_lib.svh"
-
- import uvm_pkg::*;
- `include "uvm_macros.svh"
-
- `include "uart_transaction.svh"
- `include "uart_sequence.svh"
- `include "uart_config.svh"
- `include "uart_driver.svh"
- `include "uart_monitor.svh"
-
- `include "uart_agent.svh"
-
-endpackage:agent_pkg
\ No newline at end of file
trunk/tb/agent/agent_pkg.sv
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/tb/agent/configuration/uart_config.svh
===================================================================
--- trunk/tb/agent/configuration/uart_config.svh (revision 2)
+++ trunk/tb/agent/configuration/uart_config.svh (nonexistent)
@@ -1,50 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// UART2BUS VERIFICATION
-//
-//-----------------------------------------------------------------------------
-// CREATOR : HANY SALAH
-// PROJECT : UART2BUS UVM TEST BENCH
-// UNIT : CONFIGURATION
-//-----------------------------------------------------------------------------
-// TITLE : UART Configuration
-// DESCRIPTION: This
-//-----------------------------------------------------------------------------
-// LOG DETAILS
-//-------------
-// VERSION NAME DATE DESCRIPTION
-// 1 HANY SALAH 02012016 FILE CREATION
-//-----------------------------------------------------------------------------
-// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
-// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
-// CREATOR'S PERMISSION
-//-----------------------------------------------------------------------------
-
-class uart_config extends uvm_object;
-
- virtual uart_interface uart_inf;
-
- virtual rf_interface rf_inf;
-
- virtual uart_arbiter arb_inf;
-
- act_edge _edge;
-
- start_bit _start;
-
- data_mode _datamode;
-
- int num_stop_bits;
-
- int num_of_bits;
-
- parity_mode _paritymode;
-
- time response_time;
-
- `uvm_object_utils(uart_config)
-
- function new (string name = "uart_config");
- super.new(name);
- endfunction:new
-endclass:uart_config
\ No newline at end of file
trunk/tb/agent/configuration/uart_config.svh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/tb/agent/monitor/uart_monitor.svh
===================================================================
--- trunk/tb/agent/monitor/uart_monitor.svh (revision 2)
+++ trunk/tb/agent/monitor/uart_monitor.svh (nonexistent)
@@ -1,147 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// UART2BUS VERIFICATION
-//
-//-----------------------------------------------------------------------------
-// CREATOR : HANY SALAH
-// PROJECT : UART2BUS UVM TEST BENCH
-// UNIT : MONITOR
-//-----------------------------------------------------------------------------
-// TITLE : UART Monitor
-// DESCRIPTION: This
-//-----------------------------------------------------------------------------
-// LOG DETAILS
-//-------------
-// VERSION NAME DATE DESCRIPTION
-// 1 HANY SALAH 12012016 FILE CREATION
-//-----------------------------------------------------------------------------
-// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
-// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
-// CREATOR'S PERMISSION
-//-----------------------------------------------------------------------------
-class uart_monitor extends uvm_monitor;
-
- uart_transaction trans;
-
- uart_config _config;
-
- virtual uart_interface uart_inf;
-
- virtual rf_interface rf_inf;
-
- uvm_analysis_port #(uart_transaction) mon_scbd;
-
- `uvm_component_utils(uart_monitor)
-
- function new (string name, uvm_component parent);
- super.new(name,parent);
- endfunction:new
-
- function void display_content ();
- $display("here %s\n command_type = %p \n command = %p \n char_type = %p \n space_type1 = %p \n space_wrong1 = %8b \n space_type2 = %p \n space_wrong2 = %8b \n eol_type = %p \n eol_wrong = %8b \n address = %h \n data = %8b", get_full_name(),trans._mode,
- trans._command,
- trans._chartype,
- trans._spacetype1,
- trans.space_wrong1,
- trans._spacetype2,
- trans.space_wrong2,
- trans._eoltype,
- trans.eol_wrong,
- trans.address,
- trans._data[0]);
- endfunction:display_content
-
- extern function void build_phase (uvm_phase phase);
-
- extern function void connect_phase (uvm_phase phase);
-
- extern function void end_of_elaboration_phase (uvm_phase phase);
-
- extern task run_phase (uvm_phase phase);
-
-endclass:uart_monitor
-
-function void uart_monitor::build_phase (uvm_phase phase);
- super.build_phase(phase);
-
- _config = uart_config::type_id::create("_config",this);
-
- trans = uart_transaction::type_id::create("trans");
-
- mon_scbd = new ("mon_scbd",this);
-endfunction:build_phase
-
-function void uart_monitor::connect_phase (uvm_phase phase);
-
-endfunction:connect_phase
-
-function void uart_monitor::end_of_elaboration_phase(uvm_phase phase);
- if (!uvm_config_db#(uart_config)::get(this,"","UART_CONFIGURATION",_config))
- `uvm_fatal("NOCONFIGURATION",{"configuration instance must be set for",get_full_name(),"._config"})
-
- if (!uvm_config_db#(virtual uart_interface)::get(this,"","uart_inf",_config.uart_inf))
- `uvm_fatal("NOINF",{"UART Interface instance must be set for",get_full_name,".uart_inf"})
- uart_inf = _config.uart_inf;
-
- if(!uvm_config_db#(virtual rf_interface)::get(this,"","rf_inf",_config.rf_inf))
- `uvm_fatal("NOINF",{"RF Interface instance must be set for",get_full_name(),".rf_inf"})
- rf_inf = _config.rf_inf;
-
-endfunction:end_of_elaboration_phase
-
-task uart_monitor::run_phase (uvm_phase phase);
- int iteration;
- int command_type;
- int _command;
- int _chartype;
- int _spacetype1;
- int _spacetype2;
- int _eoltype;
- int _reqack;
- int _reqinc;
- iteration = 0;
- forever
- begin
- iteration++;
- uart_inf.wait_event();
- uart_inf.capture_command(command_type,
- _command,
- _chartype,
- _spacetype1,
- trans.space_wrong1,
- _spacetype2,
- trans.space_wrong2,
- _eoltype,
- trans.eol_wrong,
- trans.address,
- trans._data,
- trans.acknowledge,
- trans.length_data,
- _reqack,
- _reqinc);
- trans._mode = mode'(command_type);
- trans._command = command'(_command);
- trans._chartype = char_type'(_chartype);
- trans._spacetype1 = space_type'(_spacetype1);
- trans._spacetype2 = space_type'(_spacetype2);
- trans._eoltype = eol_type '(_eoltype);
- trans._reqinc = req '(_reqinc);
- trans._reqack = req '(_reqack);
- if (trans._command == write)
- begin
- if (trans._mode == text)
- begin
- trans._data[0] = rf_inf.read_mem_data(trans.address[7:0]);
- end
- else if (trans._mode == binary)
- begin
- rf_inf.read_block(trans.data_length,
- trans.address,
- trans._data);
- end
- end
- //display_content();
- mon_scbd.write(trans);
- end
-
-endtask:run_phase
trunk/tb/agent/monitor/uart_monitor.svh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/tb/agent/sequence/uart_sequence.svh
===================================================================
--- trunk/tb/agent/sequence/uart_sequence.svh (revision 2)
+++ trunk/tb/agent/sequence/uart_sequence.svh (nonexistent)
@@ -1,1338 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// UART2BUS VERIFICATION
-//
-//-----------------------------------------------------------------------------
-// CREATOR : HANY SALAH
-// PROJECT : UART2BUS UVM TEST BENCH
-// UNIT : SEQUENCE
-//-----------------------------------------------------------------------------
-// TITLE : UART Sequence
-// DESCRIPTION: This
-//-----------------------------------------------------------------------------
-// LOG DETAILS
-//-------------
-// VERSION NAME DATE DESCRIPTION
-// 1 HANY SALAH 01012016 FILE CREATION
-// 2 HANY SALAH 02012016 ADD REST OF TESTS
-//-----------------------------------------------------------------------------
-// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
-// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
-// CREATOR'S PERMISSION
-//-----------------------------------------------------------------------------
-
-
-// Base Sequence Class that hold the common attributes to all sequences
-class uart_base_sequence extends uvm_sequence #(uart_transaction);
-
- uart_transaction trans;
-
- `uvm_object_utils(uart_base_sequence)
-
- function new (string name = "uart_base_sequence");
- super.new(name);
- trans = uart_transaction::type_id::create("trans");
- endfunction:new
-endclass:uart_base_sequence
-
-//-------------------------------------------------------
-//
-// WRITE IN TEXT MODE
-//
-//-------------------------------------------------------
-
- // 1.1 Apply UART write request using capital W
- class seq_1p1 extends uart_base_sequence;
-
- `uvm_object_utils(seq_1p1)
-
- function new (string name = "seq_1p1");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == text;
- _spacetype1 != wrong_space;
- _spacetype2 != wrong_space;
- length_data == 1;
- _eoltype != wrong_eol;
- _command == write;
- _reqinc == no;
- _arbit == accept;
- _chartype == cap;
- };
- finish_item(trans);
- endtask:body
- endclass:seq_1p1
-
-
- // 1.2 Apply UART write request using small w
- class seq_1p2 extends uart_base_sequence;
-
- `uvm_object_utils(seq_1p2)
-
- function new (string name = "seq_1p2");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == text;
- _spacetype1 != wrong_space;
- _spacetype2 != wrong_space;
- length_data == 1;
- _eoltype != wrong_eol;
- _command == write;
- _reqinc == no;
- _arbit == accept;
- _chartype == smal;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_1p2
-
-
- // 1.3 Apply UART write request using single space only
- class seq_1p3 extends uart_base_sequence;
-
- `uvm_object_utils(seq_1p3)
-
- function new (string name = "seq_1p3");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == text;
- _spacetype1 == single;
- _spacetype2 == single;
- length_data == 1;
- _eoltype != wrong_eol;
- _command == write;
- _reqinc == no;
- _arbit == accept;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_1p3
-
-
- // 1.4 Apply UART write request using tab only.
- class seq_1p4 extends uart_base_sequence;
-
- `uvm_object_utils(seq_1p4)
-
- function new (string name = "seq_1p4");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == text;
- _spacetype1 == tab;
- _spacetype2 == tab;
- length_data == 1;
- _eoltype != wrong_eol;
- _command == write;
- _reqinc == no;
- _arbit == accept;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_1p4
-
-
- // 1.5 Apply UART write request using both single space and tab.
- class seq_1p5 extends uart_base_sequence;
-
- `uvm_object_utils(seq_1p5)
-
- function new (string name = "seq_1p5");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == text;
- _spacetype1 != wrong_space;
- _spacetype2 != wrong_space;
- _spacetype2 != _spacetype1;
- length_data == 1;
- _eoltype != wrong_eol;
- _command == write;
- _reqinc == no;
- _arbit == accept;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_1p5
-
-
- // 1.6 Apply UART write request using one wrong space.
- class seq_1p6 extends uart_base_sequence;
-
- `uvm_object_utils(seq_1p6)
-
- function new (string name = "seq_1p6");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == text;
- (_spacetype1 == wrong_space) -> (_spacetype2 inside {tab, single});
- (_spacetype1 != wrong_space) -> (_spacetype2 == wrong_space);
- length_data == 1;
- _eoltype != wrong_eol;
- _command == write;
- _reqinc == no;
- _arbit == accept;
- };
- finish_item(trans);
- endtask:body
- endclass:seq_1p6
-
-
- // 1.7 Apply UART write request using two wrong spaces
- class seq_1p7 extends uart_base_sequence;
-
- `uvm_object_utils(seq_1p7)
-
- function new (string name = "seq_1p7");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == text;
- _spacetype1 == wrong_space;
- _spacetype2 == wrong_space;
- length_data == 1;
- _eoltype != wrong_eol;
- _command == write;
- _reqinc == no;
- _arbit == accept;
- };
- finish_item(trans);
- endtask:body
- endclass:seq_1p7
-
-
- // 1.8 Apply UART write request to address 0
- class seq_1p8 extends uart_base_sequence;
-
- `uvm_object_utils(seq_1p8)
-
- function new (string name = "seq_1p8");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == text;
- _spacetype1 != wrong_space;
- _spacetype2 != wrong_space;
- length_data == 1;
- _eoltype != wrong_eol;
- _command == write;
- address == 16'b0;
- _reqinc == no;
- _arbit == accept;
- };
- finish_item(trans);
- endtask:body
- endclass:seq_1p8
-
-
- // 1.9 Apply UART write request to full range address
- class seq_1p9 extends uart_base_sequence;
-
- `uvm_object_utils(seq_1p9)
-
- function new (string name = "seq_1p9");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == text;
- _spacetype1 != wrong_space;
- _spacetype2 != wrong_space;
- length_data == 1;
- _eoltype != wrong_eol;
- _command == write;
- address == 4'hFFFF;
- _reqinc == no;
- _arbit == accept;
- };
- finish_item(trans);
- endtask:body
- endclass:seq_1p9
-
-
- // 1.10 Apply UART write request with data equal 0.
- class seq_1p10 extends uart_base_sequence;
-
- `uvm_object_utils(seq_1p10)
-
- function new (string name = "seq_1p10");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == text;
- _spacetype1 != wrong_space;
- _spacetype2 != wrong_space;
- length_data == 1;
- _eoltype != wrong_eol;
- _command == write;
- _data [0] == 8'b0;
- _reqinc == no;
- _arbit == accept;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_1p10
-
-
- // 1.11 Apply UART write request with full range data.
- class seq_1p11 extends uart_base_sequence;
-
- `uvm_object_utils(seq_1p11)
-
- function new (string name = "seq_1p11");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == text;
- _spacetype1 != wrong_space;
- _spacetype2 != wrong_space;
- length_data == 1;
- _eoltype != wrong_eol;
- _command == write;
- _data [0] == 2'hff;
- _reqinc == no;
- _arbit == accept;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_1p11
-
-
-//-------------------------------------------------------
-//
-// READ IN TEXT MODE
-//
-//-------------------------------------------------------
-
- // 2.1 Apply UART read request using capital R
- class seq_2p1 extends uart_base_sequence;
-
- `uvm_object_utils(seq_2p1)
-
- function new (string name = "seq_2p1");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == text;
- _spacetype1 != wrong_space;
- _spacetype2 != wrong_space;
- length_data == 1;
- _eoltype != wrong_eol;
- _command == read;
- _reqinc == no;
- _arbit == accept;
- _chartype == cap;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_2p1
-
-
- // 2.2 Apply UART read request using small r
- class seq_2p2 extends uart_base_sequence;
-
- `uvm_object_utils(seq_2p2)
-
- function new (string name = "seq_2p2");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == text;
- _spacetype1 != wrong_space;
- _spacetype2 != wrong_space;
- length_data == 1;
- _eoltype != wrong_eol;
- _command == read;
- _reqinc == no;
- _arbit == accept;
- _chartype == smal;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_2p2
-
-
- // 2.3 Apply UART read request using single space only
- class seq_2p3 extends uart_base_sequence;
-
- `uvm_object_utils(seq_2p3)
-
- function new (string name = "seq_2p3");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == text;
- _spacetype1 == single;
- _spacetype2 == single;
- length_data == 1;
- _eoltype != wrong_eol;
- _command == read;
- _reqinc == no;
- _arbit == accept;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_2p3
-
-
- // 2.4 Apply UART read request using tab only.
- class seq_2p4 extends uart_base_sequence;
-
- `uvm_object_utils(seq_2p4)
-
- function new (string name = "seq_2p4");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == text;
- _spacetype1 == tab;
- _spacetype2 == tab;
- length_data == 1;
- _eoltype != wrong_eol;
- _command == read;
- _reqinc == no;
- _arbit == accept;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_2p4
-
-
- // 2.5 Apply UART read request using both single space and tab.
- class seq_2p5 extends uart_base_sequence;
-
- `uvm_object_utils(seq_2p5)
-
- function new (string name = "seq_2p5");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == text;
- _spacetype1 != wrong_space;
- _spacetype2 != wrong_space;
- _spacetype2 != _spacetype1;
- length_data == 1;
- _eoltype != wrong_eol;
- _command == read;
- _reqinc == no;
- _arbit == accept;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_2p5
-
-
- // 2.6 Apply UART read request using one wrong space.
- class seq_2p6 extends uart_base_sequence;
-
- `uvm_object_utils(seq_2p6)
-
- function new (string name = "seq_2p6");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == text;
- (_spacetype1 == wrong_space) -> (_spacetype2 inside {tab, single});
- (_spacetype1 != wrong_space) -> (_spacetype2 == wrong_space);
- length_data == 1;
- _eoltype != wrong_eol;
- _command == read;
- _reqinc == no;
- _arbit == accept;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_2p6
-
-
- // 2.7 Apply UART read request using two wrong spaces
- class seq_2p7 extends uart_base_sequence;
-
- `uvm_object_utils(seq_2p7)
-
- function new (string name = "seq_2p7");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == text;
- _spacetype1 == wrong_space;
- _spacetype2 == wrong_space;
- length_data == 1;
- _eoltype != wrong_eol;
- _command == read;
- _reqinc == no;
- _arbit == accept;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_2p7
-
-
- // 2.8 Apply UART read request to address 0
- class seq_2p8 extends uart_base_sequence;
-
- `uvm_object_utils(seq_2p8)
-
- function new (string name = "seq_2p8");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == text;
- _spacetype1 != wrong_space;
- _spacetype2 != wrong_space;
- length_data == 1;
- _eoltype != wrong_eol;
- _command == read;
- address == 16'b0;
- _reqinc == no;
- _arbit == accept;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_2p8
-
-
- // 2.9 Apply UART read request to full range address
- class seq_2p9 extends uart_base_sequence;
-
- `uvm_object_utils(seq_2p9)
-
- function new (string name = "seq_2p9");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == text;
- _spacetype1 != wrong_space;
- _spacetype2 != wrong_space;
- length_data == 1;
- _eoltype != wrong_eol;
- _command == read;
- address == 4'hFFFF;
- _reqinc == no;
- _arbit == accept;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_2p9
-
-
- // 2.10 Apply UART read request with data equal 0.
- class seq_2p10 extends uart_base_sequence;
-
- `uvm_object_utils(seq_2p10)
-
- function new (string name = "seq_2p10");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == text;
- _spacetype1 != wrong_space;
- _spacetype2 != wrong_space;
- length_data == 1;
- _eoltype != wrong_eol;
- _command == read;
- _data [0] == 8'b0;
- _reqinc == no;
- _arbit == accept;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_2p10
-
-
- // 2.11 Apply UART read request with full range data.
- class seq_2p11 extends uart_base_sequence;
-
- `uvm_object_utils(seq_2p11)
-
- function new (string name = "seq_2p11");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == text;
- _spacetype1 != wrong_space;
- _spacetype2 != wrong_space;
- length_data == 1;
- _eoltype != wrong_eol;
- _command == read;
- _data [0] == 2'hff;
- _reqinc == no;
- _arbit == accept;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_2p11
-
-//-------------------------------------------------------
-//
-// NOP IN COMMAND MODE
-//
-//-------------------------------------------------------
-
- // 3.1 Apply UART NOP command with acknowledge request and right command
- // mode prefix
- class seq_3p1 extends uart_base_sequence;
-
- `uvm_object_utils(seq_3p1)
-
- function new (string name = "seq_3p1");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == binary;
- _command == nop;
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- _reqack == yes;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_3p1
-
- // 3.2 Apply UART NOP command with acknowledge request and wrong command
- // mode prefix
- class seq_3p2 extends uart_base_sequence;
-
- `uvm_object_utils(seq_3p2)
-
- function new (string name = "seq_3p2");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == wrong_mode;
- _command == nop;
- address[15:7] != 2'h00;
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- _reqack == yes;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_3p2
-
- // 3.3 Apply several UART NOP command to different locations with different
- // data lengths
- class seq_3p3 extends uart_base_sequence;
-
- rand int unsigned num_of_comands;
-
- `uvm_object_utils(seq_3p3)
-
- function new (string name = "seq_3p3");
- super.new(name);
- endfunction:new
-
- constraint num_iter {
- num_of_comands inside {[1:5]};
- }
-
- virtual task body ();
- randomize();
- start_item(trans);
- repeat (num_of_comands)
- begin
- trans.randomize() with {
- _mode == binary;
- _command == nop;
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- _reqack == yes;
- } ;
- end
- finish_item(trans);
- endtask:body
- endclass:seq_3p3
-
- // 4.1 Apply UART NOP command with non-acknowledge request and right command
- // mode prefix
- class seq_4p1 extends uart_base_sequence;
-
- `uvm_object_utils(seq_4p1)
-
- function new (string name = "seq_4p1");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == binary;
- _command == nop;
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- _reqack == no;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_4p1
-
- // 4.2 Apply UART NOP command with non-acknowledge request and wrong command
- // mode prefix
- class seq_4p2 extends uart_base_sequence;
-
- `uvm_object_utils(seq_4p2)
-
- function new (string name = "seq_4p2");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == wrong_mode;
- _command == nop;
- address[15:7] != 2'h00;
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- _reqack == no;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_4p2
-
- // 4.3 Apply several UART NOP command to different locations with different
- // data lengths and non-acknowledge request
- class seq_4p3 extends uart_base_sequence;
-
- rand int unsigned num_of_comands;
-
- `uvm_object_utils(seq_4p3)
-
- function new (string name = "seq_4p3");
- super.new(name);
- endfunction:new
-
- constraint num_iter {
- num_of_comands inside {[1:5]};
- }
-
- virtual task body ();
- randomize();
- start_item(trans);
- repeat (num_of_comands)
- begin
- trans.randomize() with {
- _mode == binary;
- _command == nop;
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- _reqack == no;
- } ;
- end
- finish_item(trans);
- endtask:body
- endclass:seq_4p3
-
-//-------------------------------------------------------
-//
-// WRITE IN COMMAND MODE
-//
-//-------------------------------------------------------
-
- // 5.1 Apply UART write command with wrong prefix.
- class seq_5p1 extends uart_base_sequence;
-
- `uvm_object_utils(seq_5p1)
-
- function new (string name="seq_5p1");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == wrong_mode;
- _command == write;
- address[15:7] != 2'h00;
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_5p1
-
- // 5.2 Apply UART write commands to different addresses.
- class seq_5p2 extends uart_base_sequence;
-
- rand int unsigned num_of_comands;
-
- `uvm_object_utils(seq_5p2)
-
- function new (string name="seq_5p2");
- super.new(name);
- endfunction:new
-
- constraint num_iter {
- num_of_comands inside {[1:5]};
- }
-
- virtual task body ();
- randomize();
- start_item(trans);
- repeat (num_of_comands)
- begin
- trans.randomize() with {
- _mode == binary;
- _command == write;
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- };
- end
- finish_item(trans);
- endtask:body
- endclass:seq_5p2
-
- // 5.3 Apply UART write commands with several data lengths
- class seq_5p3 extends uart_base_sequence;
-
- rand int unsigned num_of_comands;
-
- `uvm_object_utils(seq_5p3)
-
- function new (string name="seq_5p3");
- super.new(name);
- endfunction:new
-
- constraint num_iter {
- num_of_comands inside {[1:5]};
- }
-
- virtual task body ();
- randomize();
- start_item(trans);
- repeat (num_of_comands)
- begin
- trans.randomize() with {
- _mode == binary;
- _command == write;
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- } ;
- end
- finish_item(trans);
- endtask:body
- endclass:seq_5p3
-
- // 5.4 Apply UART write command to address 0 with random data.
- class seq_5p4 extends uart_base_sequence;
-
- `uvm_object_utils(seq_5p4)
-
- function new (string name="seq_5p4");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == binary;
- _command == write;
- address == 16'b0;
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_5p4
-
- // 5.5 Apply UART write command to address 0xFFFF with random data.
- class seq_5p5 extends uart_base_sequence;
-
- `uvm_object_utils(seq_5p5)
-
- function new (string name="seq_5p5");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == binary;
- _command == write;
- address == 4'hffff;
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_5p5
-
- // 5.6 Apply UART write command with acknowledge request.
- class seq_5p6 extends uart_base_sequence;
-
- `uvm_object_utils(seq_5p6)
-
- function new (string name="seq_5p6");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == binary;
- _command == write;
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- _reqack == yes;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_5p6
-
- // 5.7 Apply UART write command with non-acknowledge request.
- class seq_5p7 extends uart_base_sequence;
-
- `uvm_object_utils(seq_5p7)
-
- function new (string name="seq_5p7");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == binary;
- _command == write;
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- _reqack == no;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_5p7
-
- // 5.8 Apply UART write command including single byte.
- class seq_5p8 extends uart_base_sequence;
-
- `uvm_object_utils(seq_5p8)
-
- function new (string name="seq_5p8");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == binary;
- _command == write;
- length_data == 1;
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_5p8
-
- // 5.9 Apply UART write command including non-incremental address bit.
- class seq_5p9 extends uart_base_sequence;
-
- `uvm_object_utils(seq_5p9)
-
- function new (string name="seq_5p9");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == binary;
- _command == write;
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- _reqinc == no;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_5p9
-
- // 5.10 Apply UART write command including incremental address bit.
- class seq_5p10 extends uart_base_sequence;
-
- `uvm_object_utils(seq_5p10)
-
- function new (string name="seq_5p10");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == binary;
- _command == write;
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- _reqinc == yes;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_5p10
-
-
-//-------------------------------------------------------
-//
-// READ IN COMMAND MODE
-//
-//-------------------------------------------------------
-
- // 6.1 Apply UART read command with wrong prefix.
- class seq_6p1 extends uart_base_sequence;
-
- `uvm_object_utils(seq_6p1)
-
- function new (string name="seq_6p1");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == wrong_mode;
- _command == read;
- address[15:7] != 2'h00;
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_6p1
-
- // 6.2 Apply UART read commands to different addresses.
- class seq_6p2 extends uart_base_sequence;
-
- rand int unsigned num_of_comands;
-
- `uvm_object_utils(seq_6p2)
-
- function new (string name="seq_6p2");
- super.new(name);
- endfunction:new
-
- constraint num_iter {
- num_of_comands inside {[1:5]};
- }
-
- virtual task body ();
- randomize();
- start_item(trans);
- repeat (num_of_comands)
- begin
- trans.randomize() with {
- _mode == binary;
- _command == read;
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- } ;
- end
- finish_item(trans);
- endtask:body
- endclass:seq_6p2
-
- // 6.3 Apply UART read commands with several data lengths
- class seq_6p3 extends uart_base_sequence;
-
- rand int unsigned num_of_comands;
-
- `uvm_object_utils(seq_6p3)
-
- function new (string name="seq_6p3");
- super.new(name);
- endfunction:new
-
- constraint num_iter {
- num_of_comands inside {[1:5]};
- }
-
- virtual task body ();
- randomize();
- start_item(trans);
- repeat (num_of_comands)
- begin
- trans.randomize() with {
- _mode == binary;
- _command == read;
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- } ;
- end
- finish_item(trans);
- endtask:body
- endclass:seq_6p3
-
- // 6.4 Apply UART read command to address 0 with random data.
- class seq_6p4 extends uart_base_sequence;
-
- `uvm_object_utils(seq_6p4)
-
- function new (string name="seq_6p4");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == binary;
- _command == read;
- address == 16'b0;
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_6p4
-
- // 6.5 Apply UART read command to address 0xFFFF with random data.
- class seq_6p5 extends uart_base_sequence;
-
- `uvm_object_utils(seq_6p5)
-
- function new (string name="seq_6p5");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == binary;
- _command == read;
- address == 4'hffff;
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_6p5
-
- // 6.6 Apply UART read command with acknowledge request.
- class seq_6p6 extends uart_base_sequence;
-
- `uvm_object_utils(seq_6p6)
-
- function new (string name="seq_6p6");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == binary;
- _command == read;
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- _reqack == yes;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_6p6
-
- // 6.7 Apply UART read command with non-acknowledge request.
- class seq_6p7 extends uart_base_sequence;
-
- `uvm_object_utils(seq_6p7)
-
- function new (string name="seq_6p7");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == binary;
- _command == read;
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- _reqack == no;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_6p7
-
- // 6.8 Apply UART read command including single byte.
- class seq_6p8 extends uart_base_sequence;
-
- `uvm_object_utils(seq_6p8)
-
- function new (string name="seq_6p8");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == binary;
- _command == read;
- length_data == 1;
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_6p8
-
- // 6.9 Apply UART read command including non-incremental address bit.
- class seq_6p9 extends uart_base_sequence;
-
- `uvm_object_utils(seq_6p9)
-
- function new (string name="seq_6p9");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == binary;
- _command == read;
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- _reqinc == no;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_6p9
-
- // 6.10 Apply UART read command including incremental address bit.
- class seq_6p10 extends uart_base_sequence;
-
- `uvm_object_utils(seq_6p10)
-
- function new (string name="seq_6p10");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == binary;
- _command == read;
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- _reqinc == yes;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_6p10
-
-//-------------------------------------------------------
-//
-// INTERNAL BUS
-//
-//-------------------------------------------------------
-
- // 7.1 Apply UART read or write commands and give the UART the bus grant.
- class seq_7p1 extends uart_base_sequence;
-
- `uvm_object_utils(seq_7p1)
-
- function new (string name="seq_7p1");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == binary;
- _command inside {write,read};
- (length_data > 1) -> (_reqinc == yes);
- _arbit == accept;
- _reqinc == yes;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_7p1
-
- // 7.2 Apply UART read or write commands and give no agreement to access internal bus
- class seq_7p2 extends uart_base_sequence;
-
- `uvm_object_utils(seq_7p2)
-
- function new (string name="seq_7p2");
- super.new(name);
- endfunction:new
-
- virtual task body ();
- start_item(trans);
- trans.randomize() with {
- _mode == binary;
- _command inside {write,read};
- (length_data > 1) -> (_reqinc == yes);
- _arbit == declain;
- _reqinc == yes;
- } ;
- finish_item(trans);
- endtask:body
- endclass:seq_7p2
\ No newline at end of file
trunk/tb/agent/sequence/uart_sequence.svh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/tb/agent/uart_agent.svh
===================================================================
--- trunk/tb/agent/uart_agent.svh (revision 2)
+++ trunk/tb/agent/uart_agent.svh (nonexistent)
@@ -1,64 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// UART2BUS VERIFICATION
-//
-//-----------------------------------------------------------------------------
-// CREATOR : HANY SALAH
-// PROJECT : UART2BUS UVM TEST BENCH
-// UNIT : AGENT
-//-----------------------------------------------------------------------------
-// TITLE : UART AGENT
-// DESCRIPTION: This
-//-----------------------------------------------------------------------------
-// LOG DETAILS
-//-------------
-// VERSION NAME DATE DESCRIPTION
-// 1 HANY SALAH 10012016 FILE CREATION
-//-----------------------------------------------------------------------------
-// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
-// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
-// CREATOR'S PERMISSION
-//-----------------------------------------------------------------------------
-
-class uart_agent extends uvm_agent;
-
- uart_driver _drv;
-
- uvm_sequencer#(uart_transaction) _seq;
-
- uart_monitor _mon;
-
- uvm_analysis_port #(uart_transaction) drv_port;
-
- uvm_analysis_port #(uart_transaction) mon_port;
-
- `uvm_component_utils(uart_agent)
-
- function new (string name,uvm_component parent);
- super.new(name,parent);
- endfunction:new
-
-
- extern function void build_phase (uvm_phase phase);
-
- extern function void connect_phase (uvm_phase phase);
-endclass:uart_agent
-
-function void uart_agent::build_phase (uvm_phase phase);
- super.build_phase(phase);
- _drv = uart_driver::type_id::create("_drv",this);
- _seq = uvm_sequencer#(uart_transaction)::type_id::create("_seq",this);
- _mon = uart_monitor::type_id::create("_mon",this);
-
- drv_port = new ("drv_port",this);
- mon_port = new ("mon_port",this);
-endfunction:build_phase
-
-function void uart_agent::connect_phase (uvm_phase phase);
- super.connect_phase(phase);
- _drv.seq_item_port.connect(_seq.seq_item_export);
-
- _drv.drv_scbd_cov.connect(drv_port);
-
- _mon.mon_scbd.connect(mon_port);
-endfunction:connect_phase
\ No newline at end of file
trunk/tb/agent/uart_agent.svh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/tb/agent/driver/uart_driver.svh
===================================================================
--- trunk/tb/agent/driver/uart_driver.svh (revision 2)
+++ trunk/tb/agent/driver/uart_driver.svh (nonexistent)
@@ -1,268 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// UART2BUS VERIFICATION
-//
-//-----------------------------------------------------------------------------
-// CREATOR : HANY SALAH
-// PROJECT : UART2BUS UVM TEST BENCH
-// UNIT : DRIVER
-//-----------------------------------------------------------------------------
-// TITLE : UART Driver
-// DESCRIPTION: This
-//-----------------------------------------------------------------------------
-// LOG DETAILS
-//-------------
-// VERSION NAME DATE DESCRIPTION
-// 1 HANY SALAH 02012016 FILE CREATION
-// 2 HANY SALAH 07012016 ADD INITIALIZE BFM METHOD
-//-----------------------------------------------------------------------------
-// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
-// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
-// CREATOR'S PERMISSION
-//-----------------------------------------------------------------------------
-
-class uart_driver extends uvm_driver #(uart_transaction);
-
- // Two Transaction Instances that are used to bring and clone the
- // stimulus
- uart_transaction trans,_trans;
-
- // Instance from Global UART Configuration
- uart_config _config;
-
- // UART Interafce instance
- virtual uart_interface uart_inf;
-
- // RF Interface instance
- virtual rf_interface rf_inf;
-
- // Arbiter Interface Instance
- virtual uart_arbiter arb_inf;
-
- uvm_analysis_port #(uart_transaction) drv_scbd_cov;
-
- `uvm_component_utils(uart_driver)
-
- function new (string name , uvm_component parent);
- super.new(name,parent);
- endfunction: new
-
- function void display_content ();
- $display("here %s\n command_type = %p \n command = %p \n char_type = %p \n space_type1 = %p \n space_wrong1 = %8b \n space_type2 = %p \n space_wrong2 = %8b \n eol_type = %p \n eol_wrong = %8b \n address = %h \n data = %8b", get_full_name(),trans._mode,
- trans._command,
- trans._chartype,
- trans._spacetype1,
- trans.space_wrong1,
- trans._spacetype2,
- trans.space_wrong2,
- trans._eoltype,
- trans.eol_wrong,
- trans.address,
- trans._data[0]);
- endfunction:display_content
-
- // UVM Build Phase Declaration that includes locating instances and get
- // interfaces handler from the configuration database
- extern function void build_phase (uvm_phase phase);
-
- extern function void end_of_elaboration_phase (uvm_phase phase);
-
- // UVM Run Phase Declaratio
- extern task run_phase (uvm_phase phase);
-
- // Actual drive data routine
- extern task drive_data (int iteration);
-
- // initialize bfms
- extern function void initialize_bfms (act_edge _edge,
- start_bit _bit,
- int num_stop_bits,
- int num_of_bits,
- data_mode _datamode,
- parity_mode _paritymode,
- time _resp);
-endclass:uart_driver
-
-function void uart_driver::build_phase (uvm_phase phase);
- super.build_phase(phase);
-
- trans = uart_transaction::type_id::create("trans");
- _trans = uart_transaction::type_id::create("_trans");
-
- _config = uart_config::type_id::create("_config");
-
- drv_scbd_cov = new("drv_scbd_cov",this);
-
-endfunction:build_phase
-
-function void uart_driver::end_of_elaboration_phase (uvm_phase phase);
-
- if(!uvm_config_db#(uart_config)::get(this, "", "UART_CONFIGURATION", _config))
- `uvm_fatal("NOCONFIGURATION",{"configuration instance must be set for: ",get_full_name(),"._config"});
-
- if(!uvm_config_db#(virtual uart_interface)::get(this, "", "uart_inf", _config.uart_inf))
- `uvm_fatal("NOVIF",{"virtual interface must be set for: ",get_full_name(),".uart_inf"});
- uart_inf=_config.uart_inf;
-
- if(!uvm_config_db#(virtual rf_interface)::get(this, "", "rf_inf", _config.rf_inf))
- `uvm_fatal("NOVIF",{"virtual interface must be set for: ",get_full_name(),".rf_inf"});
- rf_inf=_config.rf_inf;
-
- if(!uvm_config_db#(virtual uart_arbiter)::get(this,"","arb_inf",_config.arb_inf))
- `uvm_fatal("NOVIF",{"virtual interface must be set for:",get_full_name(),".arb_inf"})
- arb_inf=_config.arb_inf;
-
-endfunction:end_of_elaboration_phase
-
-function void uart_driver::initialize_bfms (act_edge _edge,
- start_bit _bit,
- int num_stop_bits,
- int num_of_bits,
- data_mode _datamode,
- parity_mode _paritymode,
- time _resp);
- uart_inf.set_configuration(_edge,_bit,num_stop_bits,num_of_bits,_datamode,_paritymode,_resp);
-endfunction:initialize_bfms
-
-task uart_driver::run_phase (uvm_phase phase);
-
- int iteration;
- iteration = 0;
-
- initialize_bfms(_config._edge,
- _config._start,
- _config.num_stop_bits,
- _config.num_of_bits,
- _config._datamode,
- _config._paritymode,
- _config.response_time);
-
- forever
- begin
- iteration++;
- if (iteration == 3)
- begin
- //$stop;
- end
- seq_item_port.get_next_item(_trans);
- $cast(trans,_trans.clone());
- drv_scbd_cov.write(trans);
- //display_content();
- drive_data(iteration);
- seq_item_port.item_done();
- end
-endtask:run_phase
-
-task uart_driver::drive_data(int iteration);
- uart_inf.wait_idle_time(trans.time_before*trans.scale);
- uart_inf.set_event();
- case (trans._mode)
- text:
- begin
- case(trans._command)
- read:
- begin
- fork
- begin
- if (trans._arbit == accept)
- begin
- arb_inf.accept_req();
- end
- else
- begin
- arb_inf.declain_req();
- end
- end
- join_none
- rf_inf.fill_byte (trans.address,
- trans._data[0]);
- uart_inf.read_text_mode(trans._chartype,
- trans._spacetype1,
- trans.space_wrong1,
- trans._eoltype,
- trans.eol_wrong,
- trans.address);
- end
- write:
- begin
- fork
- begin
- if (trans._arbit == accept)
- begin
- arb_inf.accept_req();
- end
- else
- begin
- arb_inf.declain_req();
- end
- end
- join_none
- uart_inf.write_text_mode(trans._chartype,
- trans._spacetype1,
- trans.space_wrong1,
- trans._spacetype2,
- trans.space_wrong2,
- trans._eoltype,
- trans.eol_wrong,
- trans.address,
- trans._data[0]);
- end
- nop:
- begin
- `uvm_fatal("UNEXPECTED VALUE","NOP command value shouldn't be valued in text mode")
- end
- default:
- begin
- `uvm_fatal("wrong output", "wrong_mode")
- end
- endcase
- end
- binary:
- begin
- case(trans._command)
- read:
- begin
- rf_inf.fill_block(trans.address,
- trans._data,
- trans.length_data);
- uart_inf.read_binary_mode(trans._reqack,
- trans._reqinc,
- trans.length_data,
- trans.address,
- trans._data);
- end
- write:
- begin
- uart_inf.write_binary_mode(trans._reqack,
- trans._reqinc,
- trans.length_data,
- trans.address,
- trans._data);
- end
- nop:
- begin
- uart_inf.nop_command(trans._reqack,
- trans._reqinc);
- end
- default:
- begin
- `uvm_fatal("UNDEFINED COMMAND","Binary command should be either read or write or no operation")
- end
- endcase
- end
- wrong_mode:
- begin
- uart_inf.wrong_command(trans._reqack,
- trans._reqinc,
- trans.space_wrong1,
- trans.length_data,
- trans.address,
- trans._data);
- end
- default:
- begin
- `uvm_fatal("UNEXPECTED VALUE","Command should be text or command or wrong")
- end
- endcase
- uart_inf.wait_idle_time(trans.time_after*trans.scale);
-endtask:drive_data
\ No newline at end of file
trunk/tb/agent/driver/uart_driver.svh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/tb/test/uart_test.svh
===================================================================
--- trunk/tb/test/uart_test.svh (revision 2)
+++ trunk/tb/test/uart_test.svh (nonexistent)
@@ -1,317 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// UART2BUS VERIFICATION
-//
-//-----------------------------------------------------------------------------
-// CREATOR : HANY SALAH
-// PROJECT : UART2BUS UVM TEST BENCH
-// UNIT : TEST
-//-----------------------------------------------------------------------------
-// TITLE : UART TEST
-// DESCRIPTION: This
-//-----------------------------------------------------------------------------
-// LOG DETAILS
-//-------------
-// VERSION NAME DATE DESCRIPTION
-// 1 HANY SALAH 10012016 FILE CREATION
-//-----------------------------------------------------------------------------
-// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
-// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
-// CREATOR'S PERMISSION
-//-----------------------------------------------------------------------------
-class uart_base_test extends uvm_test;
-
- uart_env env;
-
- uvm_table_printer printer;
-
- uart_config _config;
-
- `uvm_component_utils(uart_base_test)
-
- function new (string name,uvm_component parent);
- super.new(name,parent);
- endfunction:new
-
- function void build_phase (uvm_phase phase);
- super.build_phase(phase);
-
- env = uart_env::type_id::create("env",this);
-
- _config = uart_config::type_id::create("_config",this);
-
- uvm_config_db#(uart_config)::set(this,"*","UART_CONFIGURATION",_config);
-
- printer = new();
- printer.knobs.depth = 3;
- endfunction:build_phase
-
- function void connect_phase (uvm_phase phase);
- super.connect_phase(phase);
- endfunction:connect_phase
-
- function void end_of_elaboration_phase (uvm_phase phase);
- super.end_of_elaboration_phase(phase);
- _config._edge = pos_edge;
- _config._start = lsb;
- _config._datamode = ascii;
- _config.num_stop_bits = 1;
- _config.num_of_bits = 8;
- _config._paritymode = parity_off;
- _config.response_time = 10000;
- endfunction:end_of_elaboration_phase
-
- task run_phase (uvm_phase phase);
- phase.phase_done.set_drain_time(this,5000);
- endtask:run_phase
-endclass:uart_base_test
-
-
-class write_text_mode extends uart_base_test;
-
- seq_1p1 seq1;
- seq_1p2 seq2;
- seq_1p3 seq3;
- seq_1p4 seq4;
- seq_1p5 seq5;
- seq_1p6 seq6;
- seq_1p7 seq7;
- seq_1p8 seq8;
- seq_1p9 seq9;
- seq_1p10 seq10;
- seq_1p11 seq11;
-
- `uvm_component_utils(write_text_mode)
-
- function new (string name,uvm_component parent);
- super.new(name,parent);
- endfunction:new
-
- function void build_phase (uvm_phase phase);
- super.build_phase (phase);
- seq1 = seq_1p1::type_id::create("seq1");
- seq2 = seq_1p2::type_id::create("seq2");
- seq3 = seq_1p3::type_id::create("seq3");
- seq4 = seq_1p4::type_id::create("seq4");
- seq5 = seq_1p5::type_id::create("seq5");
- seq6 = seq_1p6::type_id::create("seq6");
- seq7 = seq_1p7::type_id::create("seq7");
- seq8 = seq_1p8::type_id::create("seq8");
- seq9 = seq_1p9::type_id::create("seq9");
- seq10 = seq_1p10::type_id::create("seq10");
- seq11 = seq_1p11::type_id::create("seq11");
- endfunction:build_phase
-
-
- task run_phase (uvm_phase phase);
- super.run_phase(phase);
- phase.raise_objection(this);
- seq1.start(env.agent._seq,null);
- seq2.start(env.agent._seq,null);
- seq3.start(env.agent._seq,null);
- seq4.start(env.agent._seq,null);
- seq5.start(env.agent._seq,null);
- seq6.start(env.agent._seq,null);
- seq7.start(env.agent._seq,null);
- seq8.start(env.agent._seq,null);
- seq9.start(env.agent._seq,null);
- seq10.start(env.agent._seq,null);
- seq11.start(env.agent._seq,null);
- phase.drop_objection(this);
- endtask:run_phase
-endclass:write_text_mode
-
-
-class read_text_mode extends uart_base_test;
-
- seq_2p1 seq1;
- seq_2p2 seq2;
- seq_2p3 seq3;
- seq_2p4 seq4;
- seq_2p5 seq5;
- seq_2p6 seq6;
- seq_2p7 seq7;
- seq_2p8 seq8;
- seq_2p9 seq9;
- seq_2p10 seq10;
- seq_2p11 seq11;
-
-
- `uvm_component_utils(read_text_mode)
-
- function new (string name,uvm_component parent);
- super.new(name,parent);
- endfunction:new
-
- function void build_phase (uvm_phase phase);
- super.build_phase(phase);
- seq1 = seq_2p1::type_id::create("seq1");
- seq2 = seq_2p2::type_id::create("seq2");
- seq3 = seq_2p3::type_id::create("seq3");
- seq4 = seq_2p4::type_id::create("seq4");
- seq5 = seq_2p5::type_id::create("seq5");
- seq6 = seq_2p6::type_id::create("seq6");
- seq7 = seq_2p7::type_id::create("seq7");
- seq8 = seq_2p8::type_id::create("seq8");
- seq9 = seq_2p9::type_id::create("seq9");
- seq10 = seq_2p10::type_id::create("seq10");
- seq11 = seq_2p11::type_id::create("seq11");
- endfunction:build_phase
-
- task run_phase (uvm_phase phase);
- super.run_phase(phase);
- phase.raise_objection(this);
- seq1.start(env.agent._seq,null);
- seq2.start(env.agent._seq,null);
- seq3.start(env.agent._seq,null);
- seq4.start(env.agent._seq,null);
- seq5.start(env.agent._seq,null);
- seq6.start(env.agent._seq,null);
- seq7.start(env.agent._seq,null);
- seq8.start(env.agent._seq,null);
- seq9.start(env.agent._seq,null);
- seq10.start(env.agent._seq,null);
- seq11.start(env.agent._seq,null);
- phase.drop_objection(this);
- endtask:run_phase
-endclass:read_text_mode
-
-class nop_command_mode extends uart_base_test;
-
- seq_3p1 seq1;
- //seq_3p2 seq2;
- seq_3p3 seq3;
- seq_4p1 seq4;
- //seq_4p2 seq5;
- seq_4p3 seq6;
-
- `uvm_component_utils(nop_command_mode)
-
- function new (string name,uvm_component parent);
- super.new(name,parent);
- endfunction:new
-
- function void build_phase (uvm_phase phase);
- super.build_phase(phase);
- seq1 = seq_3p1::type_id::create("seq1");
- //seq2 = seq_3p2::type_id::create("seq2");
- seq3 = seq_3p3::type_id::create("seq3");
- seq4 = seq_4p1::type_id::create("seq4");
- //seq5 = seq_4p2::type_id::create("seq5");
- seq6 = seq_4p3::type_id::create("seq6");
- endfunction:build_phase
-
- task run_phase(uvm_phase phase);
- super.run_phase(phase);
- phase.raise_objection(this);
- seq1.start(env.agent._seq,null);
- //seq2.start(env.agent._seq,null);
- seq3.start(env.agent._seq,null);
- seq4.start(env.agent._seq,null);
- //seq5.start(env.agent._seq,null);
- seq6.start(env.agent._seq,null);
- phase.drop_objection(this);
- endtask:run_phase
-endclass:nop_command_mode
-
-class write_command_mode extends uart_base_test;
-
- seq_5p1 seq1;
- seq_5p2 seq2;
- seq_5p3 seq3;
- seq_5p4 seq4;
- seq_5p5 seq5;
- seq_5p6 seq6;
- seq_5p7 seq7;
- seq_5p8 seq8;
- seq_5p9 seq9;
- seq_5p10 seq10;
-
- `uvm_component_utils(write_command_mode)
-
- function new (string name,uvm_component parent);
- super.new(name,parent);
- endfunction:new
-
- function void build_phase (uvm_phase phase);
- super.build_phase(phase);
- seq1 = seq_5p1::type_id::create("seq1");
- seq2 = seq_5p2::type_id::create("seq2");
- seq3 = seq_5p3::type_id::create("seq3");
- seq4 = seq_5p4::type_id::create("seq4");
- seq5 = seq_5p5::type_id::create("seq5");
- seq6 = seq_5p6::type_id::create("seq6");
- seq7 = seq_5p7::type_id::create("seq7");
- seq8 = seq_5p8::type_id::create("seq8");
- seq9 = seq_5p9::type_id::create("seq9");
- seq10 = seq_5p10::type_id::create("seq10");
- endfunction:build_phase
-
- task run_phase (uvm_phase phase);
- super.run_phase(phase);
- phase.raise_objection(this);
- uvm_test_done.set_drain_time(this,5000);
- seq1.start(env.agent._seq,null);
- seq2.start(env.agent._seq,null);
- seq3.start(env.agent._seq,null);
- seq4.start(env.agent._seq,null);
- seq5.start(env.agent._seq,null);
- seq6.start(env.agent._seq,null);
- seq7.start(env.agent._seq,null);
- seq8.start(env.agent._seq,null);
- seq9.start(env.agent._seq,null);
- seq10.start(env.agent._seq,null);
- phase.drop_objection(this);
- endtask:run_phase
-endclass: write_command_mode
-
-class read_command_mode extends uart_base_test;
-
- seq_6p1 seq1;
- seq_6p2 seq2;
- seq_6p3 seq3;
- seq_6p4 seq4;
- seq_6p5 seq5;
- seq_6p6 seq6;
- seq_6p7 seq7;
- seq_6p8 seq8;
- seq_6p9 seq9;
- seq_6p10 seq10;
-
- `uvm_component_utils(read_command_mode)
-
- function new (string name,uvm_component parent);
- super.new(name,parent);
- seq1 = seq_6p1::type_id::create("seq1");
- seq2 = seq_6p2::type_id::create("seq2");
- seq3 = seq_6p3::type_id::create("seq3");
- seq4 = seq_6p4::type_id::create("seq4");
- seq5 = seq_6p5::type_id::create("seq5");
- seq6 = seq_6p6::type_id::create("seq6");
- seq7 = seq_6p7::type_id::create("seq7");
- seq8 = seq_6p8::type_id::create("seq8");
- seq9 = seq_6p9::type_id::create("seq9");
- seq10 = seq_6p10::type_id::create("seq10");
- endfunction:new
-
- function void build_phase (uvm_phase phase);
- super.build_phase(phase);
-
- endfunction:build_phase
-
- task run_phase (uvm_phase phase);
- super.run_phase(phase);
- phase.raise_objection(this);
- seq1.start(env.agent._seq,null);
- seq2.start(env.agent._seq,null);
- seq3.start(env.agent._seq,null);
- seq4.start(env.agent._seq,null);
- seq5.start(env.agent._seq,null);
- seq6.start(env.agent._seq,null);
- seq7.start(env.agent._seq,null);
- seq8.start(env.agent._seq,null);
- seq9.start(env.agent._seq,null);
- seq10.start(env.agent._seq,null);
- phase.drop_objection(this);
- endtask:run_phase
-endclass:read_command_mode
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trunk/tb/test/uart_test.svh
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Deleted: svn:executable
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-*
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