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URL https://opencores.org/ocsvn/uart2bus_testbench/uart2bus_testbench/trunk

Subversion Repositories uart2bus_testbench

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  • This comparison shows the changes necessary to convert path 
    /uart2bus_testbench
    from Rev 13 to Rev 14
    ↔ Reverse comparison
  •

Rev 13 → Rev 14

/trunk/doc/.~lock.uart2bus_verification_plan.odt#
1,?rev1len? → ?rev2line?,?rev2len?
,hany,hany-Inspiron-3542,23.06.2017 01:29,file:///home/hany/.config/libreoffice/4;
,hany,hany-Inspiron-3542,26.06.2017 15:12,file:///home/hany/.config/libreoffice/4;
/trunk/doc/uart2bus_verification_plan.odt Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/doc/uart2bus_verification_plan.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/tb/agent/coverage/uart_coverage.svh
31,14 → 31,11
communication_mode:
coverpoint trans._mode{
bins valid_mode = {text,binary};
bins invalid_mode = {wrong_mode_text,wrong_mode_bin};
illegal_bins invalid_mode = {wrong_mode_text,wrong_mode_bin};
}
address:
coverpoint trans.address;
false_data:
coverpoint trans.false_data_en;
unknown_prefix:
coverpoint trans.wrong_prefix;
 
endgroup:trans_attrib
 
covergroup text_mode_cov;
48,13 → 45,17
illegal_bins invalid_command={nop,invalid_read,invalid_write};
}
first_white_space_field:
coverpoint trans._spacetype1;
coverpoint trans._spacetype1{bins validspace ={single,tab};
illegal_bins invalidspace ={wrong_space};}
second_white_space_field:
coverpoint trans._spacetype2;
coverpoint trans._spacetype2{bins validspace ={single,tab};
illegal_bins invalidspace ={wrong_space};}
end_of_line_field:
coverpoint trans._eoltype;
coverpoint trans._eoltype{bins valideol={cr,lf};
illegal_bins eol ={wrong_eol};}
prefix_character_type:
coverpoint trans._chartype;
endgroup:text_mode_cov
 
covergroup binary_mode_cov;
61,7 → 62,7
command:
coverpoint trans._command{
bins normal_command={read,2,nop};
bins wrong_command ={invalid_read,invalid_write};
illegal_bins wrong_command ={invalid_read,invalid_write};
}
acknowledge_requirement:
coverpoint trans._reqack;
105,7 → 106,6
endfunction:build_phase
 
function void uart_coverage::connect_phase(uvm_phase phase);
// cov_mon.connect(mon_fifo.analysis_export);
endfunction:connect_phase
 
task uart_coverage::run_phase(uvm_phase phase);
114,7 → 114,8
 
function void uart_coverage::write(uart_transaction t);
$cast(trans,t.clone());
trans_attrib.sample();
trans_attrib.sample();
uvm_resource_db#(int)::write_by_name("coverage_cloud","general_coverage",trans_attrib.get_coverage());
if(trans._mode == text)
begin
text_mode_cov.sample();
123,5 → 124,6
else if (trans._mode == binary)
begin
binary_mode_cov.sample();
uvm_resource_db#(int)::write_by_name("coverage_cloud","binary_coverage",binary_mode_cov.get_coverage());
end
endfunction // write
/trunk/tb/agent/driver/uart_driver.svh
142,18 → 142,6
case(trans._command)
read:
begin
/*fork
begin
if (trans._arbit == accept)
begin
arb_inf.accept_req();
end
else
begin
arb_inf.declain_req();
end
end
join_none*/
rf_inf.fill_byte (trans.address,
trans._data[0]);
uart_inf.read_text_mode(trans._mode,
170,18 → 158,6
end
write:
begin
/*fork
begin
if (trans._arbit == accept)
begin
arb_inf.accept_req();
end
else
begin
arb_inf.declain_req();
end
end
join_none*/
uart_inf.write_text_mode(trans._mode,
trans.wrong_prefix,
trans._chartype,
197,11 → 173,11
end
nop:
begin
`uvm_fatal("UNEXPECTED VALUE","NOP command value shouldn't be valued in text mode")
`uvm_fatal("TB ISSUE","NOP command value shouldn't be valued in text mode")
end
default:
begin
`uvm_fatal("wrong output", "wrong_mode")
`uvm_fatal("TB ISSUE", "wrong_mode")
end
endcase
end
244,4 → 220,4
 
end
uart_inf.wait_idle_time(trans.time_after*trans.scale);
endtask:drive_data
endtask:drive_data
/trunk/tb/agent/monitor/uart_monitor.svh
40,17 → 40,8
endfunction:new
 
function void display_content ();
$display("here %s\n command_type = %p \n command = %p \n char_type = %p \n space_type1 = %p \n space_wrong1 = %8b \n space_type2 = %p \n space_wrong2 = %8b \n eol_type = %p \n eol_wrong = %8b \n address = %h \n data = %8b", get_full_name(),trans._mode,
trans._command,
trans._chartype,
trans._spacetype1,
trans.space_wrong1,
trans._spacetype2,
trans.space_wrong2,
trans._eoltype,
trans.eol_wrong,
trans.address,
trans._data[0]);
`uvm_info("TRACE","Printing the transaction content:",UVM_HIGH);
trans.print();
endfunction:display_content
 
extern function void build_phase (uvm_phase phase);
107,7 → 98,6
forever
begin
iteration++;
//trans.reset_fields();
uart_inf.wait_event();
trans.acknowledge=8'b00;
 
/trunk/tb/agent/sequence/uart_sequence.svh
764,7 → 764,6
_arbit == accept;
_reqack == yes;
} ;
$display("reached here sequence @time=%0t ,, _mode = %p",$time,trans._mode);
finish_item(trans);
endtask:body
endclass:seq_3p1
1492,4 → 1491,4
} ;
finish_item(trans);
endtask:body
endclass:seq_8p2
endclass:seq_8p2
/trunk/tb/agent/transaction/uart_transaction.svh
18,6 → 18,7
// 2 HANY SALAH 01012016 COMPLETE ATTRIBUTES
// 3 HANY SALAH 26012016 ADD VALID TRANSACTION CONSTRAINTS
// 4 HANY SALAH 11022016 IMPROVE BLOCK DESCRIPTION AND ADD CODING COMMENTS
// 5 HANY SALAH 25062017 ADD DO_COPY, DO_COMPARE METHODS
//-------------------------------------------------------------------------------------------------
// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR OPENCORES MEMBERS
// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION
80,7 → 81,7
rand req false_data_en;
 
// Represents random idle time before and after the UART stimulus
rand time time_before,time_after;
rand int time_before,time_after;
 
// Represents the acknowledge byte driven by the DUT
byte acknowledge;
91,8 → 92,33
// Represent the scale that is used to scale the idle time values described above
int unsigned scale = 100;
 
`uvm_object_utils(uart_transaction)
 
`uvm_object_utils_begin(uart_transaction)
`uvm_field_int(wrong_prefix,UVM_ALL_ON)
`uvm_field_enum(mode,_mode,UVM_ALL_ON)
`uvm_field_enum(eol_type,_eoltype,UVM_ALL_ON)
`uvm_field_enum(space_type,_spacetype1,UVM_ALL_ON)
`uvm_field_enum(space_type,_spacetype2,UVM_ALL_ON)
`uvm_field_enum(command,_command,UVM_ALL_ON)
`uvm_field_enum(req,_reqack,UVM_ALL_ON)
`uvm_field_enum(req,_reqinc,UVM_ALL_ON)
`uvm_field_enum(char_type,_chartype,UVM_ALL_ON)
`uvm_field_enum(arbit,_arbit,UVM_ALL_ON)
`uvm_field_enum(req,false_data_en,UVM_ALL_ON)
`uvm_field_int(wrong_prefix,UVM_ALL_ON)
`uvm_field_int(space_wrong1,UVM_ALL_ON)
`uvm_field_int(space_wrong2,UVM_ALL_ON)
`uvm_field_array_int(_data,UVM_ALL_ON)
`uvm_field_array_int(false_data,UVM_ALL_ON)
`uvm_field_int(length_data,UVM_ALL_ON)
`uvm_field_int(eol_wrong,UVM_ALL_ON)
`uvm_field_int(address,UVM_ALL_ON)
`uvm_field_int(time_before,UVM_ALL_ON)
`uvm_field_int(time_after,UVM_ALL_ON)
`uvm_field_int(acknowledge,UVM_ALL_ON)
`uvm_field_int(_id,UVM_ALL_ON)
`uvm_field_int(scale,UVM_ALL_ON)
`uvm_object_utils_end
function new (string name ="uart_transaction");
super.new(name);
endfunction: new
148,7 → 174,9
 
extern function void do_copy (uvm_object rhs);
 
extern function bit do_compare(uvm_object rhs);
//extern function bit do_compare(uvm_object rhs);
 
extern function void do_print(uvm_printer printer=null);
endclass:uart_transaction
186,7 → 214,7
endfunction:do_copy
 
 
function bit uart_transaction::do_compare(uvm_object rhs,
/*function bit uart_transaction::do_compare(uvm_object rhs,
uvm_comparer comparer);
uart_transaction t;
do_compare=super.do_compare(rhs,comparer);
213,4 → 241,8
do_compare &= comparer.compare_field_ ("false_data",false_data, rhs.false_data);
do_compare &= comparer.compare_field_ ("false_data_en",false_data_en, rhs.false_data_en);
do_compare &= comparer.compare_field_ ("_id",_id, rhs._id);
endfunction // do_compare
endfunction // do_compare*/
 
function void uart_transaction::do_print(uvm_printer printer=null);
super.do_print(printer);
endfunction // do_print
/trunk/tb/test/uart_test.svh
20,6 → 20,7
// 1 HANY SALAH 10012016 FILE CREATION
// 2 HANY SALAH 20012016 ADD BINARY MODE TESTS AND INVALID TESTS
// 3 HANY SALAH 12022016 IMPROVE BLOCK DESCRIPTION & ADD COMMENTS
// 4 HANY SALAH 26062017 ADD COVERAGE DRIVEN TEST
//-------------------------------------------------------------------------------------------------
// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR OPENCORES MEMBERS
// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION
65,6 → 66,10
int matched ;
 
uvm_report_server report_server;
 
int hit_text_cov=90;
int hit_bin_cov=90;
int hit_mode_cov=90;
`uvm_component_utils_begin(uart_base_test)
`uvm_field_int(matched,UVM_ALL_ON)
86,7 → 91,9
env_configuration();
TE_configuration();
uvm_config_db#(uart_config)::set(this,"*","UART_CONFIGURATION",_config);
uvm_resource_db #(int)::set("coverage_cloud","text_coverage",0,null);
uvm_resource_db #(int)::set("coverage_cloud","text_coverage",0,null);
uvm_resource_db #(int)::set("coverage_cloud","binary_coverage",0,null);
uvm_resource_db #(int)::set("coverage_cloud","general_coverage",0,null);
endfunction:build_phase
 
function void connect_phase (uvm_phase phase);
635,7 → 642,7
//
//-------------------------------------------------------------------------------------------------
 
class all_tests extends uart_base_test;
class cover_driven_test extends uart_base_test;
 
rand int unsigned testnumber;
643,7 → 650,7
 
int iteration=0;
parameter MAX_ITER=10000;
parameter MAX_ITER=500;
// Text write tests
seq_1p1 seq1;
704,10 → 711,14
seq_7p2 seq45;
 
`uvm_component_utils(all_tests)
`uvm_component_utils(cover_driven_test)
 
constraint validtest{testnumber inside{[0:45]};
testnumber != 13;}
testnumber != 13;
testnumber != 9;
testnumber != 19;
testnumber != 21;
testnumber != 24;}
function new (string name,uvm_component parent);
super.new(name,parent);
766,7 → 777,8
task run_phase (uvm_phase phase);
super.run_phase(phase);
phase.raise_objection(this);
while(coverage_hit==1'b0 && (iteration < MAX_ITER) ) begin
while(coverage_hit==1'b0 && (iteration < MAX_ITER)) begin
// while(iteration < 1000) begin
iteration++;
randomize();
case(testnumber)
965,19 → 977,32
endtask // run_phase
function void evaluate_coverage();
int text_coverage;
uvm_resource_db#(int)::read_by_name("coverage_cloud","text_coverage",text_coverage);
if(text_coverage >= 80) coverage_hit=1'b1;
int text_cov;
int bin_cov;
int mode_cov;
uvm_resource_db#(int)::read_by_name("coverage_cloud","text_coverage",text_cov);
uvm_resource_db#(int)::read_by_name("coverage_cloud","general_coverage",mode_cov);
uvm_resource_db#(int)::read_by_name("coverage_cloud","binary_coverage",bin_cov);
if((text_cov >= hit_text_cov) &&
(bin_cov >= hit_bin_cov) &&
(mode_cov >= hit_mode_cov)) coverage_hit=1'b1;
endfunction // evaluate_coverage
 
function void report_phase(uvm_phase phase);
int coverage;
int text_cov;
int mode_cov;
int bin_cov;
super.report_phase(phase);
if(!(iteration<MAX_ITER))
begin
uvm_resource_db#(int)::read_by_name("coverage_cloud","text_coverage",coverage);
`uvm_warning("SIM",$sformatf("coverage not hit and reached %0d",coverage));
uvm_resource_db#(int)::read_by_name("coverage_cloud","text_coverage",text_cov);
uvm_resource_db#(int)::read_by_name("coverage_cloud","binary_coverage",bin_cov);
uvm_resource_db#(int)::read_by_name("coverage_cloud","general_coverage",mode_cov);
`uvm_warning("SIM",$sformatf("coverage not hit and reached \n textcov:%0d\nmodecov:%0d\nbincov:%0d",text_cov,mode_cov,bin_cov));
end
else begin
`uvm_info("SIM",$sformatf("Simulation hit the coverage successfully by %0d transactions",iteration),UVM_NONE);
end
endfunction // report_phase
endclass // all_tests
endclass // cover_driven_test
/trunk/tb/uart_top.sv
104,9 → 104,8
uvm_config_db#(virtual rf_interface)::set(uvm_root::get(), "*", "rf_inf",rf_inf);
 
uvm_config_db#(virtual uart_arbiter)::set(uvm_root::get(),"*","arb_inf",arb_inf);
run_test("all_tests");
run_test("cover_driven_test");
end
endmodule:uart_top_tb

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