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URL https://opencores.org/ocsvn/uart2bus_testbench/uart2bus_testbench/trunk

Subversion Repositories uart2bus_testbench

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  • This comparison shows the changes necessary to convert path 
    /uart2bus_testbench
    from Rev 17 to Rev 18
    ↔ Reverse comparison
  •

Rev 17 → Rev 18

/trunk/doc/uart2bus_verification_plan.odt Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/tb/agent/agent_pkg.sv
29,6 → 29,7
`include "uvm_macros.svh"
 
`include "uart_transaction.svh"
`include "uart_dashboard.svh"
`include "uart_sequence.svh"
`include "uart_config.svh"
`include "uart_driver.svh"
37,4 → 38,4
 
`include "uart_agent.svh"
 
endpackage:agent_pkg
endpackage:agent_pkg
/trunk/tb/agent/coverage/uart_coverage.svh
20,6 → 20,7
// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION
//-------------------------------------------------------------------------------------------------
 
struct {command cmd1; command cmd2;} twoburstscmd;
 
class uart_coverage extends uvm_subscriber#(uart_transaction);
26,12 → 27,16
`uvm_component_utils(uart_coverage)
 
uart_transaction trans,_trans;
uart_transaction trans_o1,trans_o2,trans_o3;
 
uart_dashboard dashboard;
covergroup trans_attrib;
communication_mode:
coverpoint trans._mode{
bins valid_mode = {text,binary};
illegal_bins invalid_mode = {wrong_mode_text,wrong_mode_bin};
ignore_bins invalid_mode = {wrong_mode_text,wrong_mode_bin};
}
address:
coverpoint trans.address;
42,20 → 47,26
command:
coverpoint trans._command{
bins valid_command ={read,2};
illegal_bins invalid_command={nop,invalid_read,invalid_write};
ignore_bins invalid_command={nop,invalid_read,invalid_write};
}
first_white_space_field:
coverpoint trans._spacetype1{bins validspace ={single,tab};
illegal_bins invalidspace ={wrong_space};}
ignore_bins invalidspace ={wrong_space};}
second_white_space_field:
coverpoint trans._spacetype2{bins validspace ={single,tab};
illegal_bins invalidspace ={wrong_space};}
ignore_bins invalidspace ={wrong_space};}
end_of_line_field:
coverpoint trans._eoltype{bins valideol={cr,lf};
illegal_bins eol ={wrong_eol};}
ignore_bins eol ={wrong_eol};}
prefix_character_type:
coverpoint trans._chartype;
 
white_spaces_x:
cross first_white_space_field,second_white_space_field,end_of_line_field;
 
pref_x_command:
cross command,prefix_character_type;
endgroup:text_mode_cov
 
covergroup binary_mode_cov;
62,7 → 73,7
command:
coverpoint trans._command{
bins normal_command={read,2,nop};
illegal_bins wrong_command ={invalid_read,invalid_write};
ignore_bins wrong_command ={invalid_read,invalid_write};
}
acknowledge_requirement:
coverpoint trans._reqack;
75,7 → 86,53
illegal_bins invalid= {[257:$]};
}
endgroup:binary_mode_cov
covergroup two_bursts ;
command: coverpoint trans._command{
bins nop_write = (nop=>2);
bins nop_read = (nop=>read);
bins nop_nop = (nop=>nop);
bins write_write = (2=>2);
bins write_read = (2=>read);
bins write_nop = (2=>nop);
bins read_write = (read=>2);
bins read_read = (read=>read);
bins read_nop = (read=>nop);
}
mode_trans: coverpoint trans._mode
{
bins text_bin = (text=>binary);
bins bin_text = (binary=>text);
bins bin_bin = (binary=>binary);
bins text_text = (text=>text);
}
mode_x_cmd: cross command,mode_trans
{
illegal_bins text_nop1 = binsof(command.nop_write) && (binsof(mode_trans.text_bin) || binsof(mode_trans.text_text) );
illegal_bins text_nop2 = binsof(command.nop_read) && (binsof(mode_trans.text_bin) || binsof(mode_trans.text_text) );
illegal_bins text_nop3 = binsof(command.nop_nop) && (binsof(mode_trans.text_bin) || binsof(mode_trans.text_text) ||
binsof(mode_trans.bin_text));
illegal_bins text_nop4 = binsof(command.write_nop) && (binsof(mode_trans.bin_text) || binsof(mode_trans.text_text) );
illegal_bins text_nop5 = binsof(command.read_nop) && (binsof(mode_trans.bin_text) || binsof(mode_trans.text_text) );
}
endgroup // two_bursts
 
covergroup four_bursts ;
command: coverpoint trans._command
{
bins nop_read_write_nop = (nop=>read=>2=>nop);
bins read_write_read_write = (read=>2=>read=>2);
bins read_read_write_read = (read=>read=>2=>read);
bins write_read_read_write = (2=>read=>read=>2);
bins write_write_read_write= (2=>2=>read=>2);
bins write_write_write_write=(2=>2=>2=>2);
bins read_read_read_read = (read=>read=>read=>read);
bins nop_nop_nop_nop = (nop=>nop=>nop=>nop);
}
endgroup
function new (string name, uvm_component parent);
super.new(name,parent);
82,6 → 139,8
trans_attrib = new();
text_mode_cov = new();
binary_mode_cov = new();
two_bursts = new();
four_bursts = new();
endfunction:new
 
extern function void build_phase(uvm_phase phase);
91,18 → 150,16
extern task run_phase (uvm_phase);
 
extern function void write (uart_transaction t);
 
extern function void update_cov ();
endclass:uart_coverage
 
 
function void uart_coverage::build_phase (uvm_phase phase);
super.build_phase(phase);
 
 
trans = uart_transaction::type_id::create("trans");
_trans = uart_transaction::type_id::create("_trans");
 
super.build_phase(phase);
trans = uart_transaction::type_id::create("trans");
dashboard = uvm_resource_db#(uart_dashboard)::get_by_name("shared_cloud","dashboard").read();
endfunction:build_phase
 
function void uart_coverage::connect_phase(uvm_phase phase);
115,15 → 172,24
function void uart_coverage::write(uart_transaction t);
$cast(trans,t.clone());
trans_attrib.sample();
uvm_resource_db#(int)::write_by_name("coverage_cloud","general_coverage",trans_attrib.get_coverage());
if(trans._mode == text)
begin
text_mode_cov.sample();
uvm_resource_db#(int)::write_by_name("coverage_cloud","text_coverage",text_mode_cov.get_coverage());
end
else if (trans._mode == binary)
begin
binary_mode_cov.sample();
uvm_resource_db#(int)::write_by_name("coverage_cloud","binary_coverage",binary_mode_cov.get_coverage());
end
four_bursts.sample();
two_bursts.sample();
update_cov();
endfunction // write
 
function void uart_coverage::update_cov();
dashboard.trans_attribute_cov=trans_attrib.get_coverage();
dashboard.text_mode_cov = text_mode_cov.get_coverage();
dashboard.binary_mode_cov = binary_mode_cov.get_coverage();
dashboard.two_binary_bursts_cov=two_bursts.get_coverage();
dashboard.four_bursts_cov=four_bursts.get_coverage();
dashboard.evaluate_coverage();
endfunction // update_cov
/trunk/tb/agent/transaction/uart_dashboard.svh
0,0 → 1,84
//-------------------------------------------------------------------------------------------------
//
// UART2BUS VERIFICATION
//
//-------------------------------------------------------------------------------------------------
// CREATOR : HANY SALAH
// PROJECT : UART2BUS UVM TEST BENCH
// UNIT : DASHBOARD
//-------------------------------------------------------------------------------------------------
// TITLE : UART DASHBOARD
// DESCRIPTION: THIS OBJECTS HOLD THE SHARED ATTRIBUTES AMONG ALL COMPONENTS AND THE UPDATED RESULTS
//-------------------------------------------------------------------------------------------------
// LOG DETAILS
//-------------
// VERSION NAME DATE DESCRIPTION
// 1 HANY SALAH 14072017 FILE CREATION
//-------------------------------------------------------------------------------------------------
// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR OPENCORES MEMBERS
// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION
//-------------------------------------------------------------------------------------------------
class uart_dashboard extends uvm_object;
 
// Coverage Fields
// Thresholds
protected int hit_text_cov=90;
protected int hit_bin_cov=90;
protected int hit_mode_cov=90;
protected int hit_two_bursts_cov=90;
protected int hit_four_bursts_cov=90;
// Ratios
int unsigned trans_attribute_cov;
int unsigned text_mode_cov;
int unsigned binary_mode_cov;
int unsigned two_binary_bursts_cov;
int unsigned four_bursts_cov;
bit hit_coverage=1'b0;
 
uvm_table_printer pr;
`uvm_object_utils_begin(uart_dashboard);
`uvm_field_int(trans_attribute_cov,UVM_ALL_ON)
`uvm_field_int(text_mode_cov,UVM_ALL_ON)
`uvm_field_int(binary_mode_cov,UVM_ALL_ON)
`uvm_field_int(two_binary_bursts_cov,UVM_ALL_ON)
`uvm_field_int(four_bursts_cov,UVM_ALL_ON)
 
`uvm_field_int(hit_text_cov,UVM_ALL_ON|UVM_NOPRINT|UVM_DEC)
`uvm_field_int(hit_bin_cov,UVM_ALL_ON|UVM_NOPRINT)
`uvm_field_int(hit_mode_cov,UVM_ALL_ON|UVM_NOPRINT)
`uvm_field_int(hit_two_bursts_cov,UVM_ALL_ON|UVM_NOPRINT)
`uvm_field_int(hit_four_bursts_cov,UVM_ALL_ON|UVM_NOPRINT)
`uvm_object_utils_end
 
function new (string name="uart_dashboard");
super.new(name);
pr = new ();
pr.knobs.default_radix=UVM_DEC;
endfunction // new
 
function void set_cov_threshold(hit_text_cov,
hit_bin_cov,
hit_mode_cov,
hit_two_bursts_cov,
hit_four_bursts_cov);
this.hit_text_cov = hit_text_cov;
this.hit_bin_cov = hit_bin_cov;
this.hit_mode_cov = hit_mode_cov;
this.hit_two_bursts_cov = hit_two_bursts_cov;
this.hit_four_bursts_cov = hit_four_bursts_cov;
endfunction // set_cov_threshold
 
function void evaluate_coverage();
if((text_mode_cov >= hit_text_cov) &&
(binary_mode_cov >= hit_bin_cov) &&
(trans_attribute_cov >= hit_mode_cov) &&
(two_binary_bursts_cov >= hit_two_bursts_cov)&&
(four_bursts_cov >= hit_four_bursts_cov))
hit_coverage = 1'b1;
endfunction // evaluate_coverage
 
endclass
/trunk/tb/run.do
1,7 → 1,17
rm -rf work
rm -rf *.log
rm -rf transcript
rm -rf vsim.wlf
rm -rf vsim_stacktrace.vstf
vlib work
#setenv UVM_HOME '/home/hanysalah/Desktop/training/uvm-1.2'
#------------------------------
# BFMs Compiling
#------------------------------
vlog uvm-1.2/src/uvm.sv +incdir+uvm_src/
#------------------------------
# BFMs Compiling
#------------------------------
vlog -novopt interfaces/uart_interface.sv +incdir+../
vlog -novopt interfaces/rf_interface.sv +incdir+../
vlog -novopt interfaces/uart_arbiter.sv +incdir+../
8,15 → 18,15
#-----------------------------
# Agent Compiling
#------------------------------
vlog -novopt agent/agent_pkg.sv +incdir+agent +incdir+agent/driver +incdir+./ +incdir+agent/configuration +incdir+agent/sequence +incdir+agent/transaction +incdir+agent/monitor +incdir+agent/coverage
vlog -novopt agent/agent_pkg.sv +incdir+agent +incdir+agent/driver +incdir+./ +incdir+agent/configuration +incdir+agent/sequence +incdir+agent/transaction +incdir+agent/monitor +incdir+agent/coverage +incdir+uvm_src/ +define+UVM_1p2
#-----------------------------
# Environment & Scoreboard Compiling
#------------------------------
vlog -novopt env/env_pkg.sv +incdir+env +incdir+analysis
vlog -novopt env/env_pkg.sv +incdir+env +incdir+analysis +incdir+uvm_src/ +define+UVM_1p2
#-----------------------------
# UART TEST Compiling
#------------------------------
vlog -novopt uart_pkg.sv +incdir+test/ +incdir+agent/ +incdir+env/ +incdir+./ +incdir+../
vlog -novopt uart_pkg.sv +incdir+test/ +incdir+agent/ +incdir+env/ +incdir+./ +incdir+../ +incdir+uvm_src/ +define+UVM_1p2
#-----------------------------
# UART DUT Compiling
#------------------------------
29,9 → 39,9
#-----------------------------
# UART Top Testbench Compiling
#------------------------------
vlog -novopt uart_top.sv +incdir+../../rtl/i2c/ +incdir+./ +incdir+../rtl
vlog -novopt uart_top.sv +incdir+../../rtl/i2c/ +incdir+./ +incdir+../rtl +incdir+uvm_src/ +define+UVM_1p2
#-----------------------------
# UART Top Testbench Simulation
#------------------------------
vsim -novopt +coverage uart_top_tb
vsim -novopt +coverage uart_top_tb -sv_lib /home/hanysalah/Desktop/training/uvm-1.2/lib/uvm_dpi64 +UVM_NO_RELNOTES
run -all
/trunk/tb/run_script_packeduvm.sh
42,5 → 42,6
#-----------------------------
# UART Top Testbench Simulation
#------------------------------
vsim -novopt +coverage -c uart_top_tb -sv_lib $UVM_HOME/lib/uvm_dpi64
#vsim -novopt +coverage -c uart_top_tb -sv_lib $UVM_HOME/lib/uvm_dpi64
vsim -novopt +coverage -c uart_top_tb -sv_lib $UVM_HOME/lib/uvm_dpi64 -do "run -a;"
#run -all
/trunk/tb/test/uart_test.svh
21,6 → 21,7
// 2 HANY SALAH 20012016 ADD BINARY MODE TESTS AND INVALID TESTS
// 3 HANY SALAH 12022016 IMPROVE BLOCK DESCRIPTION & ADD COMMENTS
// 4 HANY SALAH 26062017 ADD COVERAGE DRIVEN TEST
// 5 HANY SALAH 22072017 ADD THE DASHBOARD SETTINGS
//-------------------------------------------------------------------------------------------------
// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR OPENCORES MEMBERS
// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION
72,8 → 73,11
`endif
int hit_text_cov=90;
int hit_bin_cov=90;
int hit_mode_cov=90;
int hit_mode_cov=90;
 
uart_dashboard dashboard;
`uvm_component_utils_begin(uart_base_test)
`uvm_field_int(matched,UVM_ALL_ON)
`uvm_component_utils_end
97,10 → 101,9
`endif
env_configuration();
TE_configuration();
dashboard = uart_dashboard::type_id::create("uart_dashboard");
uvm_resource_db#(uart_dashboard)::set("shared_cloud","dashboard",dashboard,null);
uvm_config_db#(uart_config)::set(this,"*","UART_CONFIGURATION",_config);
uvm_resource_db #(int)::set("coverage_cloud","text_coverage",0,null);
uvm_resource_db #(int)::set("coverage_cloud","binary_coverage",0,null);
uvm_resource_db #(int)::set("coverage_cloud","general_coverage",0,null);
endfunction:build_phase
 
function void connect_phase (uvm_phase phase);
125,6 → 128,11
uvm_root::get().set_timeout(10s);
//uvm_root::get().finish_on_completion=1'b0;
endfunction // TE_configuration
 
function void end_of_elaboration_phase (uvm_phase phase);
super.end_of_elaboration_phase(phase);
//dashboard.set_cov_threshold(80,80,80,80,80);
endfunction // end_of_elaboration_phase
task run_phase (uvm_phase phase);
phase.phase_done.set_drain_time(this,5000);
511,8 → 519,7
seq24 = seq_2p11::type_id::create("seq24");
seq25 = seq_2p12::type_id::create("seq25");
seq26 = seq_2p13::type_id::create("seq26");
uvm_resource_db #(int)::set("coverage_cloud","text_coverage",0,null);
//uvm_resource_db #(int)::set("coverage_cloud","text_coverage",0,null);
uvm_resource_db #(int)::set("coverage_cloud","text_coverage",0,null);
endfunction:build_phase
 
task run_phase (uvm_phase phase);
650,7 → 657,7
//
//-------------------------------------------------------------------------------------------------
 
class cover_driven_test extends uart_base_test;
class coverage_base_test extends uart_base_test;
 
rand int unsigned testnumber;
658,7 → 665,9
 
int iteration=0;
parameter MAX_ITER=500;
parameter MAX_ITER=10000;
 
uvm_table_printer cov_pr;
// Text write tests
seq_1p1 seq1;
719,7 → 728,7
seq_7p2 seq45;
 
`uvm_component_utils(cover_driven_test)
`uvm_component_utils(coverage_base_test)
 
constraint validtest{testnumber inside{[0:45]};
testnumber != 13;
780,12 → 789,18
seq43 = seq_6p10::type_id::create("seq43");
seq44 = seq_7p1::type_id::create("seq44");
seq45 = seq_7p2::type_id::create("seq45");
cov_pr = new();
endfunction // build_phase
 
function void end_of_elaboration_phase (uvm_phase phase);
super.end_of_elaboration_phase(phase);
cov_pr.knobs.default_radix=UVM_DEC;
endfunction // end_of_elaboration_phase
task run_phase (uvm_phase phase);
super.run_phase(phase);
phase.raise_objection(this);
while(coverage_hit==1'b0 && (iteration < MAX_ITER)) begin
while(!dashboard.hit_coverage && (iteration < MAX_ITER)) begin
// while(iteration < 1000) begin
iteration++;
randomize();
979,38 → 994,24
`uvm_error("TE","Invalid_test")
end
endcase // case (testnumber)
evaluate_coverage();
end // while (coverage_hit==1'b0)
end // while (!dashboard.hit_coverage && (iteration < MAX_ITER))
phase.drop_objection(this);
endtask // run_phase
function void evaluate_coverage();
int text_cov;
int bin_cov;
int mode_cov;
uvm_resource_db#(int)::read_by_name("coverage_cloud","text_coverage",text_cov);
uvm_resource_db#(int)::read_by_name("coverage_cloud","general_coverage",mode_cov);
uvm_resource_db#(int)::read_by_name("coverage_cloud","binary_coverage",bin_cov);
if((text_cov >= hit_text_cov) &&
(bin_cov >= hit_bin_cov) &&
(mode_cov >= hit_mode_cov)) coverage_hit=1'b1;
endfunction // evaluate_coverage
 
function void report_phase(uvm_phase phase);
int text_cov;
int mode_cov;
int bin_cov;
super.report_phase(phase);
if(!(iteration<MAX_ITER))
if(!dashboard.hit_coverage)
begin
uvm_resource_db#(int)::read_by_name("coverage_cloud","text_coverage",text_cov);
uvm_resource_db#(int)::read_by_name("coverage_cloud","binary_coverage",bin_cov);
uvm_resource_db#(int)::read_by_name("coverage_cloud","general_coverage",mode_cov);
`uvm_warning("SIM",$sformatf("coverage not hit and reached \n textcov:%0d\nmodecov:%0d\nbincov:%0d",text_cov,mode_cov,bin_cov));
`uvm_warning("SIM","Coverage not hit");
dashboard.print(cov_pr);
end
else begin
`uvm_info("SIM",$sformatf("Simulation hit the coverage successfully by %0d transactions",iteration),UVM_NONE);
dashboard.print(cov_pr);
end
endfunction // report_phase
endclass // cover_driven_test
endclass // coverage_base_test
/trunk/tb/uart_top.sv
104,7 → 104,7
uvm_config_db#(virtual rf_interface)::set(uvm_root::get(), "*", "rf_inf",rf_inf);
 
uvm_config_db#(virtual uart_arbiter)::set(uvm_root::get(),"*","arb_inf",arb_inf);
run_test("cover_driven_test");
run_test("coverage_base_test");
end

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