URL
https://opencores.org/ocsvn/uart6551/uart6551/trunk
Subversion Repositories uart6551
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- This comparison shows the changes necessary to convert path
/uart6551/trunk/trunk/rtl
- from Rev 2 to Rev 3
- ↔ Reverse comparison
Rev 2 → Rev 3
/uart6551.sv
110,7 → 110,7
reg [3:0] rxThres; // receiver threshold for interrupt |
reg [3:0] txThres; // transmitter threshold for interrupt |
reg rxTout; // receiver timeout |
wire [11:0] rxCnt; // reciever counter value |
wire [9:0] rxCnt; // reciever counter value |
reg [7:0] rxToutMax; |
reg [2:0] irqenc; // encoded irq cause |
wire rxITrig; // receiver interrupt trigger level |
147,8 → 147,8
assign txITrig = txQued <= txThres; |
wire rxDRQ1 = (fifoEnable ? rxITrig : ~rxEmpty); |
wire txDRQ1 = (fifoEnable ? txITrig : txEmpty); |
assign rxDRQ = dmaEnable & rxDRQ1; |
assign txDRQ = dmaEnable & txDRQ1; |
assign rxDRQ_o = dmaEnable & rxDRQ1; |
assign txDRQ_o = dmaEnable & txDRQ1; |
wire rxIRQ = rxIe & rxDRQ1; |
wire txIRQ = txIe & txDRQ1; |
|
583,12 → 583,12
|
//----------------------------------------------------- |
// encode IRQ mailbox |
always @(rxDRQ or rxTout or txDRQ or lineStatusChange or modemStatusChange) |
always @(rxDRQ_o or rxTout or txDRQ_o or lineStatusChange or modemStatusChange) |
irqenc <= |
lineStatusChange ? 3'd0 : |
~rxDRQ ? 3'd1 : |
~rxDRQ_o ? 3'd1 : |
rxTout ? 3'd2 : |
~txDRQ ? 3'd3 : |
~txDRQ_o ? 3'd3 : |
modemStatusChange ? 3'd4 : |
3'd0; |
|
/uart6551Rx.sv
67,6 → 67,7
reg [10:0] rx_data; // working receive data register |
reg [9:0] t2; // data minus stop bit(s) |
reg [7:0] t3,t4; // data minus parity bit and start bit |
reg [7:0] t5; |
reg p1; |
reg gerr; // global error status |
reg perr; // parity error |
76,6 → 77,9
reg wf; // fifo write |
wire empty; |
reg didRd; |
wire [7:0] dout1; |
reg full1; |
wire fifoFull, fifoEmpty; |
|
assign ack = cyc & cs; |
wire pe_rd; |
92,12 → 96,16
.wr(wf), |
.rd(rdf), |
.din({bz,perr,ferr,t4}), |
.dout({break_o,parityErr,frameErr,dout}), |
.dout({break_o,parityErr,frameErr,dout1}), |
.ctr(qcnt), |
.full(full), |
.empty(empty) |
.full(fifoFull), |
.empty(fifoEmpty) |
); |
|
assign dout = fifoEnable ? dout1 : t5; |
assign empty = fifoEnable ? fifoEmpty : ~full1; |
assign full = fifoEnable ? fifoFull : full1; |
|
// compute 1/2 the length of the last bit |
// needed for framing error detection |
reg [7:0] halfLastBit; |
128,7 → 136,7
|
// grab the parity bit |
always @(t2) |
p1 <= t2[33]; |
p1 <= t2[9]; |
|
// strip off parity and start bit |
always @(parityCtrl or t2) |
257,6 → 265,24
|
always @(posedge clk) |
if (rst) |
t5 <= 1'b0; |
else begin |
if (wf) |
t5 <= t4; |
end |
|
always @(posedge clk) |
if (rst) |
full1 <= 1'b0; |
else begin |
if (wf) |
full1 <= 1'b1; |
else if (pe_rd) |
full1 <= 1'b0; |
end |
|
always @(posedge clk) |
if (rst) |
didRd <= 1'b0; |
else begin |
// set a read flag for later reference |
/uart6551Tx.sv
24,6 → 24,8
`define IDLE 0 |
`define CNT 1 |
|
//`define UART_NO_TX_FIFO 1'b1 |
|
module uart6551Tx(rst, clk, cyc, cs, wr, din, ack, |
fifoEnable, fifoClear, txBreak, |
frameSize, wordLength, parityCtrl, baud16x_ce, |
63,11 → 65,11
edge_det ued1 (.rst(rst), .clk(clk), .ce(1'b1), .i(ack & wr), .pe(awr), .ne(), .ee()); |
|
`ifdef UART_NO_TX_FIFO |
reg [7:0] fdo; |
reg [7:0] fdo2; |
reg empty; |
|
always @(posedge clk) |
if (awr) fdo <= {3'd0,din}; |
if (awr) fdo2 <= {3'd0,din}; |
|
always @(posedge clk) |
begin |
76,7 → 78,11
end |
|
assign full = ~empty; |
wire [7:0] fdo = fdo2; |
`else |
reg [7:0] fdo2; |
always @(posedge clk) |
if (awr) fdo2 <= {3'd0,din}; |
// generate an empty signal for when the fifo is disabled |
reg fempty2; |
always @(posedge clk) |
88,7 → 94,7
end |
|
|
wire [7:0] fdo; // fifo data output |
wire [7:0] fdo1; // fifo data output |
wire rdf = fifoEnable ? rd : awr; |
wire fempty; |
wire ffull; |
99,7 → 105,7
.din(din), |
.wr(awr), |
.rd(rdf), |
.dout(fdo), |
.dout(fdo1), |
.full(ffull), |
.empty(fempty), |
.ctr(qcnt) |
106,9 → 112,9
); |
assign empty = fifoEnable ? fempty : fempty2; |
assign full = fifoEnable ? ffull : ~fempty2; |
wire [7:0] fdo = fifoEnable ? fdo1 : fdo2; |
`endif |
|
|
// mask transmit data for word length |
// this mask is needed for proper parity generation |
integer n; |