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Rev 5 → Rev 6

/uart6551BaudLUT.sv
1,34 → 1,49
// ============================================================================
// __
// \\__/ o\ (C) 2005-2019 Robert Finch, Waterloo
// \\__/ o\ (C) 2005-2022 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// ============================================================================
//
module uart6551BaudLUT(a, o);
parameter CLK_FREQ = 100;
parameter pCounterBits = 24;
input [4:0] a;
output reg [pCounterBits-1:0] o;
 
/*
// table for a 50.000MHz reference clock
// value = 50,000,000 / (baud * 16)
always @(a)
always_comb
case (a) // synopsys full_case parallel_case
5'd0: o <= 0;
5'd1: o <= 24'd62500; // 50 baud
55,7 → 70,97
5'd21: o <= 24'd3; // 921600 baud
default: o <= 24'd326; // 9600 baud
endcase
*/
 
// table for a 40.000MHz reference clock
// value = 40,000,000 / (baud * 16)
 
always_comb
if (CLK_FREQ==40)
case (a) // synopsys full_case parallel_case
5'd0: o <= 0;
5'd1: o <= 24'd50000; // 50 baud
5'd2: o <= 24'd33333; // 75 baud
5'd3: o <= 24'd22744; // 109.92 baud
5'd4: o <= 24'd18576; // 134.58 baud
5'd5: o <= 24'd16667; // 150 baud
5'd6: o <= 24'd8333; // 300 baud
5'd7: o <= 24'd4167; // 600 baud
5'd8: o <= 24'd2083; // 1200 baud
5'd9: o <= 24'd1389; // 1800 baud
5'd10: o <= 24'd1042; // 2400 baud
5'd11: o <= 24'd694; // 3600 baud
5'd12: o <= 24'd521; // 4800 baud
5'd13: o <= 24'd347; // 7200 baud
5'd14: o <= 24'd260; // 9600 baud
5'd15: o <= 24'd130; // 19200 baud
 
5'd16: o <= 24'd65; // 38400 baud
5'd17: o <= 24'd43; // 57600 baud
5'd18: o <= 24'd22; // 115200 baud
5'd19: o <= 24'd11; // 230400 baud
5'd20: o <= 24'd5; // 460800 baud
5'd21: o <= 24'd3; // 921600 baud
default: o <= 24'd260; // 9600 baud
endcase
else if (CLK_FREQ==60)
// table for a 60.000MHz reference clock
case (a) // synopsys full_case parallel_case
5'd0: o <= 0;
5'd1: o <= 24'd75000; // 50 baud
5'd2: o <= 24'd50000; // 75 baud
5'd3: o <= 24'd34116; // 109.92 baud
5'd4: o <= 24'd27864; // 134.58 baud
5'd5: o <= 24'd25000; // 150 baud
5'd6: o <= 24'd12500; // 300 baud
5'd7: o <= 24'd6250; // 600 baud
5'd8: o <= 24'd3125; // 1200 baud
5'd9: o <= 24'd2083; // 1800 baud
5'd10: o <= 24'd1563; // 2400 baud
5'd11: o <= 24'd1042; // 3600 baud
5'd12: o <= 24'd781; // 4800 baud
5'd13: o <= 24'd521; // 7200 baud
5'd14: o <= 24'd391; // 9600 baud
5'd15: o <= 24'd195; // 19200 baud
 
5'd16: o <= 24'd98; // 38400 baud
5'd17: o <= 24'd65; // 57600 baud
5'd18: o <= 24'd33; // 115200 baud
5'd19: o <= 24'd16; // 230400 baud
5'd20: o <= 24'd8; // 460800 baud
5'd21: o <= 24'd4; // 921600 baud
default: o <= 24'd391; // 9600 baud
endcase
else if (CLK_FREQ==100)
// 100MHz
case (a) // synopsys full_case parallel_case
5'd0: o <= 0;
5'd1: o <= 24'd125000; // 50 baud
5'd2: o <= 24'd83333; // 75 baud
5'd3: o <= 24'd56860; // 109.92 baud
5'd4: o <= 24'd46441; // 134.58 baud
5'd5: o <= 24'd41667; // 150 baud
5'd6: o <= 24'd20833; // 300 baud
5'd7: o <= 24'd10417; // 600 baud
5'd8: o <= 24'd5208; // 1200 baud
5'd9: o <= 24'd3472; // 1800 baud
5'd10: o <= 24'd2604; // 2400 baud
5'd11: o <= 24'd1736; // 3600 baud
5'd12: o <= 24'd1302; // 4800 baud
5'd13: o <= 24'd868; // 7200 baud
5'd14: o <= 24'd651; // 9600 baud
5'd15: o <= 24'd326; // 19200 baud
 
5'd16: o <= 24'd163; // 38400 baud
5'd17: o <= 24'd109; // 57600 baud
5'd18: o <= 24'd54; // 115200 baud
5'd19: o <= 24'd27; // 230400 baud
5'd20: o <= 24'd14; // 460800 baud
5'd21: o <= 24'd7; // 921600 baud
default: o <= 24'd651; // 9600 baud
endcase
 
 
endmodule
 
 
/uart6551Rx_x12.sv
66,7 → 66,7
output parityErr; // parity error
output break_o; // break detected
output gerr; // global error indicator
output [3:0] qcnt; // count of number of words queued
output [5:0] qcnt; // count of number of words queued
output [10:0] cnt; // receiver counter
output bitStream; // received bit stream
 
95,9 → 95,26
reg full1;
wire fifoFull, fifoEmpty;
 
assign ack = cyc & cs;
ack_gen #(
.READ_STAGES(1),
.WRITE_STAGES(0),
.REGISTER_OUTPUT(1)
) uag1
(
.rst_i(rst),
.clk_i(clk),
.ce_i(1'b1),
.i(cs & cyc & ~wr),
.we_i(cs & cyc & wr),
.o(ack),
.rid_i(0),
.wid_i(0),
.rid_o(),
.wid_o()
);
 
wire pe_rd, pe_wf;
edge_det ued1 (.rst(rst), .clk(clk), .ce(1'b1), .i(ack & ~wr), .pe(pe_rd), .ne(), .ee());
edge_det ued1 (.rst(rst), .clk(clk), .ce(1'b1), .i(cs & cyc & ~wr), .pe(pe_rd), .ne(), .ee());
edge_det ued2 (.rst(rst), .clk(clk), .ce(1'b1), .i(wf), .pe(pe_wf), .ne(), .ee());
 
assign bitStream = rx_data[14];
104,15 → 121,19
assign bz = t3==12'd0;
wire rdf = fifoEnable ? pe_rd : pe_wf;
 
uart6551Fifo #(.WID(15)) uf1
// Distributed RAM fifo (vendor supplied):
// First word fall-through
// 64 entries deep
// 15 bits wide
uart6551RxFifo uf1
(
.clk(clk),
.rst(rst|clear|fifoClear),
.wr(wf),
.rd(rdf),
.srst(rst|clear|fifoClear),
.wr_en(wf),
.rd_en(rdf),
.din({bz,perr,ferr,t3}),
.dout({break_o,parityErr,frameErr,dout1}),
.ctr(qcnt),
.data_count(qcnt),
.full(fifoFull),
.empty(fifoEmpty)
);
/uart6551Tx_x12.sv
35,7 → 35,9
// ============================================================================
//
`define IDLE 0
`define CNT 1
`define READ1 1
`define READ2 2
`define CNT 3
 
//`define UART_NO_TX_FIFO 1'b1
 
64,12 → 66,12
output reg txd; // external serial output
output full; // fifo is full
output empty; // fifo is empty
output [3:0] qcnt; // number of characters queued
output [5:0] qcnt; // number of characters queued
 
reg [11:0] t1;
reg [15:0] t2;
reg [15:0] tx_data; // transmit data working reg (raw)
reg state; // state machine state
reg [1:0] state; // state machine state
reg [8:0] cnt; // baud clock counter
reg rd;
reg p1, p2; // parity bit
95,7 → 97,7
`else
reg [11:0] fdo2;
always_ff @(posedge clk)
if (awr) fdo2 <= {3'd0,din};
if (awr) fdo2 <= din;
// generate an empty signal for when the fifo is disabled
reg fempty2;
always_ff @(posedge clk)
111,17 → 113,20
wire rdf = fifoEnable ? rd : awr;
wire fempty;
wire ffull;
uart6551Fifo #(.WID(12)) fifo0
(
.clk(clk),
.rst(rst|clear|fifoClear),
.din(din),
.wr(awr),
.rd(rdf),
.dout(fdo1),
.full(ffull),
.empty(fempty),
.ctr(qcnt)
// Distributed RAM fifo (vendor supplied):
// Standard fifo
// 64 entries deep
// 12 bits wide
uart6551TxFifo fifo1 (
.clk(clk), // input wire clk
.srst(rst|clear|fifoClear), // input wire srst
.din(din), // input wire [11 : 0] din
.wr_en(awr), // input wire wr_en
.rd_en(rdf), // input wire rd_en
.dout(fdo1), // output wire [11 : 0] dout
.full(ffull), // output wire full
.empty(fempty), // output wire empty
.data_count(qcnt) // output wire [4 : 0] data_count
);
assign empty = fifoEnable ? fempty : fempty2;
assign full = fifoEnable ? ffull : ~fempty2;
188,7 → 193,11
case(state)
`IDLE:
if ((!empty && cts)||txBreak)
state <= `CNT;
state <= `READ1;
`READ1:
state <= `READ2;
`READ2:
state <= `CNT;
`CNT:
if (cnt==frameSize)
state <= `IDLE;
234,9 → 243,8
else begin
if (baud16x_ce) begin
case(state)
`IDLE:
if ((!empty && cts)||txBreak)
tx_data <= t2;
`READ2:
tx_data <= t2;
`CNT:
// Shift the data out. LSB first.
if (cnt[3:0]==4'hF)
/uart6551_x12.sv
57,6 → 57,7
rxDRQ_o, txDRQ_o,
xclk_i, RxC_i
);
parameter CLK_FREQ = 100;
parameter pCounterBits = 24;
parameter pFifoSize = 1024;
parameter pClkDiv = 24'd1302; // 9.6k baud, 200.000MHz clock
157,9 → 158,10
// fifo
reg rxFifoClear;
reg txFifoClear;
reg fifoEnable;
wire [3:0] rxQued;
wire [3:0] txQued;
reg rxFifoEnable;
reg txFifoEnable;
wire [5:0] rxQued;
wire [5:0] txQued;
 
// test
wire txd1;
166,10 → 168,10
 
assign data_present = ~rxEmpty;
 
assign rxITrig = rxQued >= rxThres;
assign txITrig = txQued <= txThres;
wire rxDRQ1 = (fifoEnable ? rxITrig : ~rxEmpty);
wire txDRQ1 = (fifoEnable ? txITrig : txEmpty);
assign rxITrig = rxQued[5:2] >= rxThres;
assign txITrig = txQued[5:2] <= txThres;
wire rxDRQ1 = (rxFifoEnable ? rxITrig : ~rxEmpty);
wire txDRQ1 = (txFifoEnable ? txITrig : txEmpty);
assign rxDRQ_o = dmaEnable & rxDRQ1;
assign txDRQ_o = dmaEnable & txDRQ1;
wire rxIRQ = rxIe & rxDRQ1;
232,7 → 234,7
.wr(we),
.dout(rx_do),
.ack(),
.fifoEnable(fifoEnable),
.fifoEnable(rxFifoEnable),
.fifoClear(rxFifoClear),
.clearGErr(1'b0),
.wordLength(wordLength),
262,7 → 264,7
.wr(we),
.din(dati),
.ack(),
.fifoEnable(fifoEnable),
.fifoEnable(txFifoEnable),
.fifoClear(txFifoClear),
.txBreak(txBreak),
.frameSize(frameSize), // 16 x 10 bits
289,7 → 291,7
if (cs) begin
case(adr_h)
`UART_TRB: dat_o <= {4'h0,rx_do}; // receiver holding register
`UART_STAT: dat_o <= {irq_o,3'h0,irq_o,dsrx[1],dcdx[1],fifoEnable ? ~txFull : txEmpty,~rxEmpty,overrun,frameErr,parityErr};
`UART_STAT: dat_o <= {irq_o,3'h0,irq_o,dsrx[1],dcdx[1],txFifoEnable ? ~txFull : txEmpty,~rxEmpty,overrun,frameErr,parityErr};
`UART_CMD: dat_o <= cmd0;
`UART_CTRL: dat_o <= ctrl0;
`UART_IRQS: dat_o <= irqStatusReg;
337,7 → 339,8
// Fifo control
txFifoClear <= 1'b1;
rxFifoClear <= 1'b1;
fifoEnable <= 1'b1;
rxFifoEnable <= 1'b1;
txFifoEnable <= 1'b1;
// Test
llb <= 1'b0;
selCD <= 1'b0;
418,9 → 421,10
`UART_CTRL2:
begin
ctrl2 <= dati;
fifoEnable <= dati[0];
rxFifoClear <= dati[1];
txFifoClear <= dati[2];
rxFifoEnable <= dati[0];
txFifoEnable <= dati[1];
rxFifoClear <= dati[2];
txFifoClear <= dati[3];
case (dati[5:4])
2'd0: txThres <= 4'd1; // one-byte
2'd1: txThres <= pFifoSize / 4; // one-quarter full
457,7 → 461,10
xClkSrc <= baudRateSel==5'd0;
 
wire [pCounterBits-1:0] bclkdiv;
uart6551BaudLUT #(pCounterBits) ublt1 (.a(baudRateSel), .o(bclkdiv));
uart6551BaudLUT #(
.CLK_FREQ(CLK_FREQ),
.pCounterBits(pCounterBits)
) ublt1 (.a(baudRateSel), .o(bclkdiv));
 
reg [pCounterBits-1:0] clkdiv2;
always_ff @(posedge clk_i)

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