URL
https://opencores.org/ocsvn/uart6551/uart6551/trunk
Subversion Repositories uart6551
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- This comparison shows the changes necessary to convert path
/uart6551/trunk/trunk/rtl
- from Rev 7 to Rev 8
- ↔ Reverse comparison
Rev 7 → Rev 8
/uart6551.sv
1,24 → 1,37
// ============================================================================ |
// __ |
// \\__/ o\ (C) 2005-2019 Robert Finch, Waterloo |
// \\__/ o\ (C) 2005-2022 Robert Finch, Waterloo |
// \ __ / All rights reserved. |
// \/_// robfinch<remove>@finitron.ca |
// || |
// |
// |
// This source file is free software: you can redistribute it and/or modify |
// it under the terms of the GNU Lesser General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or |
// (at your option) any later version. |
// |
// This source file is distributed in the hope that it will be useful, |
// but WITHOUT ANY WARRANTY; without even the implied warranty of |
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
// GNU General Public License for more details. |
// |
// You should have received a copy of the GNU General Public License |
// along with this program. If not, see <http://www.gnu.org/licenses/>. |
// BSD 3-Clause License |
// Redistribution and use in source and binary forms, with or without |
// modification, are permitted provided that the following conditions are met: |
// |
// 1. Redistributions of source code must retain the above copyright notice, this |
// list of conditions and the following disclaimer. |
// |
// 2. Redistributions in binary form must reproduce the above copyright notice, |
// this list of conditions and the following disclaimer in the documentation |
// and/or other materials provided with the distribution. |
// |
// 3. Neither the name of the copyright holder nor the names of its |
// contributors may be used to endorse or promote products derived from |
// this software without specific prior written permission. |
// |
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
// |
// ============================================================================ |
// |
`define UART_TRB 2'd0 // transmit/receive buffer |
33,6 → 46,7
rxDRQ_o, txDRQ_o, |
xclk_i, RxC_i |
); |
parameter pClkFreq = 40; |
parameter pCounterBits = 24; |
parameter pFifoSize = 1024; |
parameter pClkDiv = 24'd1302; // 9.6k baud, 200.000MHz clock |
134,6 → 148,7
// fifo |
reg rxFifoClear; |
reg txFifoClear; |
reg txClear; |
reg fifoEnable; |
wire [3:0] rxQued; |
wire [3:0] txQued; |
193,9 → 208,13
( |
.clk_i(clk_i), |
.ce_i(1'b1), |
.i(cs), |
.rid_i('d0), |
.wid_i('d0), |
.i(cs & ~we_i), |
.we_i(cs & we_i), |
.o(ack_o) |
.o(ack_o), |
.rid_o(), |
.wid_o() |
); |
|
uart6551Rx uart_rx0 |
245,7 → 264,7
.parityCtrl(parityCtrl),// no parity |
.baud16x_ce(baud16), |
.cts(ctsx[1]|~hwfc), |
.clear(clear), |
.clear(txClear), |
.txd(txd1), |
.full(txFull), |
.empty(txEmpty), |
298,6 → 317,7
// Fifo control |
txFifoClear <= 1'b1; |
rxFifoClear <= 1'b1; |
txClear <= 1'b1; |
fifoEnable <= 1'b1; |
// Test |
llb <= 1'b0; |
309,6 → 329,7
//llb <= 1'b1; |
rxFifoClear <= 1'b0; |
txFifoClear <= 1'b0; |
txClear <= 1'b0; |
ctrl2[1] <= 1'b0; |
ctrl2[2] <= 1'b0; |
|
401,6 → 422,7
hwfc <= dati[24]; |
dmaEnable <= dati[26]; |
baudRateSel[4] <= dati[27]; |
txClear <= dati[29]; |
selCD <= dati[30]; |
accessCD <= dati[31]; |
end |
420,7 → 442,7
xClkSrc <= baudRateSel==5'd0; |
|
wire [pCounterBits-1:0] bclkdiv; |
uart6551BaudLUT #(pCounterBits) ublt1 (.a(baudRateSel), .o(bclkdiv)); |
uart6551BaudLUT #(.pClkFreq(pClkFreq), .pCounterBits(pCounterBits)) ublt1 (.a(baudRateSel), .o(bclkdiv)); |
|
reg [pCounterBits-1:0] clkdiv2; |
always @(posedge clk_i) |
/uart6551BaudLUT.sv
1,6 → 1,6
// ============================================================================ |
// __ |
// \\__/ o\ (C) 2005-2022 Robert Finch, Waterloo |
// \\__/ o\ (C) 2005-2022 Robert Finch, Waterloo |
// \ __ / All rights reserved. |
// \/_// robfinch<remove>@finitron.ca |
// || |
35,50 → 35,17
// ============================================================================ |
// |
module uart6551BaudLUT(a, o); |
parameter CLK_FREQ = 100; |
parameter pClkFreq = 40; |
parameter pCounterBits = 24; |
input [4:0] a; |
output reg [pCounterBits-1:0] o; |
|
/* |
// table for a 50.000MHz reference clock |
// value = 50,000,000 / (baud * 16) |
always_comb |
if (pClkFreq==40) |
case (a) // synopsys full_case parallel_case |
5'd0: o <= 0; |
5'd1: o <= 24'd62500; // 50 baud |
5'd2: o <= 24'd41667; // 75 baud |
5'd3: o <= 24'd28617; // 109.92 baud |
5'd4: o <= 24'd23220; // 134.58 baud |
5'd5: o <= 24'd20833; // 150 baud |
5'd6: o <= 24'd10417; // 300 baud |
5'd7: o <= 24'd5208; // 600 baud |
5'd8: o <= 24'd2604; // 1200 baud |
5'd9: o <= 24'd1736; // 1800 baud |
5'd10: o <= 24'd1302; // 2400 baud |
5'd11: o <= 24'd868; // 3600 baud |
5'd12: o <= 24'd651; // 4800 baud |
5'd13: o <= 24'd434; // 7200 baud |
5'd14: o <= 24'd326; // 9600 baud |
5'd15: o <= 24'd163; // 19200 baud |
|
5'd16: o <= 24'd81; // 38400 baud |
5'd17: o <= 24'd54; // 57600 baud |
5'd18: o <= 24'd27; // 115200 baud |
5'd19: o <= 24'd14; // 230400 baud |
5'd20: o <= 24'd7; // 460800 baud |
5'd21: o <= 24'd3; // 921600 baud |
default: o <= 24'd326; // 9600 baud |
endcase |
*/ |
|
// table for a 40.000MHz reference clock |
// value = 40,000,000 / (baud * 16) |
|
always_comb |
if (CLK_FREQ==40) |
case (a) // synopsys full_case parallel_case |
5'd0: o <= 0; |
5'd1: o <= 24'd50000; // 50 baud |
5'd2: o <= 24'd33333; // 75 baud |
5'd3: o <= 24'd22744; // 109.92 baud |
103,64 → 70,61
5'd21: o <= 24'd3; // 921600 baud |
default: o <= 24'd260; // 9600 baud |
endcase |
else if (CLK_FREQ==60) |
// table for a 60.000MHz reference clock |
else if (pClkFreq==50) |
case (a) // synopsys full_case parallel_case |
5'd0: o <= 0; |
5'd1: o <= 24'd75000; // 50 baud |
5'd2: o <= 24'd50000; // 75 baud |
5'd3: o <= 24'd34116; // 109.92 baud |
5'd4: o <= 24'd27864; // 134.58 baud |
5'd5: o <= 24'd25000; // 150 baud |
5'd6: o <= 24'd12500; // 300 baud |
5'd7: o <= 24'd6250; // 600 baud |
5'd8: o <= 24'd3125; // 1200 baud |
5'd9: o <= 24'd2083; // 1800 baud |
5'd10: o <= 24'd1563; // 2400 baud |
5'd11: o <= 24'd1042; // 3600 baud |
5'd12: o <= 24'd781; // 4800 baud |
5'd13: o <= 24'd521; // 7200 baud |
5'd14: o <= 24'd391; // 9600 baud |
5'd15: o <= 24'd195; // 19200 baud |
5'd1: o <= 24'd62500; // 50 baud |
5'd2: o <= 24'd41667; // 75 baud |
5'd3: o <= 24'd28617; // 109.92 baud |
5'd4: o <= 24'd23220; // 134.58 baud |
5'd5: o <= 24'd20833; // 150 baud |
5'd6: o <= 24'd10417; // 300 baud |
5'd7: o <= 24'd5208; // 600 baud |
5'd8: o <= 24'd2604; // 1200 baud |
5'd9: o <= 24'd1736; // 1800 baud |
5'd10: o <= 24'd1302; // 2400 baud |
5'd11: o <= 24'd868; // 3600 baud |
5'd12: o <= 24'd651; // 4800 baud |
5'd13: o <= 24'd434; // 7200 baud |
5'd14: o <= 24'd326; // 9600 baud |
5'd15: o <= 24'd163; // 19200 baud |
|
5'd16: o <= 24'd98; // 38400 baud |
5'd17: o <= 24'd65; // 57600 baud |
5'd18: o <= 24'd33; // 115200 baud |
5'd19: o <= 24'd16; // 230400 baud |
5'd20: o <= 24'd8; // 460800 baud |
5'd21: o <= 24'd4; // 921600 baud |
default: o <= 24'd391; // 9600 baud |
5'd16: o <= 24'd81; // 38400 baud |
5'd17: o <= 24'd54; // 57600 baud |
5'd18: o <= 24'd27; // 115200 baud |
5'd19: o <= 24'd14; // 230400 baud |
5'd20: o <= 24'd7; // 460800 baud |
5'd21: o <= 24'd3; // 921600 baud |
default: o <= 24'd326; // 9600 baud |
endcase |
else if (CLK_FREQ==100) |
// 100MHz |
else if (pClkFreq==80) |
case (a) // synopsys full_case parallel_case |
5'd0: o <= 0; |
5'd1: o <= 24'd125000; // 50 baud |
5'd2: o <= 24'd83333; // 75 baud |
5'd3: o <= 24'd56860; // 109.92 baud |
5'd4: o <= 24'd46441; // 134.58 baud |
5'd5: o <= 24'd41667; // 150 baud |
5'd6: o <= 24'd20833; // 300 baud |
5'd7: o <= 24'd10417; // 600 baud |
5'd8: o <= 24'd5208; // 1200 baud |
5'd9: o <= 24'd3472; // 1800 baud |
5'd10: o <= 24'd2604; // 2400 baud |
5'd11: o <= 24'd1736; // 3600 baud |
5'd12: o <= 24'd1302; // 4800 baud |
5'd13: o <= 24'd868; // 7200 baud |
5'd14: o <= 24'd651; // 9600 baud |
5'd15: o <= 24'd326; // 19200 baud |
5'd1: o <= 24'd100000; // 50 baud |
5'd2: o <= 24'd66667; // 75 baud |
5'd3: o <= 24'd45488; // 109.92 baud |
5'd4: o <= 24'd37153; // 134.58 baud |
5'd5: o <= 24'd33333; // 150 baud |
5'd6: o <= 24'd16667; // 300 baud |
5'd7: o <= 24'd8333; // 600 baud |
5'd8: o <= 24'd4167; // 1200 baud |
5'd9: o <= 24'd2778; // 1800 baud |
5'd10: o <= 24'd2083; // 2400 baud |
5'd11: o <= 24'd1389; // 3600 baud |
5'd12: o <= 24'd1042; // 4800 baud |
5'd13: o <= 24'd694; // 7200 baud |
5'd14: o <= 24'd521; // 9600 baud |
5'd15: o <= 24'd260; // 19200 baud |
|
5'd16: o <= 24'd163; // 38400 baud |
5'd17: o <= 24'd109; // 57600 baud |
5'd18: o <= 24'd54; // 115200 baud |
5'd19: o <= 24'd27; // 230400 baud |
5'd20: o <= 24'd14; // 460800 baud |
5'd21: o <= 24'd7; // 921600 baud |
default: o <= 24'd651; // 9600 baud |
5'd16: o <= 24'd130; // 38400 baud |
5'd17: o <= 24'd87; // 57600 baud |
5'd18: o <= 24'd43; // 115200 baud |
5'd19: o <= 24'd22; // 230400 baud |
5'd20: o <= 24'd11; // 460800 baud |
5'd21: o <= 24'd5; // 921600 baud |
default: o <= 24'd521; // 9600 baud |
endcase |
|
|
endmodule |
|
|
/uart6551Fifo.sv
1,24 → 1,37
// ============================================================================ |
// __ |
// \\__/ o\ (C) 2003-2021 Robert Finch, Waterloo |
// \\__/ o\ (C) 2003-2022 Robert Finch, Waterloo |
// \ __ / All rights reserved. |
// \/_// robfinch<remove>@finitron.ca |
// || |
// |
// |
// This source file is free software: you can redistribute it and/or modify |
// it under the terms of the GNU Lesser General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or |
// (at your option) any later version. |
// |
// This source file is distributed in the hope that it will be useful, |
// but WITHOUT ANY WARRANTY; without even the implied warranty of |
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
// GNU General Public License for more details. |
// |
// You should have received a copy of the GNU General Public License |
// along with this program. If not, see <http://www.gnu.org/licenses/>. |
// BSD 3-Clause License |
// Redistribution and use in source and binary forms, with or without |
// modification, are permitted provided that the following conditions are met: |
// |
// 1. Redistributions of source code must retain the above copyright notice, this |
// list of conditions and the following disclaimer. |
// |
// 2. Redistributions in binary form must reproduce the above copyright notice, |
// this list of conditions and the following disclaimer in the documentation |
// and/or other materials provided with the distribution. |
// |
// 3. Neither the name of the copyright holder nor the names of its |
// contributors may be used to endorse or promote products derived from |
// this software without specific prior written permission. |
// |
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
// |
// ============================================================================ |
// |
module uart6551Fifo(clk, rst, wr, rd, din, dout, ctr, full, empty); |
/uart6551Rx.sv
1,24 → 1,37
// ============================================================================ |
// __ |
// \\__/ o\ (C) 2005-2019 Robert Finch, Waterloo |
// \\__/ o\ (C) 2005-2022 Robert Finch, Waterloo |
// \ __ / All rights reserved. |
// \/_// robfinch<remove>@finitron.ca |
// || |
// |
// |
// This source file is free software: you can redistribute it and/or modify |
// it under the terms of the GNU Lesser General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or |
// (at your option) any later version. |
// |
// This source file is distributed in the hope that it will be useful, |
// but WITHOUT ANY WARRANTY; without even the implied warranty of |
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
// GNU General Public License for more details. |
// |
// You should have received a copy of the GNU General Public License |
// along with this program. If not, see <http://www.gnu.org/licenses/>. |
// BSD 3-Clause License |
// Redistribution and use in source and binary forms, with or without |
// modification, are permitted provided that the following conditions are met: |
// |
// 1. Redistributions of source code must retain the above copyright notice, this |
// list of conditions and the following disclaimer. |
// |
// 2. Redistributions in binary form must reproduce the above copyright notice, |
// this list of conditions and the following disclaimer in the documentation |
// and/or other materials provided with the distribution. |
// |
// 3. Neither the name of the copyright holder nor the names of its |
// contributors may be used to endorse or promote products derived from |
// this software without specific prior written permission. |
// |
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
// |
// ============================================================================ |
// |
`define IDLE 0 |
/uart6551Tx.sv
1,24 → 1,37
// ============================================================================ |
// __ |
// \\__/ o\ (C) 2004-2019 Robert Finch, Waterloo |
// \\__/ o\ (C) 2004-2022 Robert Finch, Waterloo |
// \ __ / All rights reserved. |
// \/_// robfinch<remove>@finitron.ca |
// || |
// |
// |
// This source file is free software: you can redistribute it and/or modify |
// it under the terms of the GNU Lesser General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or |
// (at your option) any later version. |
// |
// This source file is distributed in the hope that it will be useful, |
// but WITHOUT ANY WARRANTY; without even the implied warranty of |
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
// GNU General Public License for more details. |
// |
// You should have received a copy of the GNU General Public License |
// along with this program. If not, see <http://www.gnu.org/licenses/>. |
// BSD 3-Clause License |
// Redistribution and use in source and binary forms, with or without |
// modification, are permitted provided that the following conditions are met: |
// |
// 1. Redistributions of source code must retain the above copyright notice, this |
// list of conditions and the following disclaimer. |
// |
// 2. Redistributions in binary form must reproduce the above copyright notice, |
// this list of conditions and the following disclaimer in the documentation |
// and/or other materials provided with the distribution. |
// |
// 3. Neither the name of the copyright holder nor the names of its |
// contributors may be used to endorse or promote products derived from |
// this software without specific prior written permission. |
// |
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
// |
// ============================================================================ |
// |
`define IDLE 0 |