OpenCores
URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /uart_block
    from Rev 29 to Rev 30
    ↔ Reverse comparison
  •

Rev 29 → Rev 30

/trunk/hdl/iseProject/iseProject.gise
314,7 → 314,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1336089729" xil_pn:in_ck="4673194791943474574" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-8986552465892320357" xil_pn:start_ts="1336089718">
<transform xil_pn:end_ts="1336091583" xil_pn:in_ck="4673194791943474574" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-8986552465892320357" xil_pn:start_ts="1336091572">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
343,7 → 343,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1336089834" xil_pn:in_ck="4758608941402184672" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7171404100274592149" xil_pn:start_ts="1336089729">
<transform xil_pn:end_ts="1336092309" xil_pn:in_ck="4758608941402184672" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7171404100274592149" xil_pn:start_ts="1336092204">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
355,7 → 355,7
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1336089837" xil_pn:in_ck="7070038919220904605" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1336089834">
<transform xil_pn:end_ts="1336092312" xil_pn:in_ck="7070038919220904605" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1336092309">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
371,7 → 371,7
<outfile xil_pn:name="INTERCON_P2P_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1336089848" xil_pn:in_ck="5901297062896623158" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1336089837">
<transform xil_pn:end_ts="1336092323" xil_pn:in_ck="5901297062896623158" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1336092312">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
386,7 → 386,7
<outfile xil_pn:name="INTERCON_P2P_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1336089858" xil_pn:in_ck="-1437695683665201866" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="-7817169320884990698" xil_pn:start_ts="1336089848">
<transform xil_pn:end_ts="1336092334" xil_pn:in_ck="-1437695683665201866" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="-7817169320884990698" xil_pn:start_ts="1336092323">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
399,15 → 399,15
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1336089864" xil_pn:in_ck="-5263026143922103232" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5582947192412673156" xil_pn:start_ts="1336089862">
<transform xil_pn:end_ts="1336092353" xil_pn:in_ck="-5263026143922103232" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5582947192412673156" xil_pn:start_ts="1336092352">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1336089917" xil_pn:in_ck="-5263026143922103232" xil_pn:name="TRAN_analyzeDesignUsingChipscope" xil_pn:prop_ck="-7171404100274592149" xil_pn:start_ts="1336089917">
<transform xil_pn:end_ts="1336092390" xil_pn:in_ck="-5263026143922103232" xil_pn:name="TRAN_analyzeDesignUsingChipscope" xil_pn:prop_ck="-7171404100274592149" xil_pn:start_ts="1336092389">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1336089848" xil_pn:in_ck="-5119142186248317927" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1336089846">
<transform xil_pn:end_ts="1336092323" xil_pn:in_ck="-5119142186248317927" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1336092321">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="INTERCON_P2P.twr"/>
/trunk/hdl/iseProject/debugChip.cdc
1,5 → 1,5
#ChipScope Core Inserter Project File Version 3.0
#Fri May 04 02:01:35 CEST 2012
#Fri May 04 02:43:15 CEST 2012
Project.device.designInputFile=E\:\\uart_block\\hdl\\iseProject\\INTERCON_P2P_cs.ngc
Project.device.designOutputFile=E\:\\uart_block\\hdl\\iseProject\\INTERCON_P2P_cs.ngc
Project.device.deviceFamily=13
6,15 → 6,19
Project.device.enableRPMs=true
Project.device.outputDirectory=E\:\\uart_block\\hdl\\iseProject\\_ngo
Project.device.useSRL16=true
Project.filter.dimension=8
Project.filter<0>=
Project.filter<1>=*_OBUF*
Project.filter<2>=*_OBUF
Project.filter<3>=_OBUF
Project.filter<4>=*DAT_*
Project.filter<5>=*byte*
Project.filter<6>=byte*
Project.filter<7>=byte
Project.filter.dimension=12
Project.filter<0>=*genTick*
Project.filter<10>=byte*
Project.filter<11>=byte
Project.filter<1>=*baud*
Project.filter<2>=*avai*
Project.filter<3>=*rx*
Project.filter<4>=
Project.filter<5>=*_OBUF*
Project.filter<6>=*_OBUF
Project.filter<7>=_OBUF
Project.filter<8>=*DAT_*
Project.filter<9>=*byte*
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
21,25 → 25,25
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockChannel=EXTCLK_BUFGP
Project.unit<0>.clockChannel=uUartWishboneSlave/uUartCommunicationBlocks/uBaudGen/genTickOverSample
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataChannel<0>=uMasterSerial/DAT_O<0>
Project.unit<0>.dataChannel<1>=uMasterSerial/DAT_O<1>
Project.unit<0>.dataChannel<2>=uMasterSerial/DAT_O<2>
Project.unit<0>.dataChannel<3>=uMasterSerial/DAT_O<3>
Project.unit<0>.dataChannel<4>=uMasterSerial/DAT_O<4>
Project.unit<0>.dataChannel<5>=uMasterSerial/DAT_O<5>
Project.unit<0>.dataChannel<6>=uMasterSerial/DAT_O<6>
Project.unit<0>.dataChannel<7>=uMasterSerial/DAT_O<7>
Project.unit<0>.dataChannel<0>=rx_IBUF
Project.unit<0>.dataChannel<1>=uUartWishboneSlave/uUartCommunicationBlocks/uBaudGen/genTick
Project.unit<0>.dataChannel<2>=uUartWishboneSlave/uUartCommunicationBlocks/uBaudGen/genTickOverSample
Project.unit<0>.dataChannel<3>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<3>
Project.unit<0>.dataChannel<4>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<4>
Project.unit<0>.dataChannel<5>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<5>
Project.unit<0>.dataChannel<6>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<6>
Project.unit<0>.dataChannel<7>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<7>
Project.unit<0>.dataDepth=512
Project.unit<0>.dataEqualsTrigger=true
Project.unit<0>.dataPortWidth=8
Project.unit<0>.dataEqualsTrigger=false
Project.unit<0>.dataPortWidth=3
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=false
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<0>
Project.unit<0>.triggerChannel<0><0>=rx_IBUF
Project.unit<0>.triggerChannel<0><1>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<1>
Project.unit<0>.triggerChannel<0><2>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<2>
Project.unit<0>.triggerChannel<0><3>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<3>
53,7 → 57,7
Project.unit<0>.triggerMatchType<0><0>=0
Project.unit<0>.triggerPortCount=1
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortWidth<0>=8
Project.unit<0>.triggerPortWidth<0>=1
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=0
Project.unit<0>.type=ilapro
/trunk/hdl/iseProject/webtalk_pn.xml
3,10 → 3,10
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Fri May 04 02:03:58 2012">
<application name="pn" timeStamp="Fri May 04 02:45:12 2012">
<section name="Project Information" visible="false">
<property name="ProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="project"/>
<property name="ProjectIteration" value="23" type="project"/>
<property name="ProjectIteration" value="24" type="project"/>
<property name="ProjectFile" value="E:/uart_block/hdl/iseProject/iseProject.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2012-04-20T22:53:04" type="project"/>
</section>
27,7 → 27,7
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2012-04-20T22:53:04" type="design"/>
<property name="PROP_intWbtProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="design"/>
<property name="PROP_intWbtProjectIteration" value="23" type="process"/>
<property name="PROP_intWbtProjectIteration" value="24" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
/trunk/hdl/iseProject/_xmsgs/xst.xmsgs
29,6 → 29,9
<msg type="warning" file="Xst" num="1305" delta="old" >Output &lt;<arg fmt="%s" index="1">SEL_O</arg>&gt; is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
</msg>
 
<msg type="warning" file="Xst" num="646" delta="new" >Signal &lt;<arg fmt="%s" index="1">pega_eu</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1306" delta="old" >Output &lt;<arg fmt="%s" index="1">data_avaible</arg>&gt; is never assigned.
</msg>
 
/trunk/hdl/iseProject/xst/work/hdpdeps.ref
9,73 → 9,73
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_main_blocks.vhd 2012/04/30.12:49:26 O.87xd
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/04/30.18:16:53 O.87xd
FL E:/uart_block/hdl/iseProject/baud_generator.vhd 2012/05/01.21:07:49 O.87xd
EN work/baud_generator 1336089722 \
EN work/baud_generator 1336091575 \
FL E:/uart_block/hdl/iseProject/baud_generator.vhd PB ieee/std_logic_1164 1325952872 \
PB ieee/STD_LOGIC_UNSIGNED 1325952875 PB ieee/std_logic_arith 1325952873 \
PB ieee/NUMERIC_STD 1325952877 PB work/pkgDefinitions 1336089721
AR work/baud_generator/Behavioral 1336089723 \
FL E:/uart_block/hdl/iseProject/baud_generator.vhd EN work/baud_generator 1336089722
PB ieee/NUMERIC_STD 1325952877 PB work/pkgDefinitions 1336091574
AR work/baud_generator/Behavioral 1336091576 \
FL E:/uart_block/hdl/iseProject/baud_generator.vhd EN work/baud_generator 1336091575
FL E:/uart_block/hdl/iseProject/divisor.vhd 2012/05/01.21:07:49 O.87xd
EN work/divisor 1336089728 FL E:/uart_block/hdl/iseProject/divisor.vhd \
EN work/divisor 1336091581 FL E:/uart_block/hdl/iseProject/divisor.vhd \
PB ieee/std_logic_1164 1325952872 PB ieee/std_logic_arith 1325952873 \
PB work/pkgDefinitions 1336089721
AR work/divisor/Behavioral 1336089729 \
FL E:/uart_block/hdl/iseProject/divisor.vhd EN work/divisor 1336089728
PB work/pkgDefinitions 1336091574
AR work/divisor/Behavioral 1336091582 \
FL E:/uart_block/hdl/iseProject/divisor.vhd EN work/divisor 1336091581
FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd 2012/05/04.00:27:06 O.87xd
EN work/INTERCON_P2P 1336089740 FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd \
EN work/INTERCON_P2P 1336091593 FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd \
PB ieee/std_logic_1164 1325952872
AR work/INTERCON_P2P/Behavioral 1336089741 \
FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd EN work/INTERCON_P2P 1336089740 \
AR work/INTERCON_P2P/Behavioral 1336091594 \
FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd EN work/INTERCON_P2P 1336091593 \
CP SYC0001a CP SERIALMASTER CP uart_wishbone_slave
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/05/03.23:01:52 O.87xd
PH work/pkgDefinitions 1336089720 \
PH work/pkgDefinitions 1336091573 \
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PB ieee/std_logic_1164 1325952872
PB work/pkgDefinitions 1336089721 \
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PH work/pkgDefinitions 1336089720
PB work/pkgDefinitions 1336091574 \
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PH work/pkgDefinitions 1336091573
FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd 2012/05/04.01:05:05 O.87xd
EN work/SERIALMASTER 1336089736 FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd \
EN work/SERIALMASTER 1336091589 FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd \
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1336089721
AR work/SERIALMASTER/Behavioral 1336089737 \
FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd EN work/SERIALMASTER 1336089736
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd 2012/05/01.21:07:49 O.87xd
EN work/serial_receiver 1336089726 \
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1336091574
AR work/SERIALMASTER/Behavioral 1336091590 \
FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd EN work/SERIALMASTER 1336091589
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd 2012/05/04.02:32:50 O.87xd
EN work/serial_receiver 1336091579 \
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd PB ieee/std_logic_1164 1325952872 \
PB work/pkgDefinitions 1336089721
AR work/serial_receiver/Behavioral 1336089727 \
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd EN work/serial_receiver 1336089726
PB work/pkgDefinitions 1336091574
AR work/serial_receiver/Behavioral 1336091580 \
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd EN work/serial_receiver 1336091579
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/21.09:27:16 O.87xd
EN work/serial_transmitter 1336089724 \
EN work/serial_transmitter 1336091577 \
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336089721
AR work/serial_transmitter/Behavioral 1336089725 \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336091574
AR work/serial_transmitter/Behavioral 1336091578 \
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd \
EN work/serial_transmitter 1336089724
EN work/serial_transmitter 1336091577
FL E:/uart_block/hdl/iseProject/SYC0001a.vhd 2012/05/04.00:26:54 O.87xd
EN work/SYC0001a 1336089734 FL E:/uart_block/hdl/iseProject/SYC0001a.vhd \
EN work/SYC0001a 1336091587 FL E:/uart_block/hdl/iseProject/SYC0001a.vhd \
PB ieee/std_logic_1164 1325952872
AR work/SYC0001a/SYC0001a1 1336089735 \
FL E:/uart_block/hdl/iseProject/SYC0001a.vhd EN work/SYC0001a 1336089734
AR work/SYC0001a/SYC0001a1 1336091588 \
FL E:/uart_block/hdl/iseProject/SYC0001a.vhd EN work/SYC0001a 1336091587
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd 2012/04/30.23:14:46 O.87xd
EN work/uart_communication_blocks 1336089732 \
EN work/uart_communication_blocks 1336091585 \
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336089721
AR work/uart_communication_blocks/Behavioral 1336089733 \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336091574
AR work/uart_communication_blocks/Behavioral 1336091586 \
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd \
EN work/uart_communication_blocks 1336089732 CP baud_generator \
EN work/uart_communication_blocks 1336091585 CP baud_generator \
CP serial_transmitter CP serial_receiver
FL E:/uart_block/hdl/iseProject/uart_control.vhd 2012/05/03.19:17:33 O.87xd
EN work/uart_control 1336089730 FL E:/uart_block/hdl/iseProject/uart_control.vhd \
EN work/uart_control 1336091583 FL E:/uart_block/hdl/iseProject/uart_control.vhd \
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1336089721
AR work/uart_control/Behavioral 1336089731 \
FL E:/uart_block/hdl/iseProject/uart_control.vhd EN work/uart_control 1336089730 \
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1336091574
AR work/uart_control/Behavioral 1336091584 \
FL E:/uart_block/hdl/iseProject/uart_control.vhd EN work/uart_control 1336091583 \
CP divisor
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/05/03.19:17:33 O.87xd
EN work/uart_wishbone_slave 1336089738 \
EN work/uart_wishbone_slave 1336091591 \
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336089721
AR work/uart_wishbone_slave/Behavioral 1336089739 \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336091574
AR work/uart_wishbone_slave/Behavioral 1336091592 \
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \
EN work/uart_wishbone_slave 1336089738 CP uart_control \
EN work/uart_wishbone_slave 1336091591 CP uart_control \
CP uart_communication_blocks
/trunk/hdl/iseProject/xst/work/hdllib.ref
1,22 → 1,22
AR uart_communication_blocks behavioral E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl13 1336089733
AR uart_control behavioral E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl11 1336089731
AR syc0001a syc0001a1 E:/uart_block/hdl/iseProject/SYC0001a.vhd sub00/vhpl17 1336089735
EN intercon_p2p NULL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd sub00/vhpl20 1336089740
PB pkgdefinitions pkgdefinitions E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1336089721
EN serial_receiver NULL E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1336089726
AR uart_wishbone_slave behavioral E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl15 1336089739
AR serial_transmitter behavioral E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1336089725
EN uart_communication_blocks NULL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl12 1336089732
EN divisor NULL E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl08 1336089728
AR divisor behavioral E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl09 1336089729
AR baud_generator behavioral E:/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl07 1336089723
EN syc0001a NULL E:/uart_block/hdl/iseProject/SYC0001a.vhd sub00/vhpl16 1336089734
EN serialmaster NULL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd sub00/vhpl18 1336089736
EN uart_control NULL E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl10 1336089730
AR intercon_p2p behavioral E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd sub00/vhpl21 1336089741
EN serial_transmitter NULL E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1336089724
PH pkgdefinitions NULL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1336089720
AR serialmaster behavioral E:/uart_block/hdl/iseProject/SERIALMASTER.vhd sub00/vhpl19 1336089737
EN uart_wishbone_slave NULL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl14 1336089738
EN baud_generator NULL E:/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl06 1336089722
AR serial_receiver behavioral E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1336089727
AR uart_communication_blocks behavioral E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl13 1336091586
AR uart_control behavioral E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl11 1336091584
AR syc0001a syc0001a1 E:/uart_block/hdl/iseProject/SYC0001a.vhd sub00/vhpl17 1336091588
EN intercon_p2p NULL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd sub00/vhpl20 1336091593
PB pkgdefinitions pkgdefinitions E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1336091574
EN serial_receiver NULL E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1336091579
AR uart_wishbone_slave behavioral E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl15 1336091592
AR serial_transmitter behavioral E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1336091578
EN uart_communication_blocks NULL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl12 1336091585
EN divisor NULL E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl08 1336091581
AR divisor behavioral E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl09 1336091582
AR baud_generator behavioral E:/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl07 1336091576
EN syc0001a NULL E:/uart_block/hdl/iseProject/SYC0001a.vhd sub00/vhpl16 1336091587
EN serialmaster NULL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd sub00/vhpl18 1336091589
EN uart_control NULL E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl10 1336091583
AR intercon_p2p behavioral E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd sub00/vhpl21 1336091594
EN serial_transmitter NULL E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1336091577
PH pkgdefinitions NULL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1336091573
AR serialmaster behavioral E:/uart_block/hdl/iseProject/SERIALMASTER.vhd sub00/vhpl19 1336091590
EN uart_wishbone_slave NULL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl14 1336091591
EN baud_generator NULL E:/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl06 1336091575
AR serial_receiver behavioral E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1336091580
/trunk/hdl/iseProject/xst/work/sub00/vhpl04.vho Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/hdl/iseProject/xst/work/sub00/vhpl05.vho Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

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