OpenCores
URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /uart_block
    from Rev 38 to Rev 39
    ↔ Reverse comparison
  •

Rev 38 → Rev 39

/trunk/hdl/iseProject/isim.log
1,5 → 1,5
ISim log file
Running: E:\uart_block\hdl\iseProject\testSerial_receiver_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb E:/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.wdb
Running: E:\uart_block\hdl\iseProject\testUart_communication_block_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb E:/uart_block/hdl/iseProject/testUart_communication_block_isim_beh.wdb
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
16,235 → 16,6
 
** Failure:NONE. End of simulation.
User(VHDL) Code Called Simulation Stop
In process testSerial_receiver.vhd:stim_proc
In process testUart_communication_block.vhd:stim_proc
INFO: Simulator is stopped.
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
Stopped at time : 107166 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 106
# step
Stopped at time : 107415 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 66
# step
Stopped at time : 107415 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 67
# step
Stopped at time : 107415 ns : File "E:/uart_block/hdl/iseProject/serial_receiver.vhd" Line 29
# step
Stopped at time : 107415 ns : File "E:/uart_block/hdl/iseProject/serial_receiver.vhd" Line 92
# run all
Stopped at time : 36220620100 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 66
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
Stopped at time : 107166 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 106
# step
Stopped at time : 107415 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 66
# run all
Stopped at time : 5831395972500 ps : File "E:/uart_block/hdl/iseProject/serial_receiver.vhd" Line 37
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
Stopped at time : 107166 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 106
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
Stopped at time : 107166 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 108
# run all
Stopped at time : 176610 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 112
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
 
** Failure:Wrong result... expected 0xC4
User(VHDL) Code Called Simulation Stop
In process testSerial_receiver.vhd:stim_proc
INFO: Simulator is stopped.
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
 
** Failure:NONE. End of simulation.
User(VHDL) Code Called Simulation Stop
In process testSerial_receiver.vhd:stim_proc
INFO: Simulator is stopped.
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
 
** Failure:Wrong result... expected 0x55
User(VHDL) Code Called Simulation Stop
In process testSerial_receiver.vhd:stim_proc
INFO: Simulator is stopped.
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
Stopped at time : 107166 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 105
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
Stopped at time : 107166 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 105
# run all
Stopped at time : 7368665202500 ps : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 68
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
Stopped at time : 107166 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 105
# run all
Stopped at time : 45201791145 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 66
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
Stopped at time : 105787500 ps : File "E:/uart_block/hdl/iseProject/serial_receiver.vhd" Line 186
# run all
Stopped at time : 107166 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 105
# run all
Stopped at time : 12853995542500 ps : File "E:/uart_block/hdl/iseProject/serial_receiver.vhd" Line 33
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
Stopped at time : 107166 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 107
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
Stopped at time : 107166 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 107
# run all
 
** Failure:NONE. End of simulation.
User(VHDL) Code Called Simulation Stop
In process testSerial_receiver.vhd:stim_proc
INFO: Simulator is stopped.
/trunk/hdl/iseProject/fuseRelaunch.cmd
1,235 → 16,6
-intstyle "ise" -incremental -o "E:/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe" -prj "E:/uart_block/hdl/iseProject/testSerial_receiver_beh.prj" "testSerial_receiver"
-intstyle "ise" -incremental -o "E:/uart_block/hdl/iseProject/testUart_communication_block_isim_beh.exe" -prj "E:/uart_block/hdl/iseProject/testUart_communication_block_beh.prj" "work.testUart_communication_block"
/trunk/hdl/iseProject/fuse.log
1,21 → 1,31
Running: fuse.exe -relaunch -intstyle "ise" -incremental -o "E:/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe" -prj "E:/uart_block/hdl/iseProject/testSerial_receiver_beh.prj" "testSerial_receiver"
Running: e:\Xilinx\13.4\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -o E:/uart_block/hdl/iseProject/testUart_communication_block_isim_beh.exe -prj E:/uart_block/hdl/iseProject/testUart_communication_block_beh.prj work.testUart_communication_block
ISim O.87xd (signature 0xc3576ebc)
Number of CPUs detected in this system: 8
Turning on mult-threading, number of parallel sub-compilation jobs: 16
Determining compilation order of HDL files
Parsing VHDL file "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/serial_transmitter.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/serial_receiver.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/baud_generator.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd" into library work
WARNING:HDLCompiler:946 - "E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd" Line 65: Actual for formal port rst is neither a static name nor a globally static expression
Parsing VHDL file "E:/uart_block/hdl/iseProject/testUart_communication_block.vhd" into library work
Starting static elaboration
Completed static elaboration
Compiling package standard
Compiling package std_logic_1164
Compiling package std_logic_arith
Compiling package std_logic_unsigned
Compiling package pkgdefinitions
Compiling package numeric_std
Compiling architecture behavioral of entity baud_generator [baud_generator_default]
Compiling architecture behavioral of entity serial_transmitter [serial_transmitter_default]
Compiling architecture behavioral of entity serial_receiver [serial_receiver_default]
Compiling architecture behavior of entity testserial_receiver
Compiling architecture behavioral of entity uart_communication_blocks [uart_communication_blocks_defaul...]
Compiling architecture behavior of entity testuart_communication_block
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 6 VHDL Units
Built simulation executable E:/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe
Fuse Memory Usage: 29596 KB
Fuse CPU Usage: 234 ms
Compiled 15 VHDL Units
Built simulation executable E:/uart_block/hdl/iseProject/testUart_communication_block_isim_beh.exe
Fuse Memory Usage: 37044 KB
Fuse CPU Usage: 420 ms
/trunk/hdl/iseProject/testSerial_transmitter.vhd
1,4 → 1,7
--! Test serial_transmitter module
--! @file
--! @brief Test serial_transmitter module
 
--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
8,6 → 11,8
ENTITY testSerial_transmitter IS
END testSerial_transmitter;
--! @brief Test serial_transmitter module
--! @details Just send the date over the serial_out and analyse the results
ARCHITECTURE behavior OF testSerial_transmitter IS
-- Component Declaration for the Unit Under Test (UUT)
62,6 → 67,19
data_byte <= "01010101";
wait for 50 ns;
rst <= '0';
-- Test serial data...
wait until rising_edge(baudClk); -- Start bit
wait for 1 ns;
assert serial_out = '0' report "Invalid value " severity failure;
for numBit in 0 to 7 loop
wait until rising_edge(baudClk);
wait for 1 ns;
-- The image attribute convert a typed value into a string
report "Testing bit:" & integer'image(numBit) & " value " & std_logic'image(serial_out);
assert serial_out = data_byte(numBit) report "Invalid value on bit:" severity failure;
end loop;
 
wait until data_sent = '1';
wait for baudClk_period*3;
71,6 → 89,20
data_byte <= "11000100";
wait for 50 ns;
rst <= '0';
-- Test serial data...
wait until rising_edge(baudClk); -- Start bit
wait for 1 ns;
assert serial_out = '0' report "Invalid value " severity failure;
for numBit in 0 to (data_byte'LENGTH-1) loop
-- Wait for the clock rising edge
wait until rising_edge(baudClk);
wait for 1 ns;
report "Testing bit:" & integer'image(numBit) & " value " & std_logic'image(serial_out);
assert serial_out = data_byte(numBit) report "Invalid value on bit:" severity failure;
end loop;
 
wait until data_sent = '1';
wait for baudClk_period*3;
/trunk/hdl/iseProject/iseProject.xise
16,7 → 16,7
 
<files>
<file xil_pn:name="serial_transmitter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="pkgDefinitions.vhd" xil_pn:type="FILE_VHDL">
30,11 → 30,11
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="serial_receiver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="testSerial_receiver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="40"/>
50,7 → 50,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="baud_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="testBaud_generator.vhd" xil_pn:type="FILE_VHDL">
64,13 → 64,13
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="testUart_communication_block.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="103"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="103"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="103"/>
</file>
<file xil_pn:name="uart_communication_blocks.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="testUart_control.vhd" xil_pn:type="FILE_VHDL">
331,8 → 331,8
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testSerial_receiver" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testSerial_receiver" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testUart_communication_block" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testUart_communication_block" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
348,7 → 348,7
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testSerial_receiver" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testUart_communication_block" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
398,7 → 398,7
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testSerial_receiver|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testUart_communication_block|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="iseProject" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
/trunk/hdl/iseProject/iseProject.gise
146,11 → 146,12
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="serial_transmitter_xst.xrpt"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testBaud_generator_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testDivisor_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testSerial_receiver_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testSerial_receiver_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testSerial_receiver_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testSerial_transmitter_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testUart_communication_block_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testUart_communication_block_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testUart_communication_block_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testUart_control_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testUart_wishbone_slave_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testUart_wishbone_slave_isim_beh.wdb"/>
203,7 → 204,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1336603169" xil_pn:in_ck="8052531156335828411" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1336603169">
<transform xil_pn:end_ts="1336851239" xil_pn:in_ck="8052531156335828411" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1336851239">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="INTERCON_P2P.vhd"/>
225,11 → 226,11
<outfile xil_pn:name="uart_control.vhd"/>
<outfile xil_pn:name="uart_wishbone_slave.vhd"/>
</transform>
<transform xil_pn:end_ts="1336603169" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-8542187049970039926" xil_pn:start_ts="1336603169">
<transform xil_pn:end_ts="1336851239" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="1763861231223327121" xil_pn:start_ts="1336851239">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1336603169" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="8521261985131728908" xil_pn:start_ts="1336603169">
<transform xil_pn:end_ts="1336851239" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-3978620576363339309" xil_pn:start_ts="1336851239">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
237,7 → 238,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1336603169" xil_pn:in_ck="8052531156335828411" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1336603169">
<transform xil_pn:end_ts="1336851239" xil_pn:in_ck="8052531156335828411" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1336851239">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="INTERCON_P2P.vhd"/>
259,22 → 260,22
<outfile xil_pn:name="uart_control.vhd"/>
<outfile xil_pn:name="uart_wishbone_slave.vhd"/>
</transform>
<transform xil_pn:end_ts="1336603171" xil_pn:in_ck="8052531156335828411" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-728369216885656586" xil_pn:start_ts="1336603169">
<transform xil_pn:end_ts="1336851242" xil_pn:in_ck="8052531156335828411" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-1520739801670331996" xil_pn:start_ts="1336851239">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testSerial_receiver_beh.prj"/>
<outfile xil_pn:name="testSerial_receiver_isim_beh.exe"/>
<outfile xil_pn:name="testUart_communication_block_beh.prj"/>
<outfile xil_pn:name="testUart_communication_block_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1336603172" xil_pn:in_ck="7043554240611338668" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="1766511671646254562" xil_pn:start_ts="1336603171">
<transform xil_pn:end_ts="1336851242" xil_pn:in_ck="7043554240611338668" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-4664289266449917424" xil_pn:start_ts="1336851242">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testSerial_receiver_isim_beh.wdb"/>
<outfile xil_pn:name="testUart_communication_block_isim_beh.wdb"/>
</transform>
<transform xil_pn:end_ts="1335914570" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1335914570">
<status xil_pn:value="SuccessfullyRun"/>
308,6 → 309,8
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="INTERCON_P2P.lso"/>
<outfile xil_pn:name="INTERCON_P2P.ngc"/>
<outfile xil_pn:name="INTERCON_P2P.ngr"/>
336,67 → 339,47
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="INTERCON_P2P.bld"/>
<outfile xil_pn:name="INTERCON_P2P.ngd"/>
<outfile xil_pn:name="INTERCON_P2P_cs.blc"/>
<outfile xil_pn:name="INTERCON_P2P_cs.ngc"/>
<outfile xil_pn:name="INTERCON_P2P_ngdbuild.xrpt"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1336513228" xil_pn:in_ck="7070038919220904605" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1336513221">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="NotReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="INTERCON_P2P.pcf"/>
<outfile xil_pn:name="INTERCON_P2P_map.map"/>
<outfile xil_pn:name="INTERCON_P2P_map.mrp"/>
<outfile xil_pn:name="INTERCON_P2P_map.ncd"/>
<outfile xil_pn:name="INTERCON_P2P_map.ngm"/>
<outfile xil_pn:name="INTERCON_P2P_map.xrpt"/>
<outfile xil_pn:name="INTERCON_P2P_summary.xml"/>
<outfile xil_pn:name="INTERCON_P2P_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1336513241" xil_pn:in_ck="5901297062896623158" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1336513228">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="NotReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="INTERCON_P2P.ncd"/>
<outfile xil_pn:name="INTERCON_P2P.pad"/>
<outfile xil_pn:name="INTERCON_P2P.par"/>
<outfile xil_pn:name="INTERCON_P2P.ptwx"/>
<outfile xil_pn:name="INTERCON_P2P.unroutes"/>
<outfile xil_pn:name="INTERCON_P2P.xpi"/>
<outfile xil_pn:name="INTERCON_P2P_pad.csv"/>
<outfile xil_pn:name="INTERCON_P2P_pad.txt"/>
<outfile xil_pn:name="INTERCON_P2P_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1336513346" xil_pn:in_ck="-1437695683665201866" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="-7817169320884990698" xil_pn:start_ts="1336513333">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="NotReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="INTERCON_P2P.ut"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="intercon_p2p.bgn"/>
<outfile xil_pn:name="intercon_p2p.bit"/>
<outfile xil_pn:name="intercon_p2p.drc"/>
<outfile xil_pn:name="usage_statistics_webtalk.html"/>
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1336249692" xil_pn:in_ck="-5263026143922103232" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5582947192412673156" xil_pn:start_ts="1336249691">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="NotReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
404,7 → 387,7
</transform>
<transform xil_pn:end_ts="1336249854" xil_pn:in_ck="-5263026143922103232" xil_pn:name="TRAN_analyzeDesignUsingChipscope" xil_pn:prop_ck="-7171404100274592149" xil_pn:start_ts="1336249853">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="NotReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
412,7 → 395,7
</transform>
<transform xil_pn:end_ts="1336243447" xil_pn:in_ck="-5119142186248317927" xil_pn:name="TRAN_fpgaFloorplanPostPAR" xil_pn:start_ts="1336243447">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="NotReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputAdded"/>
421,11 → 404,12
</transform>
<transform xil_pn:end_ts="1336513241" xil_pn:in_ck="-5119142186248317927" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1336513238">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="NotReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="INTERCON_P2P.twr"/>
<outfile xil_pn:name="INTERCON_P2P.twx"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
</transforms>
 
/trunk/hdl/iseProject/iseconfig/iseProject.projectmgr
7,7 → 7,7
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode>/INTERCON_P2P - Behavioral E:|uart_block|hdl|iseProject|INTERCON_P2P.vhd/uUartWishboneSlave - uart_wishbone_slave - Behavioral</ClosedNode>
<ClosedNode>/INTERCON_P2P - Behavioral E:|uart_block|hdl|iseProject|INTERCON_P2P.vhd</ClosedNode>
<ClosedNode>/INTERCON_P2P - Behavioral |home|laraujo|work|uart_block|hdl|iseProject|INTERCON_P2P.vhd/uUartWishboneSlave - uart_wishbone_slave - Behavioral</ClosedNode>
<ClosedNode>/serial_transmitter - Behavioral E:|uart_block|hdl|iseProject|serial_transmitter.vhd</ClosedNode>
<ClosedNode>/uart_wishbone_slave - Behavioral |home|laraujo|work|uart_block|hdl|iseProject|uart_wishbone_slave.vhd/uUartCommunicationBlocks - uart_communication_blocks - Behavioral</ClosedNode>
18,7 → 18,7
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001ef000000020000000000000000000000000200000064ffffffff000000810000000300000002000001ef0000000100000003000000000000000100000003</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000147000000020000000000000000000000000200000064ffffffff000000810000000300000002000001470000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>INTERCON_P2P - Behavioral (E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd)</CurrentItem>
</ItemView>
76,13 → 76,13
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Analyze Design Using ChipScope</SelectedItem>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000153000000010000000100000000000000000000000064ffffffff000000810000000000000001000001530000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000e6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e60000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Analyze Design Using ChipScope</CurrentItem>
<CurrentItem></CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
98,23 → 98,26
<ClosedNode>/testSerial_transmitter - behavior E:|uart_block|hdl|iseProject|testSerial_transmitter.vhd</ClosedNode>
<ClosedNode>/testSerial_transmitter - behavior |home|laraujo|work|uart_block|hdl|iseProject|testSerial_transmitter.vhd</ClosedNode>
<ClosedNode>/testUart_communication_block - behavior E:|uart_block|hdl|iseProject|testUart_communication_block.vhd</ClosedNode>
<ClosedNode>/testUart_communication_block - behavior E:|uart_block|hdl|iseProject|testUart_communication_block.vhd/uut - uart_communication_blocks - Behavioral</ClosedNode>
<ClosedNode>/testUart_communication_block - behavior |home|laraujo|work|uart_block|hdl|iseProject|testUart_communication_block.vhd</ClosedNode>
<ClosedNode>/testUart_control - behavior E:|uart_block|hdl|iseProject|testUart_control.vhd</ClosedNode>
<ClosedNode>/testUart_control - behavior E:|uart_block|hdl|iseProject|testUart_control.vhd/uut - uart_control - Behavioral</ClosedNode>
<ClosedNode>/testUart_control - behavior |home|laraujo|work|uart_block|hdl|iseProject|testUart_control.vhd</ClosedNode>
<ClosedNode>/testUart_control - behavior |home|laraujo|work|uart_block|hdl|iseProject|testUart_control.vhd/uut - uart_control - Behavioral</ClosedNode>
<ClosedNode>/testUart_wishbone_slave - behavior E:|uart_block|hdl|iseProject|testUart_wishbone_slave.vhd</ClosedNode>
<ClosedNode>/testUart_wishbone_slave - behavior E:|uart_block|hdl|iseProject|testUart_wishbone_slave.vhd/uut - uart_wishbone_slave - Behavioral</ClosedNode>
<ClosedNode>/testUart_wishbone_slave - behavior |home|laraujo|work|uart_block|hdl|iseProject|testUart_wishbone_slave.vhd</ClosedNode>
<ClosedNode>/testUart_wishbone_slave - behavior |home|laraujo|work|uart_block|hdl|iseProject|testUart_wishbone_slave.vhd/uut - uart_wishbone_slave - Behavioral/uUartCommunicationBlocks - uart_communication_blocks - Behavioral</ClosedNode>
<ClosedNode>/testUart_wishbone_slave - behavior |home|laraujo|work|uart_block|hdl|iseProject|testUart_wishbone_slave.vhd/uut - uart_wishbone_slave - Behavioral/uUartControl - uart_control - Behavioral</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>testUart_communication_block - behavior (E:/uart_block/hdl/iseProject/testUart_communication_block.vhd)</SelectedItem>
<SelectedItem>testSerial_transmitter - behavior (E:/uart_block/hdl/iseProject/testSerial_transmitter.vhd)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001bd000000020000000000000000000000000200000064ffffffff000000810000000300000002000001bd0000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>testUart_communication_block - behavior (E:/uart_block/hdl/iseProject/testUart_communication_block.vhd)</CurrentItem>
<CurrentItem>testSerial_transmitter - behavior (E:/uart_block/hdl/iseProject/testSerial_transmitter.vhd)</CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
<ClosedNodes>
139,12 → 142,12
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Simulate Behavioral Model</CurrentItem>
</ItemView>
<SourceProcessView>000000ff00000000000000020000011b0000011b01000000040100000002</SourceProcessView>
<CurrentView>Implementation</CurrentView>
<SourceProcessView>000000ff0000000000000002000001230000012401000000040100000002</SourceProcessView>
<CurrentView>Behavioral Simulation</CurrentView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_PACKAGE_BODY" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
171,4 → 174,18
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000163000000010000000100000000000000000000000064ffffffff000000810000000000000001000001630000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
</ItemView>
</Project>
/trunk/hdl/iseProject/testSerial_receiver_isim_beh.wdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/hdl/iseProject/testUart_communication_block.vhd
1,4 → 1,7
--! Test baud_generator module
--! @file
--! @brief Test communication block
 
--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
10,6 → 13,8
ENTITY testUart_communication_block IS
END testUart_communication_block;
--! @brief Test communication block
--! @details This will include all blocks used in uart (transmiter, receiver, baud generator)
ARCHITECTURE behavior OF testUart_communication_block IS
-- Component Declaration for the Unit Under Test (UUT)
/trunk/hdl/iseProject/_xmsgs/pn_parser.xmsgs
8,7 → 8,7
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/uart_block/hdl/iseProject/testSerial_receiver.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/uart_block/hdl/iseProject/testUart_communication_block.vhd&quot; into library work</arg>
</msg>
 
</messages>
/trunk/hdl/iseProject/fuse.xmsgs
5,5 → 5,8
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="HDLCompiler" num="946" delta="unknown" >"E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd" Line 65: Actual for formal port <arg fmt="%s" index="1">rst</arg> is neither a static name nor a globally static expression
</msg>
 
</messages>
 
/trunk/docs/Advanced testing with VHDL.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/docs/Advanced testing with VHDL.pdf
trunk/docs/Advanced testing with VHDL.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property

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