URL
https://opencores.org/ocsvn/udp_ip_stack/udp_ip_stack/trunk
Subversion Repositories udp_ip_stack
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- This comparison shows the changes necessary to convert path
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- from Rev 5 to Rev 4
- ↔ Reverse comparison
Rev 5 → Rev 4
/udp_ip_stack/tags/v1.1/rtl/vhdl/IPv4.vhd
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/udp_ip_stack/tags/v1.1/rtl/vhdl/arp.vhd
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/udp_ip_stack/tags/v1.1/rtl/vhdl/UDP_TX.vhd
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/udp_ip_stack/tags/v1.1/rtl/vhdl/tx_arbitrator.vhd
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/udp_ip_stack/tags/v1.1/rtl/vhdl/arp_types.vhd
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/udp_ip_stack/tags/v1.1/rtl/vhdl/ipv4_types.vhd
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/udp_ip_stack/tags/v1.1/rtl/vhdl/IPv4_RX.vhd
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/udp_ip_stack/tags/v1.1/rtl/vhdl/IPv4_TX.vhd
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/udp_ip_stack/tags/v1.1/rtl/vhdl/UDP_RX.vhd
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/udp_ip_stack/tags/v1.1/rtl/vhdl/axi.vhd
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/udp_ip_stack/tags/v1.1/doc/UDP_IP_Stack.pdf
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udp_ip_stack/tags/v1.1/doc/UDP_IP_Stack.pdf
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Index: udp_ip_stack/tags/v1.1/doc/release_notes.txt
===================================================================
--- udp_ip_stack/tags/v1.1/doc/release_notes.txt (revision 5)
+++ udp_ip_stack/tags/v1.1/doc/release_notes.txt (nonexistent)
@@ -1,6 +0,0 @@
-V1.1 - Added mac_tx_tfirst output to assist coupling to MAC layers that require a start of frame indication.
- Migration Notes: V1.0 to V1.1
- - The entity declaration for UDP_Complete_nomac and IP_Complete_nomac have changed.
- - if you dont need to use the new mac_tx_tfirst output, leave it open.
-
-V1.0 - initial release
Index: udp_ip_stack/tags/v1.1/doc/src/UDP_IP_Stack.pptx
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Index: udp_ip_stack/tags/v1.1/doc/src/UDP_IP_Stack.pptx
===================================================================
--- udp_ip_stack/tags/v1.1/doc/src/UDP_IP_Stack.pptx (revision 5)
+++ udp_ip_stack/tags/v1.1/doc/src/UDP_IP_Stack.pptx (nonexistent)
udp_ip_stack/tags/v1.1/doc/src/UDP_IP_Stack.pptx
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Index: udp_ip_stack/tags/v1.1/doc/src/zero latency receive.jpg
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Index: udp_ip_stack/tags/v1.1/doc/src/zero latency receive.jpg
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--- udp_ip_stack/tags/v1.1/doc/src/zero latency receive.jpg (revision 5)
+++ udp_ip_stack/tags/v1.1/doc/src/zero latency receive.jpg (nonexistent)
udp_ip_stack/tags/v1.1/doc/src/zero latency receive.jpg
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Index: udp_ip_stack/tags/v1.1/sw/UDPCxn.java
===================================================================
--- udp_ip_stack/tags/v1.1/sw/UDPCxn.java (revision 5)
+++ udp_ip_stack/tags/v1.1/sw/UDPCxn.java (nonexistent)
@@ -1,72 +0,0 @@
-package com.pjf;
-
-import java.io.IOException;
-import java.net.DatagramPacket;
-import java.net.DatagramSocket;
-import java.net.InetAddress;
-import java.net.SocketException;
-import java.net.UnknownHostException;
-
-
-public class UDPCxn {
- private DatagramSocket skt;
- private InetAddress dstIP;
-
- public UDPCxn(long dstIPadr) throws SocketException, UnknownHostException {
- skt = new DatagramSocket();
- byte[] target = new byte[4];
- target[0] = (byte) ((dstIPadr >> 24) & 0xff);
- target[1] = (byte) ((dstIPadr >> 16) & 0xff);
- target[2] = (byte) ((dstIPadr >> 8) & 0xff);
- target[3] = (byte) (dstIPadr & 0xff);
- dstIP = InetAddress.getByAddress(target);
- }
-
- public UDPCxn(String dstIPadr) throws SocketException, UnknownHostException {
- skt = new DatagramSocket();
- String[] parts = dstIPadr.split("[.]");
- if (parts.length != 4) {
- throw new UnknownHostException("ip addr must have 4 parts");
- }
- byte[] target = new byte[4];
- for (int i = 0; i<4; i++) {
- target[i] = (byte) Integer.parseInt(parts[i]);
- }
- dstIP = InetAddress.getByAddress(target);
- }
-
- public void send(byte[] data, int port) throws IOException {
- DatagramPacket pkt = new DatagramPacket(data, data.length, dstIP, port);
- System.out.println("Sending packet");
- skt.send(pkt);
- }
-
- public void fixSend(String str, int port, boolean print) throws IOException {
- String s1 = str.replace('~','\001');
- byte[] data = s1.getBytes();
- DatagramPacket pkt = new DatagramPacket(data, data.length, dstIP, port);
- if (print) {
- System.out.println("Sending packet: " + str + " on port " + port);
- }
- skt.send(pkt);
- }
-
-
- public byte[] rcv() throws IOException {
- byte[] buf = new byte[1024];
- DatagramPacket pkt = new DatagramPacket(buf, buf.length);
-// System.out.println("waiting to receive ...");
- skt.receive(pkt);
- int len = pkt.getLength();
- byte[] rd = pkt.getData();
- byte[] data = new byte[len];
- for (int i=0; i=150; price--) {
- StringBuffer fixmsg = new StringBuffer(fix1);
- fixmsg.append(Integer.toString(price));
- fixmsg.append(fix2);
- System.out.println("Sending price tick " + price);
- cxn.fixSend(fixmsg.toString(), 2000, false);
- }
- Thread.sleep(2000);
- }
-
-
- public static void main(String[] args) {
- UDPTestStream ut;
- try {
- ut = new UDPTestStream();
- ut.go();
- } catch (Exception e) {
- e.printStackTrace();
- }
- }
-
-
-}
Index: udp_ip_stack/tags/v1.1/sw/UDPTest.java
===================================================================
--- udp_ip_stack/tags/v1.1/sw/UDPTest.java (revision 5)
+++ udp_ip_stack/tags/v1.1/sw/UDPTest.java (nonexistent)
@@ -1,34 +0,0 @@
-package com.pjf;
-
-import java.io.IOException;
-import java.net.SocketException;
-import java.net.UnknownHostException;
-
-public class UDPTest {
- private UDPCxn cxn;
-
- public UDPTest() throws SocketException, UnknownHostException {
- cxn = new UDPCxn("192.168.5.9");
- }
-
- public void go() throws IOException {
- String fix1 = "1=45~34=201~18=23~";
- cxn.fixSend(fix1, 2000, true);
- byte[] rep = cxn.rcv();
- String reply = new String(rep);
- System.out.println("Got [" + reply + "]");
- }
-
-
- public static void main(String[] args) {
- UDPTest ut;
- try {
- ut = new UDPTest();
- ut.go();
- } catch (Exception e) {
- e.printStackTrace();
- }
- }
-
-
-}
Index: udp_ip_stack/tags/v1.1/sw/test_results/UDPTest_console.txt
===================================================================
--- udp_ip_stack/tags/v1.1/sw/test_results/UDPTest_console.txt (revision 5)
+++ udp_ip_stack/tags/v1.1/sw/test_results/UDPTest_console.txt (nonexistent)
@@ -1,2 +0,0 @@
-Sending packet: 1=45~34=201~18=23~ on port 2000
-Got [@ABC]
Index: udp_ip_stack/tags/v1.1/sw/test_results/UDPTest_wireshark.pcap
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Index: udp_ip_stack/tags/v1.1/sw/test_results/UDPTest_wireshark.pcap
===================================================================
--- udp_ip_stack/tags/v1.1/sw/test_results/UDPTest_wireshark.pcap (revision 5)
+++ udp_ip_stack/tags/v1.1/sw/test_results/UDPTest_wireshark.pcap (nonexistent)
udp_ip_stack/tags/v1.1/sw/test_results/UDPTest_wireshark.pcap
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Index: udp_ip_stack/tags/v1.1/sw/test_results/UDPTestStream_console.txt
===================================================================
--- udp_ip_stack/tags/v1.1/sw/test_results/UDPTestStream_console.txt (revision 5)
+++ udp_ip_stack/tags/v1.1/sw/test_results/UDPTestStream_console.txt (nonexistent)
@@ -1,152 +0,0 @@
-Sending price tick 225
-Sending price tick 224
-Sending price tick 223
-Sending price tick 222
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-Sending price tick 220
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-Sending price tick 205
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-Sending price tick 203
-Sending price tick 202
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Sending price tick 201
-Sending price tick 200
-Sending price tick 199
-Got [@ABC]
-Sending price tick 198
-Sending price tick 197
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Sending price tick 196
-Sending price tick 195
-Got [@ABC]
-Sending price tick 194
-Sending price tick 193
-Got [@ABC]
-Sending price tick 192
-Sending price tick 191
-Got [@ABC]
-Sending price tick 190
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Sending price tick 189
-Sending price tick 188
-Sending price tick 187
-Got [@ABC]
-Got [@ABC]
-Sending price tick 186
-Got [@ABC]
-Sending price tick 185
-Sending price tick 184
-Got [@ABC]
-Sending price tick 183
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Sending price tick 182
-Sending price tick 181
-Got [@ABC]
-Sending price tick 180
-Got [@ABC]
-Sending price tick 179
-Got [@ABC]
-Sending price tick 178
-Sending price tick 177
-Got [@ABC]
-Sending price tick 176
-Got [@ABC]
-Sending price tick 175
-Got [@ABC]
-Got [@ABC]
-Sending price tick 174
-Sending price tick 173
-Got [@ABC]
-Sending price tick 172
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Sending price tick 171
-Sending price tick 170
-Got [@ABC]
-Sending price tick 169
-Sending price tick 168
-Got [@ABC]
-Sending price tick 167
-Sending price tick 166
-Got [@ABC]
-Sending price tick 165
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Sending price tick 164
-Got [@ABC]
-Sending price tick 163
-Sending price tick 162
-Got [@ABC]
-Sending price tick 161
-Got [@ABC]
-Sending price tick 160
-Got [@ABC]
-Sending price tick 159
-Sending price tick 158
-Got [@ABC]
-Sending price tick 157
-Sending price tick 156
-Got [@ABC]
-Sending price tick 155
-Got [@ABC]
-Sending price tick 154
-Got [@ABC]
-Sending price tick 153
-Got [@ABC]
-Sending price tick 152
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Got [@ABC]
-Sending price tick 151
-Sending price tick 150
-Got [@ABC]
-Got [@ABC]
Index: udp_ip_stack/tags/v1.1/sw/test_results/UDPTestStream_wireshark.pcap
===================================================================
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Index: udp_ip_stack/tags/v1.1/sw/test_results/UDPTestStream_wireshark.pcap
===================================================================
--- udp_ip_stack/tags/v1.1/sw/test_results/UDPTestStream_wireshark.pcap (revision 5)
+++ udp_ip_stack/tags/v1.1/sw/test_results/UDPTestStream_wireshark.pcap (nonexistent)
udp_ip_stack/tags/v1.1/sw/test_results/UDPTestStream_wireshark.pcap
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Index: udp_ip_stack/tags/v1.1/bench/vhdl/IPv4_RX_tb.vhd
===================================================================
--- udp_ip_stack/tags/v1.1/bench/vhdl/IPv4_RX_tb.vhd (revision 5)
+++ udp_ip_stack/tags/v1.1/bench/vhdl/IPv4_RX_tb.vhd (nonexistent)
@@ -1,301 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:32:02 06/03/2011
--- Design Name:
--- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/IPv4_RX_tb.vhd
--- Project Name: ip1
--- Target Device:
--- Tool versions:
--- Description:
---
--- VHDL Test Bench Created by ISE for module: IPv4_RX
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes:
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test. Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation
--- simulation model.
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use work.axi.all;
-use work.ipv4_types.all;
-use work.arp_types.all;
-
-
-ENTITY IPv4_RX_tb IS
-END IPv4_RX_tb;
-
-ARCHITECTURE behavior OF IPv4_RX_tb IS
-
- -- Component Declaration for the Unit Under Test (UUT)
-
- COMPONENT IPv4_RX
- PORT(
- -- IP Layer signals
- ip_rx : out ipv4_rx_type;
- ip_rx_start : out std_logic; -- indicates receipt of ip frame.
- -- system signals
- clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
- reset : in STD_LOGIC;
- our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
- -- MAC layer RX signals
- mac_data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
- mac_data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock
- mac_data_in_last : in STD_LOGIC -- indicates last data in frame
- );
- END COMPONENT;
-
-
- --Inputs
- signal clk : std_logic := '0';
- signal reset : std_logic := '0';
- signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
- signal mac_data_in : std_logic_vector(7 downto 0) := (others => '0');
- signal mac_data_in_valid : std_logic := '0';
- signal mac_data_in_last : std_logic := '0';
-
- --Outputs
- signal ip_rx_start : std_logic;
- signal ip_rx : ipv4_rx_type;
-
- -- Clock period definitions
- constant clk_period : time := 8 ns;
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: IPv4_RX PORT MAP (
- ip_rx => ip_rx,
- ip_rx_start => ip_rx_start,
- clk => clk,
- reset => reset,
- our_ip_address => our_ip_address,
- mac_data_in => mac_data_in,
- mac_data_in_valid => mac_data_in_valid,
- mac_data_in_last => mac_data_in_last
- );
-
- -- Clock process definitions
- clk_process :process
- begin
- clk <= '0';
- wait for clk_period/2;
- clk <= '1';
- wait for clk_period/2;
- end process;
-
-
- -- Stimulus process
- stim_proc: process
- begin
- -- hold reset state for 100 ns.
- wait for 100 ns;
-
- our_ip_address <= x"c0a80509"; -- 192.168.5.9
- mac_data_in_valid <= '0';
- mac_data_in_last <= '0';
-
- reset <= '1';
- wait for clk_period*10;
- reset <= '0';
- wait for clk_period*5;
-
- -- check reset conditions
- assert ip_rx_start = '0' report "ip_rx_start not initialised correctly on reset";
- assert ip_rx.hdr.is_valid = '0' report "ip_rx.hdr.is_valid not initialised correctly on reset";
- assert ip_rx.hdr.protocol = x"00" report "ip_rx.hdr.protocol not initialised correctly on reset";
- assert ip_rx.hdr.data_length = x"0000" report "ip_rx.hdr.data_length not initialised correctly on reset";
- assert ip_rx.hdr.src_ip_addr = x"00000000" report "ip_rx.hdr.src_ip_addr not initialised correctly on reset";
- assert ip_rx.hdr.num_frame_errors = x"00" report "ip_rx.hdr.num_frame_errors not initialised correctly on reset";
- assert ip_rx.data.data_in = x"00" report "ip_rx.data.data_in not initialised correctly on reset";
- assert ip_rx.data.data_in_valid = '0' report "ip_rx.data.data_in_valid not initialised correctly on reset";
- assert ip_rx.data.data_in_last = '0' report "ip_rx.data.data_in_last not initialised correctly on reset";
-
- -- insert stimulus here
-
- ------------
- -- TEST 1 -- basic functional rx test with received ip pkt
- ------------
-
- report "T1: Send an eth frame with IP pkt dst ip_address c0a80509, dst mac 002320212223";
-
- mac_data_in_valid <= '1';
- -- dst MAC (bc)
- mac_data_in <= x"00"; wait for clk_period;
- mac_data_in <= x"23"; wait for clk_period;
- mac_data_in <= x"20"; wait for clk_period;
- mac_data_in <= x"21"; wait for clk_period;
- mac_data_in <= x"22"; wait for clk_period;
- mac_data_in <= x"23"; wait for clk_period;
- -- src MAC
- mac_data_in <= x"00"; wait for clk_period;
- mac_data_in <= x"23"; wait for clk_period;
- mac_data_in <= x"18"; wait for clk_period;
- mac_data_in <= x"29"; wait for clk_period;
- mac_data_in <= x"26"; wait for clk_period;
- mac_data_in <= x"7c"; wait for clk_period;
- -- type
- mac_data_in <= x"08"; wait for clk_period; -- IP pkt
- mac_data_in <= x"00"; wait for clk_period;
- -- ver & HL / service type
- mac_data_in <= x"45"; wait for clk_period;
- mac_data_in <= x"00"; wait for clk_period;
- -- total len
- mac_data_in <= x"00"; wait for clk_period;
- mac_data_in <= x"18"; wait for clk_period;
- -- ID
- mac_data_in <= x"00"; wait for clk_period;
- mac_data_in <= x"00"; wait for clk_period;
- -- flags & frag
- mac_data_in <= x"00"; wait for clk_period;
- mac_data_in <= x"00"; wait for clk_period;
- -- TTL
- mac_data_in <= x"00"; wait for clk_period;
- -- Protocol
- mac_data_in <= x"11"; wait for clk_period;
- -- Header CKS
- mac_data_in <= x"00"; wait for clk_period;
- mac_data_in <= x"00"; wait for clk_period;
- -- SRC IP
- mac_data_in <= x"c0"; wait for clk_period;
- mac_data_in <= x"a8"; wait for clk_period;
- mac_data_in <= x"05"; wait for clk_period;
- mac_data_in <= x"01"; wait for clk_period;
- -- DST IP
- mac_data_in <= x"c0"; wait for clk_period;
- mac_data_in <= x"a8"; wait for clk_period;
- mac_data_in <= x"05"; wait for clk_period;
- mac_data_in <= x"09"; wait for clk_period;
-
- -- user data
- mac_data_in <= x"24"; wait for clk_period;
-
- assert ip_rx.hdr.is_valid = '1' report "T1: ip_rx.hdr.is_valid not set";
- assert ip_rx.hdr.protocol = x"11" report "T1: ip_rx.hdr.protocol not set correctly";
- assert ip_rx.hdr.data_length = x"0004" report "T1: ip_rx.hdr.data_length not set correctly";
- assert ip_rx.hdr.src_ip_addr = x"c0a80501" report "T1: ip_rx.hdr.src_ip_addr not set correctly";
- assert ip_rx.hdr.num_frame_errors = x"00" report "T1: ip_rx.hdr.num_frame_errors not set correctly";
- assert ip_rx.hdr.last_error_code = x"0" report "T1: ip_rx.hdr.last_error_code not set correctly";
- assert ip_rx_start = '1' report "T1: ip_rx_start not set";
- assert ip_rx.data.data_in_valid = '1' report "T1: ip_rx.data.data_in_valid not set";
-
- mac_data_in <= x"25"; wait for clk_period;
- mac_data_in <= x"26"; wait for clk_period;
- mac_data_in <= x"27"; mac_data_in_last <= '1';wait for clk_period;
-
- assert ip_rx.data.data_in_last = '1' report "T1: ip_rx.data.data_in_last not set";
-
- mac_data_in <= x"00";
- mac_data_in_last <= '0';
- mac_data_in_valid <= '0';
- wait for clk_period;
-
- assert ip_rx.data.data_in_valid = '0' report "T1: ip_rx.data.data_in_valid not cleared";
- assert ip_rx.data.data_in_last = '0' report "T1: ip_rx.data.data_in_last not cleared";
- assert ip_rx.hdr.num_frame_errors = x"00" report "T1: ip_rx.hdr.num_frame_errors non zero at end of test";
- assert ip_rx.hdr.last_error_code = x"0" report "T1: ip_rx.hdr.last_error_code indicates error at end of test";
- assert ip_rx_start = '0' report "T1: ip_rx_start not cleared";
-
- ------------
- -- TEST 2 -- basic functional rx test with received ip pkt that is not for us
- ------------
-
- report "T2: Send an eth frame with IP pkt dst ip_address c0a80507, dst mac 002320212223";
-
- mac_data_in_valid <= '1';
- -- dst MAC (bc)
- mac_data_in <= x"00"; wait for clk_period;
- mac_data_in <= x"23"; wait for clk_period;
- mac_data_in <= x"20"; wait for clk_period;
- mac_data_in <= x"21"; wait for clk_period;
- mac_data_in <= x"22"; wait for clk_period;
- mac_data_in <= x"23"; wait for clk_period;
-
- assert ip_rx.hdr.is_valid = '0' report "T2: ip_rx.hdr.is_valid remains set";
-
- -- src MAC
- mac_data_in <= x"00"; wait for clk_period;
- mac_data_in <= x"23"; wait for clk_period;
- mac_data_in <= x"18"; wait for clk_period;
- mac_data_in <= x"29"; wait for clk_period;
- mac_data_in <= x"26"; wait for clk_period;
- mac_data_in <= x"7c"; wait for clk_period;
- -- type
- mac_data_in <= x"08"; wait for clk_period; -- IP pkt
- mac_data_in <= x"00"; wait for clk_period;
- -- ver & HL / service type
- mac_data_in <= x"45"; wait for clk_period;
- mac_data_in <= x"00"; wait for clk_period;
- -- total len
- mac_data_in <= x"00"; wait for clk_period;
- mac_data_in <= x"18"; wait for clk_period;
- -- ID
- mac_data_in <= x"00"; wait for clk_period;
- mac_data_in <= x"00"; wait for clk_period;
- -- flags & frag
- mac_data_in <= x"00"; wait for clk_period;
- mac_data_in <= x"00"; wait for clk_period;
- -- TTL
- mac_data_in <= x"00"; wait for clk_period;
- -- Protocol
- mac_data_in <= x"11"; wait for clk_period;
- -- Header CKS
- mac_data_in <= x"00"; wait for clk_period;
- mac_data_in <= x"00"; wait for clk_period;
- -- SRC IP
- mac_data_in <= x"c0"; wait for clk_period;
- mac_data_in <= x"a8"; wait for clk_period;
- mac_data_in <= x"05"; wait for clk_period;
- mac_data_in <= x"02"; wait for clk_period;
- -- DST IP
- mac_data_in <= x"c0"; wait for clk_period;
- mac_data_in <= x"a8"; wait for clk_period;
- mac_data_in <= x"05"; wait for clk_period;
- mac_data_in <= x"07"; wait for clk_period;
-
- -- user data
- mac_data_in <= x"24"; wait for clk_period;
-
- assert ip_rx.hdr.is_valid = '1' report "T2: ip_rx.hdr.is_valid not set";
- assert ip_rx.hdr.protocol = x"11" report "T2: ip_rx.hdr.protocol not set correctly";
- assert ip_rx.hdr.data_length = x"0004" report "T2: ip_rx.hdr.data_length not set correctly";
- assert ip_rx.hdr.src_ip_addr = x"c0a80502" report "T2: ip_rx.hdr.src_ip_addr not set correctly";
- assert ip_rx.hdr.num_frame_errors = x"00" report "T2: ip_rx.hdr.num_frame_errors not set correctly";
- assert ip_rx.hdr.last_error_code = x"0" report "T2: ip_rx.hdr.last_error_code not set correctly";
- assert ip_rx_start = '0' report "T2: ip_rx_start set when pkt not for us";
- assert ip_rx.data.data_in_valid = '0' report "T2: ip_rx.data.data_in_valid set when pkt not for us";
-
- mac_data_in <= x"25"; wait for clk_period;
- mac_data_in <= x"26"; wait for clk_period;
- mac_data_in <= x"27"; mac_data_in_last <= '1';wait for clk_period;
-
- assert ip_rx.data.data_in_last = '0' report "T2: ip_rx.data.data_in_last set";
-
- mac_data_in <= x"00";
- mac_data_in_last <= '0';
- mac_data_in_valid <= '0';
- wait for clk_period;
-
- assert ip_rx.data.data_in_valid = '0' report "T2: ip_rx.data.data_in_valid not cleared";
- assert ip_rx.data.data_in_last = '0' report "T2: ip_rx.data.data_in_last not cleared";
- assert ip_rx.hdr.num_frame_errors = x"00" report "T2: ip_rx.hdr.num_frame_errors non zero at end of test";
- assert ip_rx.hdr.last_error_code = x"0" report "T2: ip_rx.hdr.last_error_code indicates error at end of test";
- assert ip_rx_start = '0' report "T2: ip_rx_start not cleared";
-
- report "--- end of tests ---";
-
- wait;
- end process;
-
-END;
Index: udp_ip_stack/tags/v1.1/bench/vhdl/UDP_complete_nomac_tb.vhd
===================================================================
--- udp_ip_stack/tags/v1.1/bench/vhdl/UDP_complete_nomac_tb.vhd (revision 5)
+++ udp_ip_stack/tags/v1.1/bench/vhdl/UDP_complete_nomac_tb.vhd (nonexistent)
@@ -1,656 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 09:57:01 06/13/2011
--- Design Name:
--- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/udp1/UDP_complete_nomac_tb.vhd
--- Project Name: udp1
--- Target Device:
--- Tool versions:
--- Description:
---
--- VHDL Test Bench Created by ISE for module: UDP_Complete_nomac
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes:
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test. Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation
--- simulation model.
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use work.axi.all;
-use work.ipv4_types.all;
-use work.arp_types.all;
-
-ENTITY UDP_complete_nomac_tb IS
-END UDP_complete_nomac_tb;
-
-ARCHITECTURE behavior OF UDP_complete_nomac_tb IS
-
- -- Component Declaration for the Unit Under Test (UUT)
-
- COMPONENT UDP_Complete_nomac
- PORT(
- -- UDP TX signals
- udp_tx_start : in std_logic; -- indicates req to tx UDP
- udp_txi : in udp_tx_type; -- UDP tx cxns
- udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
- udp_tx_data_out_ready: out std_logic; -- indicates udp_tx is ready to take data
- -- UDP RX signals
- udp_rx_start : out std_logic; -- indicates receipt of udp header
- udp_rxo : out udp_rx_type;
- -- IP RX signals
- ip_rx_hdr : out ipv4_rx_header_type;
- -- system signals
- rx_clk : in STD_LOGIC;
- tx_clk : in STD_LOGIC;
- reset : in STD_LOGIC;
- our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
- our_mac_address : in std_logic_vector (47 downto 0);
- -- status signals
- arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
- ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
- -- MAC Transmitter
- mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
- mac_tx_tvalid : out std_logic; -- tdata is valid
- mac_tx_tready : in std_logic; -- mac is ready to accept data
- mac_tx_tfirst : out std_logic; -- indicates first byte of frame
- mac_tx_tlast : out std_logic; -- indicates last byte of frame
- -- MAC Receiver
- mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
- mac_rx_tvalid : in std_logic; -- indicates tdata is valid
- mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
- mac_rx_tlast : in std_logic -- indicates last byte of the trame
- );
- END COMPONENT;
-
-
-
- type state_type is (IDLE, DATA_OUT);
- type count_mode_type is (RST, INCR, HOLD);
- type set_clr_type is (SET, CLR, HOLD);
-
-
- --Inputs
- signal udp_tx_start_int : std_logic := '0';
- signal udp_tx_int : udp_tx_type;
- signal clk_int : std_logic := '0';
- signal reset : std_logic := '0';
- signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
- signal our_mac_address : std_logic_vector(47 downto 0) := (others => '0');
- signal mac_tx_tready : std_logic := '0';
- signal mac_rx_tdata : std_logic_vector(7 downto 0) := (others => '0');
- signal mac_rx_tvalid : std_logic := '0';
- signal mac_rx_tlast : std_logic := '0';
-
- --Outputs
- signal udp_rx_start_int : std_logic;
- signal udp_rx_int : udp_rx_type;
- signal ip_rx_hdr : ipv4_rx_header_type;
- signal udp_tx_result : std_logic_vector (1 downto 0);
- signal udp_tx_data_out_ready_int: std_logic;
-
- signal arp_pkt_count : std_logic_vector(7 downto 0);
- signal ip_pkt_count : std_logic_vector(7 downto 0);
- signal mac_tx_tdata : std_logic_vector(7 downto 0);
- signal mac_tx_tvalid : std_logic;
- signal mac_tx_tfirst : std_logic;
- signal mac_tx_tlast : std_logic;
- signal mac_rx_tready : std_logic;
-
- signal pbtx_led : std_logic;
- signal pbtx : std_logic := '0';
-
- -- state signals
- signal state : state_type;
- signal count : unsigned (7 downto 0);
- signal tx_hdr : udp_tx_header_type;
- signal tx_start_reg : std_logic;
- signal tx_started_reg : std_logic;
- signal tx_fin_reg : std_logic;
-
-
- -- control signals
- signal next_state : state_type;
- signal set_state : std_logic;
- signal set_count : count_mode_type;
- signal set_hdr : std_logic;
- signal set_tx_start : set_clr_type;
- signal tx_data : std_logic_vector (7 downto 0);
- signal set_last : std_logic;
- signal set_tx_started : set_clr_type;
- signal set_tx_fin : set_clr_type;
-
-
-
- -- Clock period definitions
- constant clk_period : time := 8 ns;
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: UDP_Complete_nomac PORT MAP (
- udp_tx_start => udp_tx_start_int,
- udp_txi => udp_tx_int,
- udp_tx_result => udp_tx_result,
- udp_tx_data_out_ready => udp_tx_data_out_ready_int,
- udp_rx_start => udp_rx_start_int,
- udp_rxo => udp_rx_int,
- ip_rx_hdr => ip_rx_hdr,
- rx_clk => clk_int,
- tx_clk => clk_int,
- reset => reset,
- our_ip_address => our_ip_address,
- our_mac_address => our_mac_address,
- arp_pkt_count => arp_pkt_count,
- ip_pkt_count => ip_pkt_count,
- mac_tx_tdata => mac_tx_tdata,
- mac_tx_tvalid => mac_tx_tvalid,
- mac_tx_tready => mac_tx_tready,
- mac_tx_tfirst => mac_tx_tfirst,
- mac_tx_tlast => mac_tx_tlast,
- mac_rx_tdata => mac_rx_tdata,
- mac_rx_tvalid => mac_rx_tvalid,
- mac_rx_tready => mac_rx_tready,
- mac_rx_tlast => mac_rx_tlast
- );
-
- -- Clock process definitions
- clk_process :process
- begin
- clk_int <= '0';
- wait for clk_period/2;
- clk_int <= '1';
- wait for clk_period/2;
- end process;
-
-
- -- Stimulus process
- stim_proc: process
- begin
- -- hold reset state for 100 ns.
- wait for 100 ns;
-
- our_ip_address <= x"c0a80509"; -- 192.168.5.9
- our_mac_address <= x"002320212223";
- mac_tx_tready <= '0';
-
- reset <= '1';
- wait for clk_period*10;
- reset <= '0';
- wait for clk_period*5;
-
- -- check reset conditions
- assert udp_tx_result = UDPTX_RESULT_NONE report "udp_tx_result not initialised correctly on reset";
- assert udp_tx_data_out_ready_int = '0' report "ip_udp_txitx.data.data_out_ready not initialised correctly on reset";
- assert mac_tx_tvalid = '0' report "mac_tx_tvalid not initialised correctly on reset";
- assert mac_tx_tlast = '0' report "mac_tx_tlast not initialised correctly on reset";
- assert arp_pkt_count = x"00" report "arp_pkt_count not initialised correctly on reset";
- assert ip_pkt_count = x"00" report "ip_pkt_count not initialised correctly on reset";
- assert udp_rx_start_int = '0' report "udp_rx_start not initialised correctly on reset";
- assert udp_rx_int.hdr.is_valid = '0' report "udp_rx_int.hdr.is_valid not initialised correctly on reset";
- assert udp_rx_int.hdr.data_length = x"0000" report "udp_rx_int.hdr.data_length not initialised correctly on reset";
- assert udp_rx_int.hdr.src_ip_addr = x"00000000" report "udp_rx_int.hdr.src_ip_addr not initialised correctly on reset";
- assert udp_rx_int.hdr.src_port = x"0000" report "udp_rx_int.hdr.src_port not initialised correctly on reset";
- assert udp_rx_int.hdr.dst_port = x"0000" report "udp_rx_int.hdr.dst_port not initialised correctly on reset";
- assert udp_rx_int.data.data_in = x"00" report "udp_rx_start.data.data_in not initialised correctly on reset";
- assert udp_rx_int.data.data_in_valid = '0' report "udp_rx_start.data.data_in_valid not initialised correctly on reset";
- assert udp_rx_int.data.data_in_last = '0' report "udp_rx_start.data.data_in_last not initialised correctly on reset";
- assert ip_rx_hdr.is_valid = '0' report "ip_rx_hdr.is_valid not initialised correctly on reset";
- assert ip_rx_hdr.protocol = x"00" report "ip_rx_hdr.protocol not initialised correctly on reset";
- assert ip_rx_hdr.data_length = x"0000" report "ip_rx_hdr.data_length not initialised correctly on reset";
- assert ip_rx_hdr.src_ip_addr = x"00000000" report "ip_rx_hdr.src_ip_addr not initialised correctly on reset";
- assert ip_rx_hdr.num_frame_errors = x"00" report "ip_rx_hdr.num_frame_errors not initialised correctly on reset";
-
-
- -- insert stimulus here
-
- ------------
- -- TEST 1 -- send ARP request
- ------------
-
- report "T1: Send an ARP request: who has 192.168.5.9? Tell 192.168.5.1";
-
- mac_tx_tready <= '1';
-
- mac_rx_tvalid <= '1';
- -- dst MAC (bc)
- mac_rx_tdata <= x"ff"; wait for clk_period;
- mac_rx_tdata <= x"ff"; wait for clk_period;
- mac_rx_tdata <= x"ff"; wait for clk_period;
- mac_rx_tdata <= x"ff"; wait for clk_period;
- mac_rx_tdata <= x"ff"; wait for clk_period;
- mac_rx_tdata <= x"ff"; wait for clk_period;
- -- src MAC
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"23"; wait for clk_period;
- mac_rx_tdata <= x"18"; wait for clk_period;
- mac_rx_tdata <= x"29"; wait for clk_period;
- mac_rx_tdata <= x"26"; wait for clk_period;
- mac_rx_tdata <= x"7c"; wait for clk_period;
- -- type
- mac_rx_tdata <= x"08"; wait for clk_period;
- mac_rx_tdata <= x"06"; wait for clk_period;
- -- HW type
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"01"; wait for clk_period;
- -- Protocol type
- mac_rx_tdata <= x"08"; wait for clk_period;
- mac_rx_tdata <= x"00"; wait for clk_period;
- -- HW size
- mac_rx_tdata <= x"06"; wait for clk_period;
- -- protocol size
- mac_rx_tdata <= x"04"; wait for clk_period;
- -- Opcode
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"01"; wait for clk_period;
- -- Sender MAC
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"23"; wait for clk_period;
- mac_rx_tdata <= x"18"; wait for clk_period;
- mac_rx_tdata <= x"29"; wait for clk_period;
- mac_rx_tdata <= x"26"; wait for clk_period;
- mac_rx_tdata <= x"7c"; wait for clk_period;
- -- Sender IP
- mac_rx_tdata <= x"c0"; wait for clk_period;
- mac_rx_tdata <= x"a8"; wait for clk_period;
- mac_rx_tdata <= x"05"; wait for clk_period;
- mac_rx_tdata <= x"01"; wait for clk_period;
- -- Target MAC
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"00"; wait for clk_period;
- -- Target IP
- mac_rx_tdata <= x"c0"; wait for clk_period;
- mac_rx_tdata <= x"a8"; wait for clk_period;
- mac_rx_tdata <= x"05"; wait for clk_period;
- mac_rx_tdata <= x"09"; wait for clk_period;
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tlast <= '1';
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tlast <= '0';
- mac_rx_tvalid <= '0';
-
- -- check we got the ARP pkt
- assert arp_pkt_count = x"01" report "T1: arp_pkt_count wrong value";
- assert ip_pkt_count = x"00" report "T1: ip_pkt_count wrong value";
- assert udp_tx_result = UDPTX_RESULT_NONE report "T1: udp_tx_result wrong value";
- assert udp_tx_data_out_ready_int = '0' report "T1: ip_udp_txitx.data.data_out_ready wrong value";
- assert udp_rx_start_int = '0' report "T1: udp_rx_start wrong value";
- assert udp_rx_int.hdr.is_valid = '0' report "T1: udp_rx_int.hdr.is_valid wrong value";
- assert ip_rx_hdr.is_valid = '0' report "T1: ip_rx_hdr.is_valid wrong value";
-
- -- check we tx a response
-
- wait for clk_period*25;
- assert mac_tx_tvalid = '1' report "T1: not transmitting a response";
- wait for clk_period*25;
- assert mac_tx_tvalid = '0' report "T1: tx held on for too long";
-
- ------------
- -- TEST 2 -- send UDP pkt (same as sample from Java program
- ------------
-
- report "T2: Send UDP IP pkt dst ip_address c0a80509, from port f49a to port 2694";
-
- mac_rx_tvalid <= '1';
- -- dst MAC (bc)
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"23"; wait for clk_period;
- mac_rx_tdata <= x"20"; wait for clk_period;
- mac_rx_tdata <= x"21"; wait for clk_period;
- mac_rx_tdata <= x"22"; wait for clk_period;
- mac_rx_tdata <= x"23"; wait for clk_period;
- -- src MAC
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"23"; wait for clk_period;
- mac_rx_tdata <= x"18"; wait for clk_period;
- mac_rx_tdata <= x"29"; wait for clk_period;
- mac_rx_tdata <= x"26"; wait for clk_period;
- mac_rx_tdata <= x"7c"; wait for clk_period;
- -- type
- mac_rx_tdata <= x"08"; wait for clk_period; -- IP pkt
- mac_rx_tdata <= x"00"; wait for clk_period;
- -- ver & HL / service type
- mac_rx_tdata <= x"45"; wait for clk_period;
- mac_rx_tdata <= x"00"; wait for clk_period;
- -- total len
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"21"; wait for clk_period;
- -- ID
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"7a"; wait for clk_period;
- -- flags & frag
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"00"; wait for clk_period;
- -- TTL
- mac_rx_tdata <= x"80"; wait for clk_period;
- -- Protocol
- mac_rx_tdata <= x"11"; wait for clk_period;
- -- Header CKS
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"00"; wait for clk_period;
- -- SRC IP
- mac_rx_tdata <= x"c0"; wait for clk_period;
- mac_rx_tdata <= x"a8"; wait for clk_period;
- mac_rx_tdata <= x"05"; wait for clk_period;
- mac_rx_tdata <= x"01"; wait for clk_period;
- -- DST IP
- mac_rx_tdata <= x"c0"; wait for clk_period;
- mac_rx_tdata <= x"a8"; wait for clk_period;
- mac_rx_tdata <= x"05"; wait for clk_period;
- mac_rx_tdata <= x"09"; wait for clk_period;
- -- SRC port
- mac_rx_tdata <= x"f4"; wait for clk_period;
- mac_rx_tdata <= x"9a"; wait for clk_period;
- -- DST port
- mac_rx_tdata <= x"26"; wait for clk_period;
- mac_rx_tdata <= x"94"; wait for clk_period;
- -- length
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"0d"; wait for clk_period;
- -- cks
- mac_rx_tdata <= x"8b"; wait for clk_period;
- mac_rx_tdata <= x"79"; wait for clk_period;
- -- user data
- mac_rx_tdata <= x"68"; wait for clk_period;
-
- -- since we are up to the user data stage, the header should be valid and the data_in_valid should be set
- assert udp_rx_int.hdr.is_valid = '1' report "T2: udp_rx_int.hdr.is_valid not set";
- assert udp_rx_int.hdr.data_length = x"0005" report "T2: udp_rx_int.hdr.data_length not set correctly";
- assert udp_rx_int.hdr.src_ip_addr = x"c0a80501" report "T2: udp_rx_int.hdr.src_ip_addr not set correctly";
- assert udp_rx_int.hdr.src_port = x"f49a" report "T2: udp_rx_int.hdr.src_port not set correctly";
- assert udp_rx_int.hdr.dst_port = x"2694" report "T2: udp_rx_int.hdr.dst_port not set correctly";
-
- assert udp_rx_start_int = '1' report "T2: udp_rx_start not set";
- assert udp_rx_int.data.data_in_valid = '1' report "T2: udp_rx_int.data.data_in_valid not set";
-
- assert ip_rx_hdr.is_valid = '1' report "T2: ip_rx_hdr.is_valid not set";
- assert ip_rx_hdr.protocol = x"11" report "T2: ip_rx_hdr.protocol not set correctly";
- assert ip_rx_hdr.src_ip_addr = x"c0a80501" report "T2: ip_rx.hdr.src_ip_addr not set correctly";
- assert ip_rx_hdr.num_frame_errors = x"00" report "T2: ip_rx.hdr.num_frame_errors not set correctly";
- assert ip_rx_hdr.last_error_code = x"0" report "T2: ip_rx.hdr.last_error_code not set correctly";
-
- -- put the rest of the user data
- mac_rx_tdata <= x"65"; wait for clk_period;
- mac_rx_tdata <= x"6c"; wait for clk_period;
- mac_rx_tdata <= x"6c"; wait for clk_period;
- mac_rx_tdata <= x"6f"; mac_rx_tlast <= '1'; wait for clk_period;
-
- assert udp_rx_int.data.data_in_last = '1' report "T2: udp_rx_int.data.data_in_last not set";
-
- mac_rx_tdata <= x"00";
- mac_rx_tlast <= '0';
- mac_rx_tvalid <= '0';
- wait for clk_period;
-
- assert udp_rx_int.data.data_in_valid = '0' report "T2: udp_rx_int.data.data_in_valid not cleared";
- assert udp_rx_int.data.data_in_last = '0' report "T2: udp_rx_int.data.data_in_last not cleared";
- assert udp_rx_start_int = '0' report "T2: udp_rx_start not cleared";
- assert ip_rx_hdr.num_frame_errors = x"00" report "T2: ip_rx_hdr.num_frame_errors non zero at end of test";
- assert ip_rx_hdr.last_error_code = x"0" report "T2: ip_rx_hdr.last_error_code indicates error at end of test";
- assert ip_pkt_count = x"01" report "T2: ip pkt cnt incorrect";
-
- wait for clk_period*20;
-
- ------------
- -- TEST 3 -- send UDP pkt again (same as sample from Java program
- ------------
-
- report "T3: Send UDP IP pkt dst ip_address c0a80509, from port f49a to port 2694";
-
- mac_rx_tvalid <= '1';
- -- dst MAC (bc)
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"23"; wait for clk_period;
- mac_rx_tdata <= x"20"; wait for clk_period;
- mac_rx_tdata <= x"21"; wait for clk_period;
- mac_rx_tdata <= x"22"; wait for clk_period;
- mac_rx_tdata <= x"23"; wait for clk_period;
- -- src MAC
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"23"; wait for clk_period;
- mac_rx_tdata <= x"18"; wait for clk_period;
- mac_rx_tdata <= x"29"; wait for clk_period;
- mac_rx_tdata <= x"26"; wait for clk_period;
- mac_rx_tdata <= x"7c"; wait for clk_period;
- -- type
- mac_rx_tdata <= x"08"; wait for clk_period; -- IP pkt
- mac_rx_tdata <= x"00"; wait for clk_period;
- -- ver & HL / service type
- mac_rx_tdata <= x"45"; wait for clk_period;
- mac_rx_tdata <= x"00"; wait for clk_period;
- -- total len
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"21"; wait for clk_period;
- -- ID
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"7a"; wait for clk_period;
- -- flags & frag
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"00"; wait for clk_period;
- -- TTL
- mac_rx_tdata <= x"80"; wait for clk_period;
- -- Protocol
- mac_rx_tdata <= x"11"; wait for clk_period;
- -- Header CKS
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"00"; wait for clk_period;
- -- SRC IP
- mac_rx_tdata <= x"c0"; wait for clk_period;
- mac_rx_tdata <= x"a8"; wait for clk_period;
- mac_rx_tdata <= x"05"; wait for clk_period;
- mac_rx_tdata <= x"01"; wait for clk_period;
- -- DST IP
- mac_rx_tdata <= x"c0"; wait for clk_period;
- mac_rx_tdata <= x"a8"; wait for clk_period;
- mac_rx_tdata <= x"05"; wait for clk_period;
- mac_rx_tdata <= x"09"; wait for clk_period;
- -- SRC port
- mac_rx_tdata <= x"f4"; wait for clk_period;
- mac_rx_tdata <= x"9a"; wait for clk_period;
- -- DST port
- mac_rx_tdata <= x"26"; wait for clk_period;
- mac_rx_tdata <= x"94"; wait for clk_period;
- -- length
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"0d"; wait for clk_period;
- -- cks
- mac_rx_tdata <= x"8b"; wait for clk_period;
- mac_rx_tdata <= x"79"; wait for clk_period;
- -- user data
- mac_rx_tdata <= x"68"; wait for clk_period;
-
- -- since we are up to the user data stage, the header should be valid and the data_in_valid should be set
- assert udp_rx_int.hdr.is_valid = '1' report "T3: udp_rx_int.hdr.is_valid not set";
- assert udp_rx_int.hdr.data_length = x"0005" report "T3: udp_rx_int.hdr.data_length not set correctly";
- assert udp_rx_int.hdr.src_ip_addr = x"c0a80501" report "T3: udp_rx_int.hdr.src_ip_addr not set correctly";
- assert udp_rx_int.hdr.src_port = x"f49a" report "T3: udp_rx_int.hdr.src_port not set correctly";
- assert udp_rx_int.hdr.dst_port = x"2694" report "T3: udp_rx_int.hdr.dst_port not set correctly";
-
- assert udp_rx_start_int = '1' report "T3: udp_rx_start not set";
- assert udp_rx_int.data.data_in_valid = '1' report "T3: udp_rx_int.data.data_in_valid not set";
-
- assert ip_rx_hdr.is_valid = '1' report "T3: ip_rx_hdr.is_valid not set";
- assert ip_rx_hdr.protocol = x"11" report "T3: ip_rx_hdr.protocol not set correctly";
- assert ip_rx_hdr.src_ip_addr = x"c0a80501" report "T3: ip_rx.hdr.src_ip_addr not set correctly";
- assert ip_rx_hdr.num_frame_errors = x"00" report "T3: ip_rx.hdr.num_frame_errors not set correctly";
- assert ip_rx_hdr.last_error_code = x"0" report "T3: ip_rx.hdr.last_error_code not set correctly";
-
- -- put the rest of the user data
- mac_rx_tdata <= x"65"; wait for clk_period;
- mac_rx_tdata <= x"6c"; wait for clk_period;
- mac_rx_tdata <= x"6c"; wait for clk_period;
- mac_rx_tdata <= x"6f"; mac_rx_tlast <= '1'; wait for clk_period;
-
- assert udp_rx_int.data.data_in_last = '1' report "T3: udp_rx_int.data.data_in_last not set";
-
- mac_rx_tdata <= x"00";
- mac_rx_tlast <= '0';
- mac_rx_tvalid <= '0';
- wait for clk_period;
-
- assert udp_rx_int.data.data_in_valid = '0' report "T3: udp_rx_int.data.data_in_valid not cleared";
- assert udp_rx_int.data.data_in_last = '0' report "T3: udp_rx_int.data.data_in_last not cleared";
- assert udp_rx_start_int = '0' report "T3: udp_rx_start not cleared";
- assert ip_rx_hdr.num_frame_errors = x"00" report "T3: ip_rx_hdr.num_frame_errors non zero at end of test";
- assert ip_rx_hdr.last_error_code = x"0" report "T3: ip_rx_hdr.last_error_code indicates error at end of test";
- assert ip_pkt_count = x"02" report "T3: ip pkt cnt incorrect";
-
- report "--- end of tests ---";
- wait;
- end process;
-
- -- AUTO TX process - on receipt of any UDP pkt, send a response
-
- -- TX response process - COMB
- tx_proc_combinatorial: process(
- -- inputs
- udp_rx_start_int, udp_tx_data_out_ready_int, udp_tx_int.data.data_out_valid, PBTX,
- -- state
- state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg,
- -- controls
- next_state, set_state, set_count, set_hdr, set_tx_start, set_last,
- set_tx_started, set_tx_fin
- )
- begin
- -- set output_followers
- udp_tx_int.hdr <= tx_hdr;
- udp_tx_int.data.data_out_last <= set_last;
- udp_tx_start_int <= tx_start_reg;
-
- -- set control signal defaults
- next_state <= IDLE;
- set_state <= '0';
- set_count <= HOLD;
- set_hdr <= '0';
- set_tx_start <= HOLD;
- set_last <= '0';
- set_tx_started <= HOLD;
- set_tx_fin <= HOLD;
-
- -- FSM
- case state is
-
- when IDLE =>
- udp_tx_int.data.data_out <= (others => '0');
- udp_tx_int.data.data_out_valid <= '0';
- if udp_rx_start_int = '1' or PBTX = '1' then
- set_tx_started <= SET;
- set_hdr <= '1';
- set_tx_start <= SET;
- set_tx_fin <= CLR;
- set_count <= RST;
- next_state <= DATA_OUT;
- set_state <= '1';
- end if;
-
- when DATA_OUT =>
- udp_tx_int.data.data_out <= std_logic_vector(count) or x"40";
- udp_tx_int.data.data_out_valid <= udp_tx_data_out_ready_int;
- if udp_tx_data_out_ready_int = '1' then
- set_tx_start <= CLR;
- if unsigned(count) = x"03" then
- set_last <= '1';
- set_tx_fin <= SET;
- set_tx_started <= CLR;
- next_state <= IDLE;
- set_state <= '1';
- else
- set_count <= INCR;
- end if;
- end if;
-
- end case;
- end process;
-
-
-
- -- TX response process - SEQ
- tx_proc_sequential: process(clk_int)
- begin
- if rising_edge(clk_int) then
- if reset = '1' then
- -- reset state variables
- state <= IDLE;
- count <= x"00";
- tx_start_reg <= '0';
- tx_hdr.dst_ip_addr <= (others => '0');
- tx_hdr.dst_port <= (others => '0');
- tx_hdr.src_port <= (others => '0');
- tx_hdr.data_length <= (others => '0');
- tx_hdr.checksum <= (others => '0');
- tx_started_reg <= '0';
- tx_fin_reg <= '0';
- PBTX_LED <= '0';
- else
- PBTX_LED <= PBTX;
-
- -- Next rx_state processing
- if set_state = '1' then
- state <= next_state;
- else
- state <= state;
- end if;
-
- -- count processing
- case set_count is
- when RST => count <= x"00";
- when INCR => count <= count + 1;
- when HOLD => count <= count;
- end case;
-
- -- set tx hdr
- if set_hdr = '1' then
- tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr;
- tx_hdr.dst_port <= udp_rx_int.hdr.src_port;
- tx_hdr.src_port <= udp_rx_int.hdr.dst_port;
- tx_hdr.data_length <= x"0004";
- tx_hdr.checksum <= x"0000";
- else
- tx_hdr <= tx_hdr;
- end if;
-
- -- set tx start signal
- case set_tx_start is
- when SET => tx_start_reg <= '1';
- when CLR => tx_start_reg <= '0';
- when HOLD => tx_start_reg <= tx_start_reg;
- end case;
-
- -- set tx started signal
- case set_tx_started is
- when SET => tx_started_reg <= '1';
- when CLR => tx_started_reg <= '0';
- when HOLD => tx_started_reg <= tx_started_reg;
- end case;
-
- -- set tx finished signal
- case set_tx_fin is
- when SET => tx_fin_reg <= '1';
- when CLR => tx_fin_reg <= '0';
- when HOLD => tx_fin_reg <= tx_fin_reg;
- end case;
-
-
- end if;
- end if;
-
- end process;
-
-END;
Index: udp_ip_stack/tags/v1.1/bench/vhdl/IPv4_TX_tb.vhd
===================================================================
--- udp_ip_stack/tags/v1.1/bench/vhdl/IPv4_TX_tb.vhd (revision 5)
+++ udp_ip_stack/tags/v1.1/bench/vhdl/IPv4_TX_tb.vhd (nonexistent)
@@ -1,309 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 09:35:58 06/03/2011
--- Design Name:
--- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/IPv4_TX_tb.vhd
--- Project Name: ip1
--- Target Device:
--- Tool versions:
--- Description:
---
--- VHDL Test Bench Created by ISE for module: IPv4_TX
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes:
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test. Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation
--- simulation model.
---------------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use work.axi.all;
-use work.ipv4_types.all;
-use work.arp_types.all;
-
-
-ENTITY IPv4_TX_tb IS
-END IPv4_TX_tb;
-
-ARCHITECTURE behavior OF IPv4_TX_tb IS
-
- -- Component Declaration for the Unit Under Test (UUT)
-
- COMPONENT IPv4_TX
- PORT(
- -- IP Layer signals
- ip_tx_start : in std_logic;
- ip_tx : in ipv4_tx_type; -- IP tx cxns
- ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
- ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
-
- -- system signals
- clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
- reset : in STD_LOGIC;
- our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
- our_mac_address : in std_logic_vector (47 downto 0);
- -- ARP lookup signals
- arp_req_req : out arp_req_req_type;
- arp_req_rslt : in arp_req_rslt_type;
- -- MAC layer TX signals
- mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
- mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
- mac_data_out_ready : in std_logic; -- indicates system ready to consume data
- mac_data_out_valid : out std_logic; -- indicates data out is valid
- mac_data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
- mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
- mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
- );
- END COMPONENT;
-
-
- --Inputs
- signal ip_tx_start : std_logic := '0';
- signal ip_tx : ipv4_tx_type;
- signal clk : std_logic := '0';
- signal reset : std_logic := '0';
- signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
- signal our_mac_address : std_logic_vector(47 downto 0) := (others => '0');
- signal mac_tx_granted : std_logic := '0';
- signal mac_data_out_ready : std_logic := '0';
- signal arp_req_rslt : arp_req_rslt_type;
-
- --Outputs
- signal ip_tx_result : std_logic_vector (1 downto 0); -- tx status (changes during transmission)
- signal ip_tx_data_out_ready : std_logic; -- indicates IP TX is ready to take data
- signal mac_tx_req : std_logic;
- signal mac_data_out_valid : std_logic;
- signal mac_data_out_last : std_logic;
- signal mac_data_out_first : std_logic;
- signal mac_data_out : std_logic_vector(7 downto 0);
- signal arp_req_req : arp_req_req_type;
-
- -- Clock period definitions
- constant clk_period : time := 8 ns;
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: IPv4_TX PORT MAP (
- ip_tx_start => ip_tx_start,
- ip_tx => ip_tx,
- ip_tx_result => ip_tx_result,
- ip_tx_data_out_ready => ip_tx_data_out_ready,
- clk => clk,
- reset => reset,
- our_ip_address => our_ip_address,
- our_mac_address => our_mac_address,
- arp_req_req => arp_req_req,
- arp_req_rslt => arp_req_rslt,
- mac_tx_req => mac_tx_req,
- mac_tx_granted => mac_tx_granted,
- mac_data_out_ready => mac_data_out_ready,
- mac_data_out_valid => mac_data_out_valid,
- mac_data_out_first => mac_data_out_first,
- mac_data_out_last => mac_data_out_last,
- mac_data_out => mac_data_out
- );
-
- -- Clock process definitions
- clk_process :process
- begin
- clk <= '0';
- wait for clk_period/2;
- clk <= '1';
- wait for clk_period/2;
- end process;
-
-
- -- Stimulus process
- stim_proc: process
- begin
- our_ip_address <= x"c0a80509"; -- 192.168.5.9
- our_mac_address <= x"002320212223";
- ip_tx_start <= '0';
- mac_tx_granted <= '0';
- mac_data_out_ready <= '0';
- ip_tx.data.data_out_valid <= '0';
- ip_tx.data.data_out_last <= '0';
- arp_req_rslt.got_mac <= '0';
- arp_req_rslt.got_err <= '0';
- arp_req_rslt.mac <= (others => '0');
-
- reset <= '1';
- wait for clk_period*10;
- reset <= '0';
- wait for clk_period*5;
-
- -- check reset conditions
- assert arp_req_req.lookup_req = '0' report "arp_req_req.lookup_req not initialised correctly on reset";
- assert ip_tx_result = IPTX_RESULT_NONE report "ip_tx_result not initialised correctly on reset";
- assert ip_tx_data_out_ready = '0' report "ip_tx_data_out_ready not initialised correctly on reset";
- assert mac_tx_req = '0' report "mac_tx_req not initialised correctly on reset";
- assert mac_data_out_valid = '0' report "mac_data_out_valid not initialised correctly on reset";
- assert mac_data_out_last = '0' report "mac_data_out_last not initialised correctly on reset";
-
- -- insert stimulus here
-
- ------------
- -- TEST 1 -- basic functional tx test with some delays for arp and chn access
- ------------
-
- report "T1: basic functional tx test with some delays for arp and chn access";
-
- ip_tx.hdr.protocol <= x"35";
- ip_tx.hdr.data_length <= x"0008";
- ip_tx.hdr.dst_ip_addr <= x"c0123478";
- ip_tx_start <= '1';
- wait for clk_period;
- ip_tx_start <= '0'; wait for clk_period;
- arp_req_rslt.got_mac <= '0';
- arp_req_rslt.got_err <= '0';
-
- assert arp_req_req.lookup_req = '1' report "T1: lookup_req not set on tx start";
- assert ip_tx_result = IPTX_RESULT_SENDING report "T1: result should be IPTX_RESULT_SENDING";
-
- wait for clk_period*10; -- simulate arp lookup time
- arp_req_rslt.mac <= x"050423271016";
- arp_req_rslt.got_mac <= '1';
-
- wait for clk_period*2;
-
- assert arp_req_req.lookup_req = '0' report "T1: lookup_req not clear after setting";
- assert mac_tx_req = '1' report "T1: mac_tx_req not set after getting mac";
-
- wait for clk_period*10; -- simulate mac chn access time
- mac_tx_granted <= '1';
- wait for clk_period*2;
- mac_data_out_ready <= '1';
- assert mac_data_out_valid = '0' report "T1: mac_data_out_valid asserted too early";
-
- wait for clk_period;
-
- assert ip_tx_data_out_ready = '0' report "T1: IP data out ready asserted too early";
- wait for clk_period;
- assert mac_data_out_valid = '1' report "T1: mac_data_out_valid not asserted";
-
- -- wait until in eth hdr
- wait for clk_period*3;
- -- go mac not ready for 2 clocks
- mac_data_out_ready <= '0';
- wait for clk_period*2;
- mac_data_out_ready <= '1';
-
-
- wait until ip_tx_data_out_ready = '1';
-
- -- start to tx IP data
- ip_tx.data.data_out_valid <= '1';
- ip_tx.data.data_out <= x"56"; wait for clk_period;
- -- delay data in for 1 clk cycle
- ip_tx.data.data_out_valid <= '0';
- ip_tx.data.data_out <= x"57"; wait for clk_period;
- ip_tx.data.data_out_valid <= '1'; wait for clk_period;
- ip_tx.data.data_out <= x"58"; wait for clk_period;
- ip_tx.data.data_out <= x"59"; wait for clk_period;
-
- -- delay mac ready for 2 clk cycles
- mac_data_out_ready <= '0';
- ip_tx.data.data_out <= x"5a"; wait for clk_period;
- assert ip_tx_data_out_ready = '0' report "T1: ip_tx_data_out_ready not cleared when mac not ready";
-
- ip_tx.data.data_out <= x"5a"; wait for clk_period;
- mac_data_out_ready <= '1';
- wait until ip_tx_data_out_ready = '1';
- wait for clk_period;
- assert ip_tx_data_out_ready = '1' report "T1: ip_tx_data_out_ready not set when mac ready";
- ip_tx.data.data_out <= x"5b"; wait for clk_period;
- ip_tx.data.data_out <= x"5c"; wait for clk_period;
-
- ip_tx.data.data_out <= x"5d";
- ip_tx.data.data_out_last <= '1';
- wait for clk_period;
- assert mac_data_out_last = '1' report "T1: mac_datda_out_last not set on last byte";
-
- ip_tx.data.data_out_valid <= '0';
- ip_tx.data.data_out_last <= '0';
- wait for clk_period*2;
-
- assert ip_tx_result = IPTX_RESULT_SENT report "T1: result should be IPTX_RESULT_SENT";
- assert mac_tx_req = '0' report "T1: mac_tx_req held on too long after TX";
-
- mac_tx_granted <= '0';
- wait for clk_period*2;
-
- ------------
- -- TEST 2 -- basic functional tx test with no delays for arp and chn access
- ------------
-
- report "T2: basic functional tx test with no delays for arp and chn access";
-
- ip_tx.hdr.protocol <= x"11";
- ip_tx.hdr.data_length <= x"0006";
- ip_tx.hdr.dst_ip_addr <= x"c0123478";
- ip_tx_start <= '1';
- wait for clk_period;
- ip_tx_start <= '0'; wait for clk_period;
- arp_req_rslt.got_mac <= '0';
-
- assert arp_req_req.lookup_req = '1' report "T1: lookup_req not set on tx start";
- assert ip_tx_result = IPTX_RESULT_SENDING report "T1: result should be IPTX_RESULT_SENDING";
-
- wait for clk_period; -- simulate arp lookup time
- arp_req_rslt.mac <= x"050423271016";
- arp_req_rslt.got_mac <= '1';
-
- wait for clk_period*2;
-
- assert arp_req_req.lookup_req = '0' report "T1: lookup_req not clear after setting";
- assert mac_tx_req = '1' report "T1: mac_tx_req not set after getting mac";
-
- wait for clk_period; -- simulate mac chn access time
- mac_tx_granted <= '1';
- wait for clk_period*2;
- mac_data_out_ready <= '1';
-
- assert ip_tx_data_out_ready = '0' report "T1: IP data out ready asserted too early";
-
- wait until ip_tx_data_out_ready = '1';
-
- -- start to tx IP data
- ip_tx.data.data_out_valid <= '1';
- ip_tx.data.data_out <= x"c1"; wait for clk_period;
- ip_tx.data.data_out <= x"c2"; wait for clk_period;
- ip_tx.data.data_out <= x"c3"; wait for clk_period;
- ip_tx.data.data_out <= x"c4"; wait for clk_period;
- ip_tx.data.data_out <= x"c5"; wait for clk_period;
-
- ip_tx.data.data_out <= x"c6";
- ip_tx.data.data_out_last <= '1';
- wait for clk_period;
-
- assert mac_data_out_last = '1' report "T1: mac_datda_out_last not set on last byte";
-
-
- ip_tx.data.data_out_valid <= '0';
- ip_tx.data.data_out_last <= '0';
- wait for clk_period*2;
-
- assert ip_tx_result = IPTX_RESULT_SENT report "T1: result should be IPTX_RESULT_SENT";
- assert mac_tx_req = '0' report "T1: mac_tx_req held on too long after TX";
-
- mac_tx_granted <= '0';
- wait for clk_period*2;
-
- report "--- end of tests ---";
-
- wait;
- end process;
-
-END;
Index: udp_ip_stack/tags/v1.1/bench/vhdl/IP_complete_nomac_tb.vhd
===================================================================
--- udp_ip_stack/tags/v1.1/bench/vhdl/IP_complete_nomac_tb.vhd (revision 5)
+++ udp_ip_stack/tags/v1.1/bench/vhdl/IP_complete_nomac_tb.vhd (nonexistent)
@@ -1,387 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 13:54:32 06/04/2011
--- Design Name:
--- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/IP_complete_nomac_tb.vhd
--- Project Name: ip1
--- Target Device:
--- Tool versions:
--- Description:
---
--- VHDL Test Bench Created by ISE for module: IP_complete_nomac
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes:
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test. Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation
--- simulation model.
---------------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use work.axi.all;
-use work.ipv4_types.all;
-use work.arp_types.all;
-
-ENTITY IP_complete_nomac_tb IS
-END IP_complete_nomac_tb;
-
-ARCHITECTURE behavior OF IP_complete_nomac_tb IS
-
- -- Component Declaration for the Unit Under Test (UUT)
-
- COMPONENT IP_complete_nomac
- PORT(
- -- IP Layer signals
- ip_tx_start : in std_logic;
- ip_tx : in ipv4_tx_type; -- IP tx cxns
- ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
- ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
- ip_rx_start : out std_logic; -- indicates receipt of ip frame.
- ip_rx : out ipv4_rx_type;
- -- system signals
- rx_clk : in STD_LOGIC;
- tx_clk : in STD_LOGIC;
- reset : in STD_LOGIC;
- our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
- our_mac_address : in std_logic_vector (47 downto 0);
- -- status signals
- arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
- ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
- -- MAC Transmitter
- mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
- mac_tx_tvalid : out std_logic; -- tdata is valid
- mac_tx_tready : in std_logic; -- mac is ready to accept data
- mac_tx_tfirst : out std_logic; -- indicates first byte of frame
- mac_tx_tlast : out std_logic; -- indicates last byte of frame
- -- MAC Receiver
- mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
- mac_rx_tvalid : in std_logic; -- indicates tdata is valid
- mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
- mac_rx_tlast : in std_logic -- indicates last byte of the trame
- );
- END COMPONENT;
-
-
- --Inputs
- signal ip_tx_start : std_logic := '0';
- signal ip_tx : ipv4_tx_type;
-
- signal clk : std_logic := '0';
- signal reset : std_logic := '0';
- signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
- signal our_mac_address : std_logic_vector(47 downto 0) := (others => '0');
- signal mac_tx_tready : std_logic := '0';
- signal mac_rx_tdata : std_logic_vector(7 downto 0) := (others => '0');
- signal mac_rx_tvalid : std_logic := '0';
- signal mac_rx_tlast : std_logic := '0';
- --Outputs
- signal ip_tx_result : std_logic_vector (1 downto 0); -- tx status (changes during transmission)
- signal ip_tx_data_out_ready : std_logic; -- indicates IP TX is ready to take data
- signal ip_rx_start : std_logic;
- signal ip_rx : ipv4_rx_type;
- signal arp_pkt_count : std_logic_vector(7 downto 0);
- signal mac_tx_tdata : std_logic_vector(7 downto 0);
- signal mac_tx_tvalid : std_logic;
- signal mac_tx_tfirst : std_logic;
- signal mac_tx_tlast : std_logic;
- signal mac_rx_tready : std_logic;
-
- -- Clock period definitions
- constant clk_period : time := 8 ns;
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: IP_complete_nomac PORT MAP (
- ip_tx_start => ip_tx_start,
- ip_tx => ip_tx,
- ip_tx_result => ip_tx_result,
- ip_tx_data_out_ready => ip_tx_data_out_ready,
- ip_rx_start => ip_rx_start,
- ip_rx => ip_rx,
- rx_clk => clk,
- tx_clk => clk,
- reset => reset,
- our_ip_address => our_ip_address,
- our_mac_address => our_mac_address,
- arp_pkt_count => arp_pkt_count,
- mac_tx_tdata => mac_tx_tdata,
- mac_tx_tvalid => mac_tx_tvalid,
- mac_tx_tready => mac_tx_tready,
- mac_tx_tfirst => mac_tx_tfirst,
- mac_tx_tlast => mac_tx_tlast,
- mac_rx_tdata => mac_rx_tdata,
- mac_rx_tvalid => mac_rx_tvalid,
- mac_rx_tready => mac_rx_tready,
- mac_rx_tlast => mac_rx_tlast
- );
-
- -- Clock process definitions
- clk_process :process
- begin
- clk <= '1';
- wait for clk_period/2;
- clk <= '0';
- wait for clk_period/2;
- end process;
-
-
- -- Stimulus process
- stim_proc: process
- begin
- -- hold reset state for 100 ns.
- wait for 80 ns;
-
- our_ip_address <= x"c0a80509"; -- 192.168.5.9
- our_mac_address <= x"002320212223";
- ip_tx_start <= '0';
- mac_tx_tready <= '0';
-
- reset <= '1';
- wait for clk_period*10;
- reset <= '0';
- wait for clk_period*5;
-
- -- check reset conditions
- assert ip_tx_result = IPTX_RESULT_NONE report "ip_tx_result not initialised correctly on reset";
- assert ip_tx_data_out_ready = '0' report "ip_tx_data_out_ready not initialised correctly on reset";
- assert mac_tx_tvalid = '0' report "mac_tx_tvalid not initialised correctly on reset";
- assert mac_tx_tlast = '0' report " mac_tx_tlast not initialised correctly on reset";
- assert arp_pkt_count = x"00" report " arp_pkt_count not initialised correctly on reset";
- assert ip_rx_start = '0' report "ip_rx_start not initialised correctly on reset";
- assert ip_rx.hdr.is_valid = '0' report "ip_rx.hdr.is_valid not initialised correctly on reset";
- assert ip_rx.hdr.protocol = x"00" report "ip_rx.hdr.protocol not initialised correctly on reset";
- assert ip_rx.hdr.data_length = x"0000" report "ip_rx.hdr.data_length not initialised correctly on reset";
- assert ip_rx.hdr.src_ip_addr = x"00000000" report "ip_rx.hdr.src_ip_addr not initialised correctly on reset";
- assert ip_rx.hdr.num_frame_errors = x"00" report "ip_rx.hdr.num_frame_errors not initialised correctly on reset";
- assert ip_rx.data.data_in = x"00" report "ip_rx.data.data_in not initialised correctly on reset";
- assert ip_rx.data.data_in_valid = '0' report "ip_rx.data.data_in_valid not initialised correctly on reset";
- assert ip_rx.data.data_in_last = '0' report "ip_rx.data.data_in_last not initialised correctly on reset";
-
- -- insert stimulus here
-
- ------------
- -- TEST 1 -- basic functional rx test with received ip pkt
- ------------
-
- report "T1: Send an eth frame with IP pkt dst ip_address c0a80509, dst mac 002320212223";
-
- mac_tx_tready <= '1';
- mac_rx_tvalid <= '1';
- -- dst MAC (bc)
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"23"; wait for clk_period;
- mac_rx_tdata <= x"20"; wait for clk_period;
- mac_rx_tdata <= x"21"; wait for clk_period;
- mac_rx_tdata <= x"22"; wait for clk_period;
- mac_rx_tdata <= x"23"; wait for clk_period;
- -- src MAC
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"23"; wait for clk_period;
- mac_rx_tdata <= x"18"; wait for clk_period;
- mac_rx_tdata <= x"29"; wait for clk_period;
- mac_rx_tdata <= x"26"; wait for clk_period;
- mac_rx_tdata <= x"7c"; wait for clk_period;
- -- type
- mac_rx_tdata <= x"08"; wait for clk_period; -- IP pkt
- mac_rx_tdata <= x"00"; wait for clk_period;
- -- ver & HL / service type
- mac_rx_tdata <= x"45"; wait for clk_period;
- mac_rx_tdata <= x"00"; wait for clk_period;
- -- total len
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"18"; wait for clk_period;
- -- ID
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"00"; wait for clk_period;
- -- flags & frag
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"00"; wait for clk_period;
- -- TTL
- mac_rx_tdata <= x"00"; wait for clk_period;
- -- Protocol
- mac_rx_tdata <= x"11"; wait for clk_period;
- -- Header CKS
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"00"; wait for clk_period;
- -- SRC IP
- mac_rx_tdata <= x"c0"; wait for clk_period;
- mac_rx_tdata <= x"a8"; wait for clk_period;
- mac_rx_tdata <= x"05"; wait for clk_period;
- mac_rx_tdata <= x"01"; wait for clk_period;
- -- DST IP
- mac_rx_tdata <= x"c0"; wait for clk_period;
- mac_rx_tdata <= x"a8"; wait for clk_period;
- mac_rx_tdata <= x"05"; wait for clk_period;
- mac_rx_tdata <= x"09"; wait for clk_period;
-
- -- user data
- mac_rx_tdata <= x"24"; wait for clk_period;
-
- -- since we are up to the user data stage, the header should be valid and the data_in_valid should be set
- assert ip_rx.hdr.is_valid = '1' report "T1: ip_rx.hdr.is_valid not set";
- assert ip_rx.hdr.protocol = x"11" report "T1: ip_rx.hdr.protocol not set correctly";
- assert ip_rx.hdr.data_length = x"0004" report "T1: ip_rx.hdr.data_length not set correctly";
- assert ip_rx.hdr.src_ip_addr = x"c0a80501" report "T1: ip_rx.hdr.src_ip_addr not set correctly";
- assert ip_rx.hdr.num_frame_errors = x"00" report "T1: ip_rx.hdr.num_frame_errors not set correctly";
- assert ip_rx.hdr.last_error_code = x"0" report "T1: ip_rx.hdr.last_error_code not set correctly";
- assert ip_rx_start = '1' report "T1: ip_rx_start not set";
- assert ip_rx.data.data_in_valid = '1' report "T1: ip_rx.data.data_in_valid not set";
-
- mac_rx_tdata <= x"25"; wait for clk_period;
- mac_rx_tdata <= x"26"; wait for clk_period;
- mac_rx_tdata <= x"27"; mac_rx_tlast <= '1'; wait for clk_period;
-
- assert ip_rx.data.data_in_last = '1' report "T1: ip_rx.data.data_in_last not set";
-
-
- mac_rx_tdata <= x"00";
- mac_rx_tlast <= '0';
- mac_rx_tvalid <= '0';
- wait for clk_period;
-
- assert ip_rx.data.data_in_valid = '0' report "T1: ip_rx.data.data_in_valid not cleared";
- assert ip_rx.data.data_in_last = '0' report "T1: ip_rx.data.data_in_last not cleared";
- assert ip_rx.hdr.num_frame_errors = x"00" report "T1: ip_rx.hdr.num_frame_errors non zero at end of test";
- assert ip_rx.hdr.last_error_code = x"0" report "T1: ip_rx.hdr.last_error_code indicates error at end of test";
- assert ip_rx_start = '0' report "T1: ip_rx_start not cleared";
-
- ------------
- -- TEST 2 -- respond with IP TX
- ------------
-
- report "T2: respond with IP TX";
-
- ip_tx.hdr.protocol <= x"35";
- ip_tx.hdr.data_length <= x"0006";
- ip_tx.hdr.dst_ip_addr <= x"c0123478";
- ip_tx.data.data_out_valid <= '0';
- ip_tx.data.data_out_last <= '0';
- wait for clk_period;
-
- ip_tx_start <= '1'; wait for clk_period;
-
- ip_tx_start <= '0'; wait for clk_period;
-
- assert ip_tx_result = IPTX_RESULT_SENDING report "T1: result should be IPTX_RESULT_SENDING";
-
- wait for clk_period*2;
-
- assert ip_tx_data_out_ready = '0' report "T2: IP data out ready asserted too early";
-
- -- need to wait for ARP tx to complete
-
- wait for clk_period*50;
-
- assert mac_tx_tvalid = '0' report "T2: mac_tx_tvalid not cleared after ARP tx";
- assert mac_tx_tlast = '0' report "T2: mac_tx_tlast not cleared after ARP tx";
-
- -- now create the ARP response (rx)
-
- -- Send the reply
- -- Send an ARP reply: x"c0123478" has mac 02:12:03:23:04:54
- mac_rx_tvalid <= '1';
- -- dst MAC (bc)
- mac_rx_tdata <= x"ff"; wait for clk_period;
- mac_rx_tdata <= x"ff"; wait for clk_period;
- mac_rx_tdata <= x"ff"; wait for clk_period;
- mac_rx_tdata <= x"ff"; wait for clk_period;
- mac_rx_tdata <= x"ff"; wait for clk_period;
- mac_rx_tdata <= x"ff"; wait for clk_period;
- -- src MAC
- mac_rx_tdata <= x"02"; wait for clk_period;
- mac_rx_tdata <= x"12"; wait for clk_period;
- mac_rx_tdata <= x"03"; wait for clk_period;
- mac_rx_tdata <= x"23"; wait for clk_period;
- mac_rx_tdata <= x"04"; wait for clk_period;
- mac_rx_tdata <= x"54"; wait for clk_period;
- -- type
- mac_rx_tdata <= x"08"; wait for clk_period;
- mac_rx_tdata <= x"06"; wait for clk_period;
- -- HW type
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"01"; wait for clk_period;
- -- Protocol type
- mac_rx_tdata <= x"08"; wait for clk_period;
- mac_rx_tdata <= x"00"; wait for clk_period;
- -- HW size
- mac_rx_tdata <= x"06"; wait for clk_period;
- -- protocol size
- mac_rx_tdata <= x"04"; wait for clk_period;
- -- Opcode
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"02"; wait for clk_period;
- -- Sender MAC
- mac_rx_tdata <= x"02"; wait for clk_period;
- mac_rx_tdata <= x"12"; wait for clk_period;
- mac_rx_tdata <= x"03"; wait for clk_period;
- mac_rx_tdata <= x"23"; wait for clk_period;
- mac_rx_tdata <= x"04"; wait for clk_period;
- mac_rx_tdata <= x"54"; wait for clk_period;
- -- Sender IP
- mac_rx_tdata <= x"c0"; wait for clk_period;
- mac_rx_tdata <= x"12"; wait for clk_period;
- mac_rx_tdata <= x"34"; wait for clk_period;
- mac_rx_tdata <= x"78"; wait for clk_period;
- -- Target MAC
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"23"; wait for clk_period;
- mac_rx_tdata <= x"20"; wait for clk_period;
- mac_rx_tdata <= x"21"; wait for clk_period;
- mac_rx_tdata <= x"22"; wait for clk_period;
- mac_rx_tdata <= x"23"; wait for clk_period;
- -- Target IP
- mac_rx_tdata <= x"c0"; wait for clk_period;
- mac_rx_tdata <= x"a8"; wait for clk_period;
- mac_rx_tdata <= x"05"; wait for clk_period;
- mac_rx_tdata <= x"09"; wait for clk_period;
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tlast <= '1';
- mac_rx_tdata <= x"00"; wait for clk_period;
- mac_rx_tlast <= '0';
- mac_rx_tvalid <= '0';
-
- wait until ip_tx_data_out_ready = '1';
-
- -- start to tx IP data
- ip_tx.data.data_out_valid <= '1';
- ip_tx.data.data_out <= x"56"; wait for clk_period;
- ip_tx.data.data_out <= x"57"; wait for clk_period;
- ip_tx.data.data_out <= x"58"; wait for clk_period;
- ip_tx.data.data_out <= x"59"; wait for clk_period;
- ip_tx.data.data_out <= x"5a"; wait for clk_period;
-
- ip_tx.data.data_out <= x"5b";
- ip_tx.data.data_out_last <= '1';
- wait for clk_period;
-
- assert mac_tx_tlast = '1' report "T1: mac_tx_tlast not set on last byte";
-
- wait for clk_period;
-
- ip_tx.data.data_out_valid <= '0';
- ip_tx.data.data_out_last <= '0';
- wait for clk_period*2;
-
- assert ip_tx_result = IPTX_RESULT_SENT report "T1: result should be SENT";
- wait for clk_period*2;
-
-
- report "-- end of tests --";
-
- wait;
- end process;
-
-END;
Index: udp_ip_stack/tags/v1.1/bench/vhdl/UDP_RX_tb.vhd
===================================================================
--- udp_ip_stack/tags/v1.1/bench/vhdl/UDP_RX_tb.vhd (revision 5)
+++ udp_ip_stack/tags/v1.1/bench/vhdl/UDP_RX_tb.vhd (nonexistent)
@@ -1,324 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 16:53:03 06/10/2011
--- Design Name:
--- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/UDP_RX_tb.vhd
--- Project Name: ip1
--- Target Device:
--- Tool versions:
--- Description:
---
--- VHDL Test Bench Created by ISE for module: UDP_RX
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes:
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test. Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation
--- simulation model.
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use work.axi.all;
-use work.ipv4_types.all;
-
-ENTITY UDP_RX_tb IS
-END UDP_RX_tb;
-
-ARCHITECTURE behavior OF UDP_RX_tb IS
-
- -- Component Declaration for the Unit Under Test (UUT)
-
- COMPONENT UDP_RX
- PORT(
- -- UDP Layer signals
- udp_rxo : inout udp_rx_type;
- udp_rx_start : out std_logic; -- indicates receipt of udp header
- -- system signals
- clk : in STD_LOGIC;
- reset : in STD_LOGIC;
- -- IP layer RX signals
- ip_rx_start : in std_logic; -- indicates receipt of ip header
- ip_rx : inout ipv4_rx_type
- );
- END COMPONENT;
-
-
- --Inputs
- signal clk : std_logic := '0';
- signal reset : std_logic := '0';
- signal ip_rx_start : std_logic := '0';
-
- --BiDirs
- signal udp_rxo : udp_rx_type;
- signal ip_rx : ipv4_rx_type;
-
- --Outputs
- signal udp_rx_start : std_logic;
-
- -- Clock period definitions
- constant clk_period : time := 8 ns;
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: UDP_RX PORT MAP (
- udp_rxo => udp_rxo,
- udp_rx_start => udp_rx_start,
- clk => clk,
- reset => reset,
- ip_rx_start => ip_rx_start,
- ip_rx => ip_rx
- );
-
- -- Clock process definitions
- clk_process :process
- begin
- clk <= '0';
- wait for clk_period/2;
- clk <= '1';
- wait for clk_period/2;
- end process;
-
-
- -- Stimulus process
- stim_proc: process
- begin
- -- hold reset state for 100 ns.
- wait for 100 ns;
- ip_rx_start <= '0';
- ip_rx.data.data_in_valid <= '0';
- ip_rx.data.data_in_last <= '0';
- ip_rx.hdr.is_valid <= '0';
- ip_rx.hdr.protocol <= (others => '0');
- ip_rx.hdr.num_frame_errors <= (others => '0');
- ip_rx.hdr.last_error_code <= (others => '0');
-
- reset <= '1';
- wait for clk_period*10;
- reset <= '0';
- wait for clk_period*5;
- reset <= '0';
-
- -- check reset conditions
- assert udp_rx_start = '0' report "udp_rx_start not initialised correctly on reset";
- assert udp_rxo.hdr.is_valid = '0' report "udp_rxo.hdr.is_valid not initialised correctly on reset";
- assert udp_rxo.data.data_in = x"00" report "udp_rxo.data.data_in not initialised correctly on reset";
- assert udp_rxo.data.data_in_valid = '0' report "udp_rxo.data.data_in_valid not initialised correctly on reset";
- assert udp_rxo.data.data_in_last = '0' report "udp_rxo.data.data_in_last not initialised correctly on reset";
-
- -- insert stimulus here
-
- ------------
- -- TEST 1 -- basic functional rx test with received ip pkt
- ------------
-
- report "T1: Send an ip frame with IP src ip_address c0a80501, udp protocol from port x1498 to port x8724 and 3 bytes data";
-
- ip_rx_start <= '1';
- ip_rx.data.data_in_valid <= '0';
- ip_rx.data.data_in_last <= '0';
- ip_rx.hdr.is_valid <= '1';
- ip_rx.hdr.protocol <= x"11"; -- UDP
- ip_rx.hdr.data_length <= x"000b";
- ip_rx.hdr.src_ip_addr<= x"c0a80501";
- wait for clk_period*3;
- -- now send the data
- ip_rx.data.data_in_valid <= '1';
- ip_rx.data.data_in <= x"14"; wait for clk_period; -- src port
- ip_rx.data.data_in <= x"98"; wait for clk_period;
- ip_rx.data.data_in <= x"87"; wait for clk_period; -- dst port
- ip_rx.data.data_in <= x"24"; wait for clk_period;
- ip_rx.data.data_in <= x"00"; wait for clk_period; -- len (hdr + data)
- ip_rx.data.data_in <= x"0b"; wait for clk_period;
- ip_rx.data.data_in <= x"00"; wait for clk_period; -- mty cks
- ip_rx.data.data_in <= x"00"; wait for clk_period;
- -- udp hdr should be valid
- assert udp_rxo.hdr.is_valid = '1' report "T1: udp_rxo.hdr.is_valid not set";
-
- ip_rx.data.data_in <= x"41"; wait for clk_period; -- data
-
- assert udp_rxo.hdr.src_ip_addr = x"c0a80501" report "T1: udp_rxo.hdr.src_ip_addr not set correctly";
- assert udp_rxo.hdr.src_port = x"1498" report "T1: udp_rxo.hdr.src_port not set correctly";
- assert udp_rxo.hdr.dst_port = x"8724" report "T1: udp_rxo.hdr.dst_port not set correctly";
- assert udp_rxo.hdr.data_length = x"0003" report "T1: udp_rxo.hdr.data_length not set correctly";
- assert udp_rx_start = '1' report "T1: udp_rx_start not set";
- assert udp_rxo.data.data_in_valid = '1' report "T1: udp_rxo.data.data_in_valid not set";
-
- ip_rx.data.data_in <= x"45"; wait for clk_period; -- data
- ip_rx.data.data_in <= x"49"; ip_rx.data.data_in_last <= '1'; wait for clk_period;
- assert udp_rxo.data.data_in_last = '1' report "T1: udp_rxo.data.data_in_last not set";
- ip_rx_start <= '0';
- ip_rx.data.data_in_valid <= '0';
- ip_rx.data.data_in_last <= '0';
- ip_rx.hdr.is_valid <= '0';
- wait for clk_period;
- assert udp_rxo.data.data_in = x"00" report "T1: udp_rxo.data.data_in not cleared";
- assert udp_rxo.data.data_in_valid = '0' report "T1: udp_rxo.data.data_in_valid not cleared";
- assert udp_rxo.data.data_in_last = '0' report "T1: udp_rxo.data.data_in_last not cleared";
-
- wait for clk_period;
-
- ------------
- -- TEST 2 -- ability to receive 2nd ip pkt
- ------------
-
- report "T2: Send an ip frame with IP src ip_address c0a80501, udp protocol from port x7623 to port x0365 and 5 bytes data";
-
- ip_rx_start <= '1';
- ip_rx.data.data_in_valid <= '0';
- ip_rx.data.data_in_last <= '0';
- ip_rx.hdr.is_valid <= '1';
- ip_rx.hdr.protocol <= x"11"; -- UDP
- ip_rx.hdr.data_length <= x"000b";
- ip_rx.hdr.src_ip_addr<= x"c0a80501";
- wait for clk_period*3;
- -- now send the data
- ip_rx.data.data_in_valid <= '1';
- ip_rx.data.data_in <= x"76"; wait for clk_period; -- src port
- ip_rx.data.data_in <= x"23"; wait for clk_period;
- ip_rx.data.data_in <= x"03"; wait for clk_period; -- dst port
- ip_rx.data.data_in <= x"65"; wait for clk_period;
- ip_rx.data.data_in <= x"00"; wait for clk_period; -- len (hdr + data)
- ip_rx.data.data_in <= x"0d"; wait for clk_period;
- ip_rx.data.data_in <= x"00"; wait for clk_period; -- mty cks
- ip_rx.data.data_in <= x"00"; wait for clk_period;
- -- udp hdr should be valid
- assert udp_rxo.hdr.is_valid = '1' report "T2: udp_rxo.hdr.is_valid not set";
-
- ip_rx.data.data_in <= x"17"; wait for clk_period; -- data
-
- assert udp_rxo.hdr.src_ip_addr = x"c0a80501" report "T2: udp_rxo.hdr.src_ip_addr not set correctly";
- assert udp_rxo.hdr.src_port = x"7623" report "T2: udp_rxo.hdr.src_port not set correctly";
- assert udp_rxo.hdr.dst_port = x"0365" report "T2: udp_rxo.hdr.dst_port not set correctly";
- assert udp_rxo.hdr.data_length = x"0005" report "T2: udp_rxo.hdr.data_length not set correctly";
- assert udp_rx_start = '1' report "T2: udp_rx_start not set";
- assert udp_rxo.data.data_in_valid = '1' report "T2: udp_rxo.data.data_in_valid not set";
-
- ip_rx.data.data_in <= x"37"; wait for clk_period; -- data
- ip_rx.data.data_in <= x"57"; wait for clk_period; -- data
- ip_rx.data.data_in <= x"73"; wait for clk_period; -- data
- ip_rx.data.data_in <= x"f9"; ip_rx.data.data_in_last <= '1'; wait for clk_period;
- assert udp_rxo.data.data_in_last = '1' report "T2: udp_rxo.data.data_in_last not set";
- ip_rx_start <= '0';
- ip_rx.data.data_in_valid <= '0';
- ip_rx.data.data_in_last <= '0';
- ip_rx.hdr.is_valid <= '0';
- wait for clk_period;
- assert udp_rxo.data.data_in = x"00" report "T2: udp_rxo.data.data_in not cleared";
- assert udp_rxo.data.data_in_valid = '0' report "T2: udp_rxo.data.data_in_valid not cleared";
- assert udp_rxo.data.data_in_last = '0' report "T2: udp_rxo.data.data_in_last not cleared";
-
- ------------
- -- TEST 3 -- ability to reject non-udp protocols
- ------------
-
- report "T3: Send an ip frame with IP src ip_address c0a80501, protocol x12 from port x7623 to port x0365 and 5 bytes data";
-
- ip_rx_start <= '1';
- ip_rx.data.data_in_valid <= '0';
- ip_rx.data.data_in_last <= '0';
- ip_rx.hdr.is_valid <= '1';
- ip_rx.hdr.protocol <= x"12"; -- non-UDP
- ip_rx.hdr.data_length <= x"000b";
- ip_rx.hdr.src_ip_addr<= x"c0a80501";
- wait for clk_period*3;
- -- now send the data
- ip_rx.data.data_in_valid <= '1';
- ip_rx.data.data_in <= x"76"; wait for clk_period; -- src port
- ip_rx.data.data_in <= x"23"; wait for clk_period;
- ip_rx.data.data_in <= x"03"; wait for clk_period; -- dst port
- ip_rx.data.data_in <= x"65"; wait for clk_period;
- ip_rx.data.data_in <= x"00"; wait for clk_period; -- len (hdr + data)
- ip_rx.data.data_in <= x"0d"; wait for clk_period;
- ip_rx.data.data_in <= x"00"; wait for clk_period; -- mty cks
- ip_rx.data.data_in <= x"00"; wait for clk_period;
- -- udp hdr should be valid
- assert udp_rxo.hdr.is_valid = '0' report "T3: udp_rxo.hdr.is_valid incorrectly set";
-
- ip_rx.data.data_in <= x"17"; wait for clk_period; -- data
-
- assert udp_rx_start = '0' report "T3: udp_rx_start incorrectly set";
- assert udp_rxo.data.data_in_valid = '0' report "T3: udp_rxo.data.data_in_valid not set";
-
- ip_rx.data.data_in <= x"37"; wait for clk_period; -- data
- ip_rx.data.data_in <= x"57"; wait for clk_period; -- data
- ip_rx.data.data_in <= x"73"; wait for clk_period; -- data
- ip_rx.data.data_in <= x"f9"; ip_rx.data.data_in_last <= '1'; wait for clk_period;
- assert udp_rxo.data.data_in_last = '0' report "T3: udp_rxo.data.data_in_last incorrectly set";
- ip_rx_start <= '0';
- ip_rx.data.data_in_valid <= '0';
- ip_rx.data.data_in_last <= '0';
- ip_rx.hdr.is_valid <= '0';
- wait for clk_period;
- assert udp_rxo.data.data_in = x"00" report "T3: udp_rxo.data.data_in not cleared";
- assert udp_rxo.data.data_in_valid = '0' report "T3: udp_rxo.data.data_in_valid not cleared";
- assert udp_rxo.data.data_in_last = '0' report "T3: udp_rxo.data.data_in_last not cleared";
-
- wait for clk_period;
-
- ------------
- -- TEST 4 -- Ability to receive UDP pkt after non-UDP pkt
- ------------
-
- report "T4: Send an ip frame with IP src ip_address c0a80501, udp protocol from port x1498 to port x8724 and 3 bytes data";
-
- ip_rx_start <= '1';
- ip_rx.data.data_in_valid <= '0';
- ip_rx.data.data_in_last <= '0';
- ip_rx.hdr.is_valid <= '1';
- ip_rx.hdr.protocol <= x"11"; -- UDP
- ip_rx.hdr.data_length <= x"000b";
- ip_rx.hdr.src_ip_addr<= x"c0a80501";
- wait for clk_period*3;
- -- now send the data
- ip_rx.data.data_in_valid <= '1';
- ip_rx.data.data_in <= x"14"; wait for clk_period; -- src port
- ip_rx.data.data_in <= x"98"; wait for clk_period;
- ip_rx.data.data_in <= x"87"; wait for clk_period; -- dst port
- ip_rx.data.data_in <= x"24"; wait for clk_period;
- ip_rx.data.data_in <= x"00"; wait for clk_period; -- len (hdr + data)
- ip_rx.data.data_in <= x"0b"; wait for clk_period;
- ip_rx.data.data_in <= x"00"; wait for clk_period; -- mty cks
- ip_rx.data.data_in <= x"00"; wait for clk_period;
- -- udp hdr should be valid
- assert udp_rxo.hdr.is_valid = '1' report "T4: udp_rxo.hdr.is_valid not set";
-
- ip_rx.data.data_in <= x"41"; wait for clk_period; -- data
-
- assert udp_rxo.hdr.src_ip_addr = x"c0a80501" report "T4: udp_rxo.hdr.src_ip_addr not set correctly";
- assert udp_rxo.hdr.src_port = x"1498" report "T4: udp_rxo.hdr.src_port not set correctly";
- assert udp_rxo.hdr.dst_port = x"8724" report "T4: udp_rxo.hdr.dst_port not set correctly";
- assert udp_rxo.hdr.data_length = x"0003" report "T4: udp_rxo.hdr.data_length not set correctly";
- assert udp_rx_start = '1' report "T4: udp_rx_start not set";
- assert udp_rxo.data.data_in_valid = '1' report "T4: udp_rxo.data.data_in_valid not set";
-
- ip_rx.data.data_in <= x"45"; wait for clk_period; -- data
- ip_rx.data.data_in <= x"49"; ip_rx.data.data_in_last <= '1'; wait for clk_period;
- assert udp_rxo.data.data_in_last = '1' report "T4: udp_rxo.data.data_in_last not set";
- ip_rx_start <= '0';
- ip_rx.data.data_in_valid <= '0';
- ip_rx.data.data_in_last <= '0';
- ip_rx.hdr.is_valid <= '0';
- wait for clk_period;
- assert udp_rxo.data.data_in = x"00" report "T4: udp_rxo.data.data_in not cleared";
- assert udp_rxo.data.data_in_valid = '0' report "T4: udp_rxo.data.data_in_valid not cleared";
- assert udp_rxo.data.data_in_last = '0' report "T4: udp_rxo.data.data_in_last not cleared";
-
- wait for clk_period;
-
- report "--- end of tests ---";
-
- wait;
- end process;
-
-END;
Index: udp_ip_stack/tags/v1.1/bench/vhdl/arp_tb.vhd
===================================================================
--- udp_ip_stack/tags/v1.1/bench/vhdl/arp_tb.vhd (revision 5)
+++ udp_ip_stack/tags/v1.1/bench/vhdl/arp_tb.vhd (nonexistent)
@@ -1,384 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:35:50 05/31/2011
--- Design Name:
--- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/arp1/arp_tb.vhd
--- Project Name: arp1
--- Target Device:
--- Tool versions:
--- Description:
---
--- VHDL Test Bench Created by ISE for module: arp
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes:
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test. Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation
--- simulation model.
---------------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-use work.arp_types.all;
-
-ENTITY arp_tb IS
-END arp_tb;
-
-ARCHITECTURE behavior OF arp_tb IS
-
- -- Component Declaration for the Unit Under Test (UUT)
-
- COMPONENT arp
- PORT(
- -- lookup request signals
- arp_req_req : in arp_req_req_type;
- arp_req_rslt : out arp_req_rslt_type;
- -- MAC layer RX signals
- data_in_clk : in STD_LOGIC;
- reset : in STD_LOGIC;
- data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
- data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock
- data_in_last : in STD_LOGIC; -- indicates last data in frame
- -- MAC layer TX signals
- mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
- mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
- data_out_clk : in std_logic;
- data_out_ready : in std_logic; -- indicates system ready to consume data
- data_out_valid : out std_logic; -- indicates data out is valid
- data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
- data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
- data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
- -- system signals
- our_mac_address : in STD_LOGIC_VECTOR (47 downto 0);
- our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
- req_count : out STD_LOGIC_VECTOR(7 downto 0) -- count of arp pkts received
- );
- END COMPONENT;
-
-
- --Inputs
- signal clk : std_logic := '0';
- signal reset : std_logic := '0';
- signal data_in : std_logic_vector(7 downto 0) := (others => '0');
- signal data_in_valid : std_logic := '0';
- signal data_in_last : std_logic := '0';
- signal our_mac_address : std_logic_vector(47 downto 0) := (others => '0');
- signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
- signal data_out_ready : std_logic;
- signal data_out_valid : std_logic;
- signal data_out_first : std_logic;
- signal data_out_last : std_logic;
- signal data_out : std_logic_vector (7 downto 0);
- signal req_count : STD_LOGIC_VECTOR(7 downto 0);
- signal arp_req_req : arp_req_req_type;
- signal arp_req_rslt : arp_req_rslt_type;
- signal mac_tx_req : std_logic;
- signal mac_tx_granted : std_logic;
-
-
- -- Clock period definitions
- constant clk_period : time := 8 ns;
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: arp PORT MAP (
- -- lookup request mappings
- arp_req_req => arp_req_req,
- arp_req_rslt => arp_req_rslt,
- -- rx mappings
- data_in_clk => clk,
- reset => reset,
- data_in => data_in,
- data_in_valid => data_in_valid,
- data_in_last => data_in_last,
- -- tx mappings
- mac_tx_req => mac_tx_req,
- mac_tx_granted => mac_tx_granted,
- data_out_clk => clk,
- data_out_ready => data_out_ready,
- data_out_valid => data_out_valid,
- data_out_first => data_out_first,
- data_out_last => data_out_last,
- data_out => data_out,
- -- system mappings
- our_mac_address => our_mac_address,
- our_ip_address => our_ip_address,
- req_count => req_count
- );
-
- -- Clock process definitions
- clk_process :process
- begin
- clk <= '0';
- wait for clk_period/2;
- clk <= '1';
- wait for clk_period/2;
- end process;
-
-
- -- Stimulus process
- stim_proc: process
- begin
- -- hold reset state for 100 ns.
- wait for 100 ns;
-
- our_ip_address <= x"c0a80509"; -- 192.168.5.9
- our_mac_address <= x"002320212223";
- mac_tx_granted <= '1'; -- FIXME 0
-
- reset <= '1';
- wait for clk_period*10;
- reset <= '0';
- wait for clk_period*5;
-
- assert mac_tx_req = '0' report "mac_tx_req asserted on reset";
-
- -- insert stimulus here
- arp_req_req.lookup_req <= '0';
- arp_req_req.ip <= (others => '0');
- data_out_ready <= '1';
-
- report "T1: Send an ARP request: who has 192.168.5.8? Tell 192.168.5.1";
- data_in_valid <= '1';
- -- dst MAC (bc)
- data_in <= x"ff"; wait for clk_period;
- data_in <= x"ff"; wait for clk_period;
- data_in <= x"ff"; wait for clk_period;
- data_in <= x"ff"; wait for clk_period;
- data_in <= x"ff"; wait for clk_period;
- data_in <= x"ff"; wait for clk_period;
- -- src MAC
- data_in <= x"00"; wait for clk_period;
- data_in <= x"23"; wait for clk_period;
- data_in <= x"18"; wait for clk_period;
- data_in <= x"29"; wait for clk_period;
- data_in <= x"26"; wait for clk_period;
- data_in <= x"7c"; wait for clk_period;
- -- type
- data_in <= x"08"; wait for clk_period;
- data_in <= x"06"; wait for clk_period;
- -- HW type
- data_in <= x"00"; wait for clk_period;
- data_in <= x"01"; wait for clk_period;
- -- Protocol type
- data_in <= x"08"; wait for clk_period;
- data_in <= x"00"; wait for clk_period;
- -- HW size
- data_in <= x"06"; wait for clk_period;
- -- protocol size
- data_in <= x"04"; wait for clk_period;
- -- Opcode
- data_in <= x"00"; wait for clk_period;
- data_in <= x"01"; wait for clk_period;
- -- Sender MAC
- data_in <= x"00"; wait for clk_period;
- data_in <= x"23"; wait for clk_period;
- data_in <= x"18"; wait for clk_period;
- data_in <= x"29"; wait for clk_period;
- data_in <= x"26"; wait for clk_period;
- data_in <= x"7c"; wait for clk_period;
- -- Sender IP
- data_in <= x"c0"; wait for clk_period;
- data_in <= x"a8"; wait for clk_period;
- data_in <= x"05"; wait for clk_period;
- data_in <= x"01"; wait for clk_period;
- -- Target MAC
- data_in <= x"00"; wait for clk_period;
- data_in <= x"00"; wait for clk_period;
- data_in <= x"00"; wait for clk_period;
- data_in <= x"00"; wait for clk_period;
- data_in <= x"00"; wait for clk_period;
- data_in <= x"00"; wait for clk_period;
- -- Target IP
- data_in <= x"c0"; wait for clk_period;
- data_in <= x"a8"; wait for clk_period;
- data_in <= x"05"; wait for clk_period;
- data_in <= x"09"; wait for clk_period;
- data_in <= x"00"; wait for clk_period;
- data_in <= x"00"; wait for clk_period;
- data_in <= x"00"; wait for clk_period;
- data_in_last <= '1';
- data_in <= x"00"; wait for clk_period;
- data_in_last <= '0';
- data_in_valid <= '0';
-
- -- check tx arbitration signals
-
- assert mac_tx_req = '1' report "T1: mac_tx_req not set";
-
- -- ready to tx
- data_out_ready <= '1';
- mac_tx_granted <= '1';
- wait for clk_period*10;
- data_out_ready <= '0';
- wait for clk_period*2;
- data_out_ready <= '1';
- wait for clk_period*50;
-
- report "T2: Send another ARP request: who has 192.168.5.8? Tell 192.168.5.1, holding off transmitter";
- data_out_ready <= '0';
- data_in_valid <= '1';
- -- dst MAC (bc)
- data_in <= x"ff"; wait for clk_period;
- data_in <= x"ff"; wait for clk_period;
- data_in <= x"ff"; wait for clk_period;
- data_in <= x"ff"; wait for clk_period;
- data_in <= x"ff"; wait for clk_period;
- data_in <= x"ff"; wait for clk_period;
- -- src MAC
- data_in <= x"00"; wait for clk_period;
- data_in <= x"23"; wait for clk_period;
- data_in <= x"18"; wait for clk_period;
- data_in <= x"29"; wait for clk_period;
- data_in <= x"26"; wait for clk_period;
- data_in <= x"7c"; wait for clk_period;
- -- type
- data_in <= x"08"; wait for clk_period;
- data_in <= x"06"; wait for clk_period;
- -- HW type
- data_in <= x"00"; wait for clk_period;
- data_in <= x"01"; wait for clk_period;
- -- Protocol type
- data_in <= x"08"; wait for clk_period;
- data_in <= x"00"; wait for clk_period;
- -- HW size
- data_in <= x"06"; wait for clk_period;
- -- protocol size
- data_in <= x"04"; wait for clk_period;
- -- Opcode
- data_in <= x"00"; wait for clk_period;
- data_in <= x"01"; wait for clk_period;
- -- Sender MAC
- data_in <= x"00"; wait for clk_period;
- data_in <= x"23"; wait for clk_period;
- data_in <= x"18"; wait for clk_period;
- data_in <= x"29"; wait for clk_period;
- data_in <= x"26"; wait for clk_period;
- data_in <= x"7c"; wait for clk_period;
- -- Sender IP
- data_in <= x"c0"; wait for clk_period;
- data_in <= x"a8"; wait for clk_period;
- data_in <= x"05"; wait for clk_period;
- data_in <= x"01"; wait for clk_period;
- -- Target MAC
- data_in <= x"00"; wait for clk_period;
- data_in <= x"00"; wait for clk_period;
- data_in <= x"00"; wait for clk_period;
- data_in <= x"00"; wait for clk_period;
- data_in <= x"00"; wait for clk_period;
- data_in <= x"00"; wait for clk_period;
- -- Target IP
- data_in <= x"c0"; wait for clk_period;
- data_in <= x"a8"; wait for clk_period;
- data_in <= x"05"; wait for clk_period;
- data_in <= x"09"; wait for clk_period;
- data_in <= x"00"; wait for clk_period;
- data_in <= x"00"; wait for clk_period;
- data_in <= x"00"; wait for clk_period;
- data_in_last <= '1';
- data_in <= x"00"; wait for clk_period;
- data_in_last <= '0';
- data_in_valid <= '0';
-
- -- ready to tx
- wait for clk_period*10;
- data_out_ready <= '1';
-
- wait for clk_period*50;
-
- -- Send a request for the IP that is already cached
- arp_req_req.ip <= x"c0a80501";
- arp_req_req.lookup_req <= '1';
- wait for clk_period;
- arp_req_req.lookup_req <= '0';
-
- wait for clk_period*50;
-
- -- Send a request for the IP that is not cached
- arp_req_req.ip <= x"c0a80503";
- arp_req_req.lookup_req <= '1';
- wait for clk_period;
- arp_req_req.lookup_req <= '0';
- wait for clk_period*80;
- -- Send the reply
- data_out_ready <= '1';
-
- report "T3: Send an ARP reply: 192.168.5.3 has mac 02:12:03:23:04:54";
- data_in_valid <= '1';
- -- dst MAC (bc)
- data_in <= x"ff"; wait for clk_period;
- data_in <= x"ff"; wait for clk_period;
- data_in <= x"ff"; wait for clk_period;
- data_in <= x"ff"; wait for clk_period;
- data_in <= x"ff"; wait for clk_period;
- data_in <= x"ff"; wait for clk_period;
- -- src MAC
- data_in <= x"02"; wait for clk_period;
- data_in <= x"12"; wait for clk_period;
- data_in <= x"03"; wait for clk_period;
- data_in <= x"23"; wait for clk_period;
- data_in <= x"04"; wait for clk_period;
- data_in <= x"54"; wait for clk_period;
- -- type
- data_in <= x"08"; wait for clk_period;
- data_in <= x"06"; wait for clk_period;
- -- HW type
- data_in <= x"00"; wait for clk_period;
- data_in <= x"01"; wait for clk_period;
- -- Protocol type
- data_in <= x"08"; wait for clk_period;
- data_in <= x"00"; wait for clk_period;
- -- HW size
- data_in <= x"06"; wait for clk_period;
- -- protocol size
- data_in <= x"04"; wait for clk_period;
- -- Opcode
- data_in <= x"00"; wait for clk_period;
- data_in <= x"02"; wait for clk_period;
- -- Sender MAC
- data_in <= x"02"; wait for clk_period;
- data_in <= x"12"; wait for clk_period;
- data_in <= x"03"; wait for clk_period;
- data_in <= x"23"; wait for clk_period;
- data_in <= x"04"; wait for clk_period;
- data_in <= x"54"; wait for clk_period;
- -- Sender IP
- data_in <= x"c0"; wait for clk_period;
- data_in <= x"a8"; wait for clk_period;
- data_in <= x"05"; wait for clk_period;
- data_in <= x"03"; wait for clk_period;
- -- Target MAC
- data_in <= x"00"; wait for clk_period;
- data_in <= x"23"; wait for clk_period;
- data_in <= x"20"; wait for clk_period;
- data_in <= x"21"; wait for clk_period;
- data_in <= x"22"; wait for clk_period;
- data_in <= x"23"; wait for clk_period;
- -- Target IP
- data_in <= x"c0"; wait for clk_period;
- data_in <= x"a8"; wait for clk_period;
- data_in <= x"05"; wait for clk_period;
- data_in <= x"09"; wait for clk_period;
- data_in <= x"00"; wait for clk_period;
- data_in <= x"00"; wait for clk_period;
- data_in <= x"00"; wait for clk_period;
- data_in_last <= '1';
- data_in <= x"00"; wait for clk_period;
- data_in_last <= '0';
- data_in_valid <= '0';
-
- report "--- end of tests ---";
- wait;
- end process;
-
-END;
Index: udp_ip_stack/tags/v1.1/bench/vhdl/UDP_TX_tb.vhd
===================================================================
--- udp_ip_stack/tags/v1.1/bench/vhdl/UDP_TX_tb.vhd (revision 5)
+++ udp_ip_stack/tags/v1.1/bench/vhdl/UDP_TX_tb.vhd (nonexistent)
@@ -1,219 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 18:43:49 06/10/2011
--- Design Name:
--- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/UDP_TX_tb.vhd
--- Project Name: ip1
--- Target Device:
--- Tool versions:
--- Description:
---
--- VHDL Test Bench Created by ISE for module: UDP_TX
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes:
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test. Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation
--- simulation model.
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use work.axi.all;
-use work.ipv4_types.all;
-
-ENTITY UDP_TX_tb IS
-END UDP_TX_tb;
-
-ARCHITECTURE behavior OF UDP_TX_tb IS
-
- -- Component Declaration for the Unit Under Test (UUT)
-
- COMPONENT UDP_TX
- PORT(
- -- UDP Layer signals
- udp_tx_start : in std_logic; -- indicates req to tx UDP
- udp_txi : in udp_tx_type; -- UDP tx cxns
- udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
- udp_tx_data_out_ready: out std_logic; -- indicates udp_tx is ready to take data
- -- system signals
- clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
- reset : in STD_LOGIC;
- -- IP layer TX signals
- ip_tx_start : out std_logic;
- ip_tx : out ipv4_tx_type; -- IP tx cxns
- ip_tx_result : in std_logic_vector (1 downto 0); -- tx status (changes during transmission)
- ip_tx_data_out_ready : in std_logic -- indicates IP TX is ready to take data
- );
- END COMPONENT;
-
-
- --Inputs
- signal udp_tx_start : std_logic := '0';
- signal clk : std_logic := '0';
- signal reset : std_logic := '0';
- signal udp_txi : udp_tx_type;
- signal ip_tx_result : std_logic_vector (1 downto 0); -- tx status (changes during transmission)
- signal ip_tx_data_out_ready : std_logic; -- indicates IP TX is ready to take data
-
- --Outputs
- signal ip_tx_start : std_logic := '0';
- signal ip_tx : ipv4_tx_type;
- signal udp_tx_result : std_logic_vector (1 downto 0);
- signal udp_tx_data_out_ready : std_logic;
-
- -- Clock period definitions
- constant clk_period : time := 8 ns;
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: UDP_TX PORT MAP (
- udp_tx_start => udp_tx_start,
- udp_txi => udp_txi,
- udp_tx_result => udp_tx_result,
- udp_tx_data_out_ready => udp_tx_data_out_ready,
- clk => clk,
- reset => reset,
- ip_tx_start => ip_tx_start,
- ip_tx => ip_tx,
- ip_tx_result => ip_tx_result,
- ip_tx_data_out_ready => ip_tx_data_out_ready
- );
-
-
- -- Clock process definitions
- clk_process :process
- begin
- clk <= '0';
- wait for clk_period/2;
- clk <= '1';
- wait for clk_period/2;
- end process;
-
-
- -- Stimulus process
- stim_proc: process
- begin
- -- hold reset state for 100 ns.
- wait for 100 ns;
-
- udp_tx_start <= '0';
-
- udp_txi.hdr.dst_ip_addr <= (others => '0');
- udp_txi.hdr.dst_port <= (others => '0');
- udp_txi.hdr.src_port <= (others => '0');
- udp_txi.hdr.data_length <= (others => '0');
- udp_txi.hdr.checksum <= (others => '0');
- udp_txi.data.data_out_last <= '0';
-
- reset <= '1';
- wait for clk_period*10;
- reset <= '0';
- wait for clk_period*5;
-
- -- check reset conditions
-
- assert ip_tx_start = '0' report "ip_tx_start not initialised correctly on reset";
- assert ip_tx.data.data_out_valid = '0' report "ip_tx.data.data_out_valid not initialised correctly on reset";
- assert ip_tx.data.data_out_last = '0' report "ip_tx.data.data_out_last not initialised correctly on reset";
- assert udp_tx_result = UDPTX_RESULT_NONE report "udp_tx_result not initialised correctly on reset";
-
- -- insert stimulus here
-
- wait for clk_period*5;
-
- ------------
- -- TEST 1 -- basic functional tx test
- ------------
-
- report "T1: basic functional tx test - send 56, 57, 58 to port 8532";
-
- udp_txi.hdr.dst_ip_addr <= x"c0123478";
- udp_txi.hdr.dst_port <= x"1467";
- udp_txi.hdr.src_port <= x"8532";
- udp_txi.hdr.data_length <= x"0003";
-
- udp_tx_start <= '1';
- ip_tx_data_out_ready <= '1'; -- IP layer can accept data
- wait for clk_period;
- udp_tx_start <= '0'; wait for clk_period;
- ip_tx_result <= IPTX_RESULT_NONE;
-
- assert udp_tx_result = UDPTX_RESULT_SENDING report "T1: result should be UDPTX_RESULT_SENDING";
-
- wait until udp_tx_data_out_ready = '1';
-
- -- start to tx IP data
- udp_txi.data.data_out_valid <= '1';
- udp_txi.data.data_out <= x"56"; wait for clk_period;
- udp_txi.data.data_out <= x"57"; wait for clk_period;
-
- udp_txi.data.data_out <= x"58";
- udp_txi.data.data_out_last <= '1';
- wait for clk_period;
-
- assert ip_tx.data.data_out_last = '1' report "T1: ip_tx.datda_out_last not set on last byte";
-
- udp_txi.data.data_out_valid <= '0';
- udp_txi.data.data_out_last <= '0';
- wait for clk_period*2;
- ip_tx_result <= IPTX_RESULT_SENT;
-
- assert udp_tx_result = UDPTX_RESULT_SENT report "T1: result should be UDPTX_RESULT_SENT";
- wait for clk_period*2;
-
- ------------
- -- TEST 2 -- 2nd pkt
- ------------
-
- report "T2: send a second pkt - 56,57,58,59 to port 8532";
-
- udp_txi.hdr.dst_ip_addr <= x"c0123475";
- udp_txi.hdr.dst_port <= x"1467";
- udp_txi.hdr.src_port <= x"8532";
- udp_txi.hdr.data_length <= x"0005";
-
- udp_tx_start <= '1';
- ip_tx_data_out_ready <= '1'; -- IP layer can accept data
- wait for clk_period;
- udp_tx_start <= '0'; wait for clk_period;
-
- assert udp_tx_result = UDPTX_RESULT_SENDING report "T1: result should be UDPTX_RESULT_SENDING";
-
- wait until udp_tx_data_out_ready = '1';
-
- -- start to tx IP data
- udp_txi.data.data_out_valid <= '1';
- udp_txi.data.data_out <= x"56"; wait for clk_period;
- udp_txi.data.data_out <= x"57"; wait for clk_period;
- udp_txi.data.data_out <= x"58"; wait for clk_period;
- udp_txi.data.data_out <= x"59"; wait for clk_period;
-
- udp_txi.data.data_out <= x"5a";
- udp_txi.data.data_out_last <= '1';
- wait for clk_period;
- assert ip_tx.data.data_out_last = '1' report "T1: ip_tx.datda_out_last not set on last byte";
-
- udp_txi.data.data_out_valid <= '0';
- udp_txi.data.data_out_last <= '0';
- wait for clk_period*2;
-
- assert udp_tx_result = UDPTX_RESULT_SENT report "T1: result should be UDPTX_RESULT_SENT";
- wait for clk_period*2;
-
- report "--- end of tests ---";
-
- wait;
- end process;
-
-END;