URL
https://opencores.org/ocsvn/udp_ip_stack/udp_ip_stack/trunk
Subversion Repositories udp_ip_stack
Compare Revisions
- This comparison shows the changes necessary to convert path
/udp_ip_stack/trunk/rtl/vhdl/ml605
- from Rev 10 to Rev 8
- ↔ Reverse comparison
Rev 10 → Rev 8
/xv6mac_straight.vhd
File deleted
/IP_complete.vhd
27,9 → 27,7
entity IP_complete is |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s) |
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error |
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
); |
Port ( |
-- IP Layer signals |
75,9 → 73,7
COMPONENT IP_complete_nomac |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s) |
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error |
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
); |
Port ( |
-- IP Layer signals |
115,7 → 111,7
------------------------------------------------------------------------------ |
-- Component Declaration for the MAC layer |
------------------------------------------------------------------------------ |
component mac_layer_v2_1 |
component mac_layer |
port ( |
-- System controls |
------------------ |
188,10 → 184,8
IP_layer : IP_complete_nomac |
generic map ( |
CLOCK_FREQ => CLOCK_FREQ, |
ARP_TIMEOUT => ARP_TIMEOUT, |
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO, |
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES |
) |
ARP_TIMEOUT => ARP_TIMEOUT |
) |
PORT MAP ( |
-- IP Layer signals |
ip_tx_start => ip_tx_start, |
227,7 → 221,7
------------------------------------------------------------------------------ |
-- Instantiate the MAC layer |
------------------------------------------------------------------------------ |
mac_block : mac_layer_v2_1 |
mac_block : mac_layer |
Port map( |
-- System controls |
------------------ |
/UDP_Complete.vhd
28,9 → 28,7
entity UDP_Complete is |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s) |
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error |
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
); |
Port ( |
-- UDP TX signals |
70,9 → 68,6
); |
end UDP_Complete; |
|
|
|
|
architecture structural of UDP_Complete is |
|
------------------------------------------------------------------------------ |
82,9 → 77,7
COMPONENT UDP_Complete_nomac |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s) |
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error |
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
); |
Port ( |
-- UDP TX signals |
125,8 → 118,7
------------------------------------------------------------------------------ |
-- Component Declaration for the MAC layer |
------------------------------------------------------------------------------ |
component mac_v2_2 |
-- component xv6mac_straight |
component mac_layer |
port ( |
-- System controls |
------------------ |
204,13 → 196,11
------------------------------------------------------------------------------ |
|
udp_block: UDP_Complete_nomac |
generic map ( |
generic map ( |
CLOCK_FREQ => CLOCK_FREQ, |
ARP_TIMEOUT => ARP_TIMEOUT, |
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO, |
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES |
ARP_TIMEOUT => ARP_TIMEOUT |
) |
PORT MAP ( |
PORT MAP ( |
-- UDP TX signals |
udp_tx_start => udp_tx_start, |
udp_txi => udp_txi, |
248,8 → 238,7
------------------------------------------------------------------------------ |
-- Instantiate the MAC layer |
------------------------------------------------------------------------------ |
mac_block : mac_v2_2 |
-- mac_block : xv6mac_straight |
mac_block : mac_layer |
Port map( |
-- System controls |
------------------ |
293,4 → 282,3
|
end structural; |
|
|
/UDP_integration_example.vhd
35,8 → 35,6
-- System controls |
------------------ |
PBTX : in std_logic; |
PB_DO_SECOND_TX : in std_logic; |
DO_SECOND_TX_LED : out std_logic; |
UDP_RX : out std_logic; |
UDP_Start : out std_logic; |
PBTX_LED : out std_logic; |
66,16 → 64,13
|
architecture Behavioral of UDP_integration_example is |
|
|
------------------------------------------------------------------------------ |
-- Component Declaration for the complete UDP layer |
-- Component Declaration for the complete IP layer |
------------------------------------------------------------------------------ |
component UDP_Complete |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s) |
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error |
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
); |
Port ( |
-- UDP TX signals |
115,13 → 110,10
); |
end component; |
|
-- for UDP_block : UDP_Complete use configuration work.UDP_Complete.udpc_multi_slot_arp; |
|
|
type state_type is (IDLE, WAIT_RX_DONE, DATA_OUT, PAUSE, CHECK_SECOND_TX, SET_SEC_HDR); |
type state_type is (IDLE, WAIT_RX_DONE, DATA_OUT); |
type count_mode_type is (RST, INCR, HOLD); |
type set_clr_type is (SET, CLR, HOLD); |
type sec_tx_ctrl_type is (CLR,PRIME,DO,HOLD); |
|
-- system signals |
signal clk_int : std_logic; |
144,9 → 136,7
signal tx_start_reg : std_logic; |
signal tx_started_reg : std_logic; |
signal tx_fin_reg : std_logic; |
signal prime_second_tx : std_logic; -- if want to do a 2nd tx after the first |
signal do_second_tx : std_logic; -- if need to do a 2nd tx as next tx |
|
|
-- control signals |
signal next_state : state_type; |
signal set_state : std_logic; |
158,7 → 148,6
signal set_tx_fin : set_clr_type; |
signal first_byte_rx : STD_LOGIC_VECTOR(7 downto 0); |
signal control_int : udp_control_type; |
signal set_second_tx : sec_tx_ctrl_type; |
|
begin |
|
165,12 → 154,11
process ( |
our_ip, our_mac, udp_tx_result_int, udp_rx_int, udp_tx_start_int, udp_rx_start_int, ip_rx_hdr_int, |
udp_tx_int, count, clk_int, ip_pkt_count_int, arp_pkt_count_int, |
reset, tx_started_reg, tx_fin_reg, tx_start_reg, state, prime_second_tx, do_second_tx, set_second_tx, |
PB_DO_SECOND_TX, do_second_tx |
reset, tx_started_reg, tx_fin_reg, tx_start_reg |
) |
begin |
-- set up our local addresses and default controls |
our_ip <= x"c0a80019"; -- 192.168.0.25 |
our_ip <= x"c0a80509"; -- 192.168.5.9 |
our_mac <= x"002320212223"; |
control_int.ip_controls.arp_controls.clear_cache <= '0'; |
|
186,7 → 174,6
TX_Completed <= tx_fin_reg; |
TX_RSLT_0 <= udp_tx_result_int(0); |
TX_RSLT_1 <= udp_tx_result_int(1); |
DO_SECOND_TX_LED <= prime_second_tx; |
|
-- set display leds to show IP pkt rx count on 7..4 and arp rx count on 3..0 |
display (7 downto 4) <= ip_pkt_count_int (3 downto 0); |
196,9 → 183,6
when IDLE => display (3 downto 0) <= "0001"; |
when WAIT_RX_DONE => display (3 downto 0) <= "0010"; |
when DATA_OUT => display (3 downto 0) <= "0011"; |
when PAUSE => display (3 downto 0) <= "0100"; |
when CHECK_SECOND_TX => display (3 downto 0) <= "0101"; |
when SET_SEC_HDR => display (3 downto 0) <= "0110"; |
end case; |
|
end process; |
209,12 → 193,12
tx_proc_combinatorial: process( |
-- inputs |
udp_rx_start_int, udp_rx_int, udp_tx_data_out_ready_int, udp_tx_result_int, ip_rx_hdr_int, |
udp_tx_int.data.data_out_valid, PBTX, PB_DO_SECOND_TX, |
udp_tx_int.data.data_out_valid, PBTX, |
-- state |
state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg, prime_second_tx, do_second_tx, |
state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg, |
-- controls |
next_state, set_state, set_count, set_hdr, set_tx_start, set_last, |
set_tx_started, set_tx_fin, first_byte_rx, set_second_tx |
set_tx_started, set_tx_fin, first_byte_rx |
) |
begin |
-- set output_followers |
234,12 → 218,7
first_byte_rx <= (others => '0'); |
udp_tx_int.data.data_out <= (others => '0'); |
udp_tx_int.data.data_out_valid <= '0'; |
set_second_tx <= HOLD; |
|
if PB_DO_SECOND_TX = '1' then |
set_second_tx <= PRIME; |
end if; |
|
-- FSM |
case state is |
|
280,7 → 259,6
set_tx_start <= CLR; |
set_tx_fin <= SET; |
set_tx_started <= CLR; |
set_second_tx <= CLR; |
next_state <= IDLE; |
set_state <= '1'; |
else |
298,7 → 276,7
set_last <= '1'; |
set_tx_fin <= SET; |
set_tx_started <= CLR; |
next_state <= PAUSE; |
next_state <= IDLE; |
set_state <= '1'; |
else |
set_count <= INCR; |
305,30 → 283,7
end if; |
end if; |
end if; |
|
when PAUSE => |
next_state <= CHECK_SECOND_TX; |
set_state <= '1'; |
|
|
when CHECK_SECOND_TX => |
if prime_second_tx = '1' then |
set_second_tx <= DO; |
next_state <= SET_SEC_HDR; |
set_state <= '1'; |
else |
set_second_tx <= CLR; |
next_state <= IDLE; |
set_state <= '1'; |
end if; |
|
when SET_SEC_HDR => |
set_hdr <= '1'; |
set_tx_started <= SET; |
set_tx_start <= SET; |
next_state <= DATA_OUT; |
set_state <= '1'; |
|
end case; |
end process; |
|
351,8 → 306,6
tx_started_reg <= '0'; |
tx_fin_reg <= '0'; |
PBTX_LED <= '0'; |
do_second_tx <= '0'; |
prime_second_tx <= '0'; |
else |
PBTX_LED <= PBTX; |
|
372,21 → 325,11
|
-- set tx hdr |
if set_hdr = '1' then |
-- select the dst addr of the tx: |
-- if do_second_tx, to solaris box |
-- otherwise control according to first byte of received data: |
-- B = broadcast |
-- C = to dummy address to test timeout |
-- D to solaris box |
-- otherwise, direct to sender |
if do_second_tx = '1' then |
tx_hdr.dst_ip_addr <= x"c0a80005"; -- set dst to solaris box at 192.168.0.5 |
elsif first_byte_rx = x"42" then |
-- if the first byte of the rx pkt is 'B' then send to broadcast, otherwise send to reply IP |
if first_byte_rx = x"42" then |
tx_hdr.dst_ip_addr <= IP_BC_ADDR; -- send to Broadcast addr |
elsif first_byte_rx = x"43" then |
tx_hdr.dst_ip_addr <= x"c0bbccdd"; -- set dst unknown so get ARP timeout |
elsif first_byte_rx = x"44" then |
tx_hdr.dst_ip_addr <= x"c0a80005"; -- set dst to solaris box at 192.168.0.5 |
else |
tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr; -- reply to sender |
end if; |
418,22 → 361,8
when CLR => tx_fin_reg <= '0'; |
when HOLD => tx_fin_reg <= tx_fin_reg; |
end case; |
|
-- set do_second_tx |
case set_second_tx is |
when PRIME => |
prime_second_tx <= '1'; |
when DO => |
prime_second_tx <= '0'; |
do_second_tx <= '1'; |
when CLR => |
prime_second_tx <= '0'; |
do_second_tx <= '0'; |
when HOLD => |
prime_second_tx <= prime_second_tx; |
do_second_tx <= do_second_tx; |
end case; |
|
|
end if; |
end if; |
|
446,7 → 375,7
------------------------------------------------------------------------------ |
UDP_block : UDP_Complete |
generic map ( |
ARP_TIMEOUT => 10 -- timeout in seconds |
ARP_TIMEOUT => 30 -- timeout in seconds |
) |
PORT MAP ( |
-- UDP interface |
/udp_constraints.ucf
20,18 → 20,17
NET "display[6]" LOC = AE24; |
NET "display[7]" LOC = AD24; |
|
NET PBTX_LED LOC = AD21; |
NET UDP_RX LOC = AH27; |
NET DO_SECOND_TX_LED LOC = AH28; |
NET TX_RSLT_0 LOC = AE21; |
NET TX_RSLT_1 LOC = AP24; |
NET PBTX_LED LOC = AD21; |
NET UDP_RX LOC = AH27; |
NET UDP_START LOC = AH28; |
NET TX_RSLT_0 LOC = AE21; |
NET TX_RSLT_1 LOC = AP24; |
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#### Module Push_Buttons_4Bit constraints |
NET PBTX LOC = H17; |
NET PB_DO_SECOND_TX LOC = A18; |
NET reset_leds LOC = G26; |
NET PBTX LOC = H17; |
NET reset_leds LOC = G26; |
|
#### Module DIP_Switches_4Bit constraints |
|