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URL https://opencores.org/ocsvn/udp_ip_stack/udp_ip_stack/trunk

Subversion Repositories udp_ip_stack

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  • This comparison shows the changes necessary to convert path 
    /udp_ip_stack/trunk/rtl/vhdl
    from Rev 8 to Rev 6
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Rev 8 → Rev 6

/arp.vhd
23,8 → 23,7
-- Revision 0.01 - File Created
-- Revision 0.02 - Added req for mac tx and wait for grant
-- Revision 0.03 - Added data_out_first
-- Revision 0.04 - Added arp response timeout
-- Revision 0.05 - Added arp cache reset control
 
-- Additional Comments:
--
----------------------------------------------------------------------------------
33,11 → 32,7
use IEEE.NUMERIC_STD.ALL;
use work.arp_types.all;
 
entity arp is
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s)
);
entity arp is
Port (
-- lookup request signals
arp_req_req : in arp_req_req_type;
59,8 → 54,7
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in STD_LOGIC_VECTOR (47 downto 0);
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
control : in arp_control_type;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
req_count : out STD_LOGIC_VECTOR(7 downto 0) -- count of arp pkts received
);
end arp;
67,7 → 61,7
 
architecture Behavioral of arp is
 
type req_state_type is (IDLE,LOOKUP,REQUEST,WAIT_REPLY,PAUSE1,PAUSE2,PAUSE3);
type req_state_type is (IDLE,LOOKUP,REQUEST,WAIT_REPLY);
type rx_state_type is (IDLE,PARSE,PROCESS_ARP,WAIT_END);
type rx_event_type is (NO_EVENT,DATA);
type count_mode_type is (RST,INCR,HOLD);
91,9 → 85,6
signal mac_addr_valid_reg: std_logic;
signal send_request_needed : std_logic;
signal tx_mac_chn_reqd : std_logic;
signal freq_scaler : unsigned (31 downto 0); -- scales data_in_clk downto 1Hz
signal timer : unsigned (7 downto 0); -- counts seconds timeout
signal timeout_reg : std_logic;
signal rx_state : rx_state_type;
signal rx_count : unsigned (7 downto 0);
102,7 → 93,7
signal arp_entry : arp_entry_type; -- arp entry store
signal new_arp_entry : arp_entry_type;
signal tx_state : tx_state_type;
signal tx_count : unsigned (7 downto 0);
signal tx_count : unsigned (7 downto 0);
 
-- FIXME - remove these debug state signals
signal arp_err_data : std_logic_vector (7 downto 0);
119,9 → 110,6
signal set_mac_addr_invalid : std_logic;
signal set_send_req : std_logic;
signal clear_send_req : std_logic;
signal set_timer : count_mode_type; -- timer reset, count, hold control
signal timer_enable : std_logic; -- enable the timer counting
signal set_timeout : set_clr_type; -- control the timeout register
-- rx control signals
195,19 → 183,12
-- input signals
arp_req_req,
-- state variables
req_state, req_ip_addr, mac_addr_found, mac_addr_valid_reg, send_request_needed, arp_entry,
freq_scaler, timer, timeout_reg,
req_state, req_ip_addr, mac_addr_found, mac_addr_valid_reg, send_request_needed, arp_entry,
-- control signals
next_req_state, set_req_state, set_req_ip, set_mac_addr, control,
set_mac_addr_invalid,set_send_req, clear_send_req, set_timer, timer_enable, set_timeout
)
next_req_state, set_req_state, set_req_ip, set_mac_addr,set_mac_addr_invalid,set_send_req, clear_send_req)
begin
-- set output followers
if arp_req_req.lookup_req = '1' then
arp_req_rslt.got_err <= '0';
else
arp_req_rslt.got_err <= timeout_reg;
end if;
-- set output followers
arp_req_rslt.got_err <= '0'; -- errors not returned in this version
-- zero time response to lookup request if already in cache
if arp_req_req.lookup_req = '1' and arp_req_req.ip = arp_entry.ip and arp_entry.is_valid = '1' then
arp_req_rslt.got_mac <= '1';
228,26 → 209,16
set_mac_addr_invalid <= '0';
set_send_req <= '0';
clear_send_req <= '0';
set_timer <= INCR; -- default is timer running, unless we hold or reset it
set_timeout <= HOLD;
timer_enable <= '0';
-- combinatorial logic
if freq_scaler = x"00000000" then
timer_enable <= '1';
end if;
-- REQ FSM
case req_state is
when IDLE =>
set_timer <= RST;
if arp_req_req.lookup_req = '1' then
-- check if we already have the info in cache
if arp_req_req.ip = arp_entry.ip and arp_entry.is_valid = '1' then
-- already have this IP
set_mac_addr <= '1';
else
set_timeout <= CLR;
else
next_req_state <= LOOKUP;
set_req_state <= '1';
set_req_ip <= '1';
262,11 → 233,10
set_req_state <= '1';
set_mac_addr <= '1';
else
-- need to request mac for this IP
set_send_req <= '1';
set_timer <= RST;
-- need to request mac for this IP
next_req_state <= REQUEST;
set_req_state <= '1';
set_send_req <= '1';
end if;
when REQUEST =>
275,28 → 245,12
set_req_state <= '1';
when WAIT_REPLY =>
if arp_entry.is_valid = '1' then
-- have reply, go back to LOOKUP state to see if it is the right one
next_req_state <= LOOKUP;
set_req_state <= '1';
end if;
if timer >= ARP_TIMEOUT then
set_timeout <= SET;
next_req_state <= PAUSE1;
set_req_state <= '1';
end if;
 
when PAUSE1 =>
next_req_state <= PAUSE2;
set_req_state <= '1';
 
when PAUSE2 =>
next_req_state <= PAUSE3;
set_req_state <= '1';
 
when PAUSE3 =>
next_req_state <= IDLE;
set_req_state <= '1';
if arp_entry.is_valid = '1' then
-- have reply, go back to LOOKUP state to see if it is the right one
next_req_state <= LOOKUP;
set_req_state <= '1';
end if;
-- TODO: add timeout here
 
end case;
end process;
310,10 → 264,7
req_ip_addr <= (others => '0');
mac_addr_found <= (others => '0');
mac_addr_valid_reg <= '0';
send_request_needed <= '0';
freq_scaler <= to_unsigned(CLOCK_FREQ,32);
timer <= (others => '0');
timeout_reg <= '0';
send_request_needed <= '0';
else
-- Next req_state processing
if set_req_state = '1' then
348,35 → 299,7
else
mac_addr_found <= mac_addr_found;
mac_addr_valid_reg <= mac_addr_valid_reg;
end if;
-- freq scaling and 1-sec timer
if freq_scaler = x"00000000" then
freq_scaler <= to_unsigned(CLOCK_FREQ,32);
else
freq_scaler <= freq_scaler - 1;
end if;
-- timer processing
case set_timer is
when RST =>
timer <= x"00";
when INCR =>
if timer_enable = '1' then
timer <= timer + 1;
else
timer <= timer;
end if;
when HOLD =>
timer <= timer;
end case;
-- timeout latching
case set_timeout is
when CLR => timeout_reg <= '0';
when SET => timeout_reg <= '1';
when HOLD => timeout_reg <= timeout_reg;
end case;
end if;
end if;
end if;
590,13 → 513,8
if (set_ip1 = '1') then new_arp_entry.ip(15 downto 8) <= dataval; end if;
if (set_ip0 = '1') then new_arp_entry.ip(7 downto 0) <= dataval; end if;
-- set arp entry request
if control.clear_cache = '1' then
arp_entry.ip <= x"00000000";
arp_entry.mac <= x"000000000000";
arp_entry.is_valid <= '0';
arp_entry.reply_required <= '0';
elsif set_arp_entry_request = '1' then
-- set arp entry request
if set_arp_entry_request = '1' then
-- copy info from new entry to arp_entry and set reply required
arp_entry.mac <= new_arp_entry.mac;
arp_entry.ip <= new_arp_entry.ip;
/ml605/UDP_integration_example.vhd
40,8 → 40,6
PBTX_LED : out std_logic;
TX_Started : out std_logic;
TX_Completed : out std_logic;
TX_RSLT_0 : out std_logic;
TX_RSLT_1 : out std_logic;
reset_leds : in std_logic;
display : out std_logic_vector(7 downto 0);
68,10 → 66,6
-- Component Declaration for the complete IP layer
------------------------------------------------------------------------------
component UDP_Complete
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s)
);
Port (
-- UDP TX signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
90,7 → 84,6
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in udp_control_type;
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
111,7 → 104,7
end component;
 
 
type state_type is (IDLE, WAIT_RX_DONE, DATA_OUT);
type state_type is (IDLE, DATA_OUT);
type count_mode_type is (RST, INCR, HOLD);
type set_clr_type is (SET, CLR, HOLD);
 
136,6 → 129,7
signal tx_start_reg : std_logic;
signal tx_started_reg : std_logic;
signal tx_fin_reg : std_logic;
signal udp_rx_start_reg : std_logic;
-- control signals
signal next_state : state_type;
146,21 → 140,20
signal set_last : std_logic;
signal set_tx_started : set_clr_type;
signal set_tx_fin : set_clr_type;
signal set_udp_rx_start_reg : set_clr_type;
signal first_byte_rx : STD_LOGIC_VECTOR(7 downto 0);
signal control_int : udp_control_type;
 
begin
 
process (
our_ip, our_mac, udp_tx_result_int, udp_rx_int, udp_tx_start_int, udp_rx_start_int, ip_rx_hdr_int,
our_ip, our_mac, udp_rx_int, udp_tx_start_int, udp_rx_start_int, ip_rx_hdr_int, udp_rx_start_reg,
udp_tx_int, count, clk_int, ip_pkt_count_int, arp_pkt_count_int,
reset, tx_started_reg, tx_fin_reg, tx_start_reg
)
begin
-- set up our local addresses and default controls
-- set up our local addresses
our_ip <= x"c0a80509"; -- 192.168.5.9
our_mac <= x"002320212223";
control_int.ip_controls.arp_controls.clear_cache <= '0';
-- determine RX good and error LEDs
if udp_rx_int.hdr.is_valid = '1' then
169,36 → 162,28
UDP_RX <= '0';
end if;
UDP_Start <= udp_rx_start_int;
UDP_Start <= udp_rx_start_reg;
TX_Started <= tx_start_reg; --tx_started_reg;
TX_Completed <= tx_fin_reg;
TX_RSLT_0 <= udp_tx_result_int(0);
TX_RSLT_1 <= udp_tx_result_int(1);
-- set display leds to show IP pkt rx count on 7..4 and arp rx count on 3..0
display (7 downto 4) <= ip_pkt_count_int (3 downto 0);
-- display (3 downto 0) <= arp_pkt_count_int (3 downto 0);
case state is
when IDLE => display (3 downto 0) <= "0001";
when WAIT_RX_DONE => display (3 downto 0) <= "0010";
when DATA_OUT => display (3 downto 0) <= "0011";
end case;
 
display (3 downto 0) <= arp_pkt_count_int (3 downto 0);
end process;
-- AUTO TX process - on receipt of any UDP pkt, send a response. data sent is modified if a broadcast was received.
-- AUTO TX process - on receipt of any UDP pkt, send a response,
-- TX response process - COMB
-- TX response process - COMB
tx_proc_combinatorial: process(
-- inputs
udp_rx_start_int, udp_rx_int, udp_tx_data_out_ready_int, udp_tx_result_int, ip_rx_hdr_int,
udp_tx_int.data.data_out_valid, PBTX,
udp_rx_start_int, udp_tx_data_out_ready_int, udp_tx_int.data.data_out_valid,
udp_rx_int, PBTX, reset_leds,
-- state
state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg,
state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg, udp_rx_start_reg,
-- controls
next_state, set_state, set_count, set_hdr, set_tx_start, set_last,
set_tx_started, set_tx_fin, first_byte_rx
set_tx_started, set_tx_fin, set_udp_rx_start_reg, first_byte_rx
)
begin
-- set output_followers
215,14 → 200,14
set_last <= '0';
set_tx_started <= HOLD;
set_tx_fin <= HOLD;
set_udp_rx_start_reg <= HOLD;
first_byte_rx <= (others => '0');
udp_tx_int.data.data_out <= (others => '0');
udp_tx_int.data.data_out_valid <= '0';
-- FSM
case state is
when IDLE =>
udp_tx_int.data.data_out <= (others => '0');
udp_tx_int.data.data_out_valid <= '0';
if udp_rx_start_int = '1' or PBTX = '1' then
if udp_rx_start_int = '1' then
230,58 → 215,34
else
first_byte_rx <= x"00";
end if;
set_udp_rx_start_reg <= SET;
set_tx_started <= SET;
set_hdr <= '1';
set_tx_start <= SET;
set_tx_fin <= CLR;
set_count <= RST;
set_hdr <= '1';
if udp_rx_int.data.data_in_last = '1' then
set_tx_started <= SET;
set_tx_start <= SET;
next_state <= DATA_OUT;
set_state <= '1';
else
next_state <= WAIT_RX_DONE;
set_state <= '1';
end if;
end if;
when WAIT_RX_DONE =>
-- wait until RX pkt fully received
if udp_rx_int.data.data_in_last = '1' then
set_tx_started <= SET;
set_tx_start <= SET;
next_state <= DATA_OUT;
set_state <= '1';
elsif reset_leds = '1' then
set_udp_rx_start_reg <= CLR;
set_tx_started <= CLR;
set_tx_fin <= CLR;
end if;
when DATA_OUT =>
if udp_tx_result_int = UDPTX_RESULT_ERR then
-- have an error from the IP TX layer, clear down the TX
set_tx_start <= CLR;
set_tx_fin <= SET;
set_tx_started <= CLR;
next_state <= IDLE;
set_state <= '1';
else
if udp_tx_result_int = UDPTX_RESULT_SENDING then
set_tx_start <= CLR; -- reset out start req as soon as we know we are sending
end if;
if ip_rx_hdr_int.is_broadcast = '1' then
udp_tx_int.data.data_out <= std_logic_vector(count) or x"50";
udp_tx_int.data.data_out <= std_logic_vector(count) or x"40";
udp_tx_int.data.data_out_valid <= udp_tx_data_out_ready_int;
if udp_tx_data_out_ready_int = '1' then
set_tx_start <= CLR;
if unsigned(count) = x"03" then
set_last <= '1';
set_tx_fin <= SET;
set_tx_started <= CLR;
next_state <= IDLE;
set_state <= '1';
else
udp_tx_int.data.data_out <= std_logic_vector(count) or x"40";
set_count <= INCR;
end if;
udp_tx_int.data.data_out_valid <= udp_tx_data_out_ready_int;
if udp_tx_data_out_ready_int = '1' then
if unsigned(count) = x"03" then
set_last <= '1';
set_tx_fin <= SET;
set_tx_started <= CLR;
next_state <= IDLE;
set_state <= '1';
else
set_count <= INCR;
end if;
end if;
end if;
end case;
327,11 → 288,9
if set_hdr = '1' then
-- if the first byte of the rx pkt is 'B' then send to broadcast, otherwise send to reply IP
if first_byte_rx = x"42" then
tx_hdr.dst_ip_addr <= IP_BC_ADDR; -- send to Broadcast addr
elsif first_byte_rx = x"43" then
tx_hdr.dst_ip_addr <= x"c0bbccdd"; -- set dst unknown so get ARP timeout
tx_hdr.dst_ip_addr <= IP_BC_ADDR;
else
tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr; -- reply to sender
tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr;
end if;
tx_hdr.dst_port <= udp_rx_int.hdr.src_port;
tx_hdr.src_port <= udp_rx_int.hdr.dst_port;
361,6 → 320,13
when CLR => tx_fin_reg <= '0';
when HOLD => tx_fin_reg <= tx_fin_reg;
end case;
 
-- set UDP START signal
case set_udp_rx_start_reg is
when SET => udp_rx_start_reg <= '1';
when CLR => udp_rx_start_reg <= '0';
when HOLD => udp_rx_start_reg <= udp_rx_start_reg;
end case;
end if;
367,17 → 333,13
end if;
 
end process;
 
------------------------------------------------------------------------------
-- Instantiate the UDP layer
------------------------------------------------------------------------------
UDP_block : UDP_Complete
generic map (
ARP_TIMEOUT => 30 -- timeout in seconds
)
PORT MAP (
UDP_block : UDP_Complete PORT MAP
(
-- UDP interface
udp_tx_start => udp_tx_start_int,
udp_txi => udp_tx_int,
394,7 → 356,6
reset => reset,
our_ip_address => our_ip,
our_mac_address => our_mac,
control => control_int,
-- status signals
arp_pkt_count => arp_pkt_count_int,
ip_pkt_count => ip_pkt_count_int,
/ml605/IP_complete.vhd
25,10 → 25,6
use work.arp_types.all;
 
entity IP_complete is
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s)
);
Port (
-- IP Layer signals
ip_tx_start : in std_logic;
44,7 → 40,6
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in ip_control_type;
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
71,11 → 66,7
------------------------------------------------------------------------------
 
COMPONENT IP_complete_nomac
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s)
);
Port (
PORT(
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
89,7 → 80,6
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in ip_control_type;
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
104,7 → 94,7
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
);
END COMPONENT;
 
 
181,12 → 171,8
-- Instantiate the IP layer
------------------------------------------------------------------------------
 
IP_layer : IP_complete_nomac
generic map (
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT
)
PORT MAP (
IP_layer : IP_complete_nomac PORT MAP
(
-- IP Layer signals
ip_tx_start => ip_tx_start,
ip_tx => ip_tx,
200,7 → 186,6
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
control => control,
-- status signals
arp_pkt_count => arp_pkt_count,
ip_pkt_count => ip_pkt_count,
/ml605/UDP_Complete.vhd
26,10 → 26,6
use work.arp_types.all;
 
entity UDP_Complete is
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s)
);
Port (
-- UDP TX signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
48,7 → 44,6
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in udp_control_type;
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
75,11 → 70,7
------------------------------------------------------------------------------
 
COMPONENT UDP_Complete_nomac
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s)
);
Port (
PORT(
-- UDP TX signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
96,7 → 87,6
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in udp_control_type;
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
195,12 → 185,7
-- Instantiate the UDP layer
------------------------------------------------------------------------------
 
udp_block: UDP_Complete_nomac
generic map (
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT
)
PORT MAP (
udp_block: UDP_Complete_nomac PORT MAP (
-- UDP TX signals
udp_tx_start => udp_tx_start,
udp_txi => udp_txi,
220,7 → 205,7
-- status signals
arp_pkt_count => arp_pkt_count,
ip_pkt_count => ip_pkt_count,
control => control,
 
-- MAC Transmitter
mac_tx_tready => mac_tx_tready_int,
mac_tx_tvalid => mac_tx_tvalid,
/ml605/udp_constraints.ucf
21,13 → 21,7
NET "display[7]" LOC = AD24;
 
NET PBTX_LED LOC = AD21;
NET UDP_RX LOC = AH27;
NET UDP_START LOC = AH28;
NET TX_RSLT_0 LOC = AE21;
NET TX_RSLT_1 LOC = AP24;
 
 
 
#### Module Push_Buttons_4Bit constraints
NET PBTX LOC = H17;
NET reset_leds LOC = G26;
/ipv4_types.vhd
6,7 → 6,6
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.axi.all;
use work.arp_types.all;
 
package ipv4_types is
 
60,9 → 59,6
data : axi_in_type; -- rx axi bus
end record;
type ip_control_type is record
arp_controls : arp_control_type;
end record;
 
------------
-- UDP TX --
112,9 → 108,5
port_num : STD_LOGIC_VECTOR (15 downto 0);
end record;
type udp_control_type is record
ip_controls : ip_control_type;
end record;
 
end ipv4_types;
/IPv4_TX.vhd
251,12 → 251,12
 
when WAIT_MAC =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
set_mac_lku_req <= CLR; -- clear the request - will have been latched in the ARP layer
if arp_req_rslt.got_mac = '1' then
-- save the MAC we got back from the ARP lookup
tx_mac_value <= arp_req_rslt.mac;
set_tx_mac <= '1';
set_chn_reqd <= SET;
set_mac_lku_req <= CLR;
-- check for optimise when already have the channel
if mac_tx_granted = '1' then
-- ready to send data
/IP_complete_nomac.vhd
27,10 → 27,6
use work.arp_types.all;
 
entity IP_complete_nomac is
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s)
);
Port (
-- IP Layer signals
ip_tx_start : in std_logic;
45,7 → 41,6
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in ip_control_type;
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
101,11 → 96,7
END COMPONENT;
COMPONENT arp
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s)
);
Port (
PORT(
-- lookup request signals
arp_req_req : in arp_req_req_type;
arp_req_rslt : out arp_req_rslt_type;
126,10 → 117,9
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in STD_LOGIC_VECTOR (47 downto 0);
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
control : in arp_control_type;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
req_count : out STD_LOGIC_VECTOR(7 downto 0) -- count of arp pkts received
);
);
END COMPONENT;
COMPONENT tx_arbitrator
236,11 → 226,7
-- Instantiate the ARP layer
------------------------------------------------------------------------------
arp_layer : arp
generic map (
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT
)
Port map(
Port map(
-- request signals
arp_req_req => arp_req_req_int,
arp_req_rslt => arp_req_rslt_int,
262,7 → 248,6
-- system signals
our_mac_address => our_mac_address,
our_ip_address => our_ip_address,
control => control.arp_controls,
req_count => arp_pkt_count
);
 
/UDP_Complete_nomac.vhd
27,10 → 27,6
use work.arp_types.all;
 
entity UDP_Complete_nomac is
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s)
);
Port (
-- UDP TX signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
48,7 → 44,6
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in udp_control_type;
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
114,10 → 109,6
------------------------------------------------------------------------------
 
component IP_complete_nomac
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s)
);
Port (
-- IP Layer signals
ip_tx_start : in std_logic;
132,7 → 123,6
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in ip_control_type;
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
167,8 → 157,7
ip_rx_hdr <= ip_rx_int.hdr;
 
-- Instantiate the UDP TX block
udp_tx_block: UDP_TX
PORT MAP (
udp_tx_block: UDP_TX PORT MAP (
-- UDP Layer signals
udp_tx_start => udp_tx_start,
udp_txi => udp_txi,
200,12 → 189,8
------------------------------------------------------------------------------
-- Instantiate the IP layer
------------------------------------------------------------------------------
IP_block : IP_complete_nomac
generic map (
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT
)
PORT MAP (
IP_block : IP_complete_nomac PORT MAP
(
-- IP interface
ip_tx_start => ip_tx_start_int,
ip_tx => ip_tx_int,
219,7 → 204,6
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
control => control.ip_controls,
-- status signals
arp_pkt_count => arp_pkt_count,
ip_pkt_count => ip_pkt_count,
/UDP_TX.vhd
43,7 → 43,7
end UDP_TX;
 
architecture Behavioral of UDP_TX is
type tx_state_type is (IDLE, PAUSE, SEND_UDP_HDR, SEND_USER_DATA);
type tx_state_type is (IDLE, SEND_UDP_HDR, SEND_USER_DATA);
type count_mode_type is (RST, INCR, HOLD);
type settable_cnt_type is (RST, SET, INCR, HOLD);
110,12 → 110,8
ip_tx.hdr.protocol <= x"11"; -- UDP protocol
ip_tx.hdr.data_length <= total_length;
ip_tx.hdr.dst_ip_addr <= udp_txi.hdr.dst_ip_addr;
if udp_tx_start = '1' and ip_tx_start_reg = '0' then
udp_tx_result <= UDPTX_RESULT_NONE; -- kill the result until have started the IP layer
else
udp_tx_result <= tx_result_reg;
end if;
udp_tx_result <= tx_result_reg;
 
case udp_tx_state is
when SEND_USER_DATA =>
ip_tx.data.data_out <= udp_txi.data.data_out;
145,7 → 141,6
set_tx_result <= '0';
set_ip_tx_start <= HOLD;
tx_count_val <= (others => '0');
udp_tx_data_out_ready <= '0';
-- set temp signals
total_length <= std_logic_vector(unsigned(udp_txi.hdr.data_length) + 8); -- total length = user data length + header length (bytes)
166,25 → 161,14
next_tx_result <= UDPTX_RESULT_SENDING;
set_ip_tx_start <= SET;
set_tx_result <= '1';
next_tx_state <= PAUSE;
next_tx_state <= SEND_UDP_HDR;
set_tx_state <= '1';
end if;
end if;
 
when PAUSE =>
-- delay one clock for IP layer to respond to ip_tx_start and remove any tx error result
next_tx_state <= SEND_UDP_HDR;
set_tx_state <= '1';
when SEND_UDP_HDR =>
udp_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
if ip_tx_result = IPTX_RESULT_ERR then
set_ip_tx_start <= CLR;
next_tx_result <= UDPTX_RESULT_ERR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
elsif ip_tx_data_out_ready = '1' then
if ip_tx_data_out_ready = '1' then
if tx_count = x"0007" then
tx_count_val <= x"0001";
tx_count_mode <= SET;
/arp_types.vhd
25,9 → 25,5
got_err : std_logic; -- indicates that we got an error (prob a timeout)
end record;
 
type arp_control_type is
record
clear_cache : std_logic;
end record;
end arp_types;

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