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URL https://opencores.org/ocsvn/usb2uart/usb2uart/trunk

Subversion Repositories usb2uart

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /usb2uart
    from Rev 7 to Rev 8
    ↔ Reverse comparison
  •

Rev 7 → Rev 8

/trunk/verify/agents/usb/usb_agent.v
3301,7 → 3301,7
input start_bit;
input data_in;
input data_in_n;
output recv_bit_count;
output [31:0] recv_bit_count;
output bit_stuff_err;
output ser_data_out;
output [7:0] par_data_out;
/trunk/verify/log/run.log
53,40 → 53,6
# Loading work.uart_agent
# Loading work.test_control
# Loading work.bit_register
# ** Warning: (vsim-3017) ../tb/tb.v(211): [TFMPC] - Too few port connections. Expected 85, found 84.
#
# Region: /tb/dut
# ** Warning: (vsim-3015) ../tb/tb.v(211): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'ep1_din'. The port definition is at: ../../rtl/core/core.v(84).
#
# Region: /tb/dut
# ** Warning: (vsim-3015) ../tb/tb.v(211): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'ep2_dout'. The port definition is at: ../../rtl/core/core.v(97).
#
# Region: /tb/dut
# ** Warning: (vsim-3015) ../tb/tb.v(211): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'ep3_din'. The port definition is at: ../../rtl/core/core.v(104).
#
# Region: /tb/dut
# ** Warning: (vsim-3015) ../tb/tb.v(211): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'ep4_dout'. The port definition is at: ../../rtl/core/core.v(117).
#
# Region: /tb/dut
# ** Warning: (vsim-3015) ../tb/tb.v(211): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'ep5_din'. The port definition is at: ../../rtl/core/core.v(124).
#
# Region: /tb/dut
# ** Warning: (vsim-3722) ../tb/tb.v(211): [TFMPC] - Missing connection for port 'usb_rst'.
#
# ** Warning: (vsim-3017) ../../rtl/uart_core/uart_core.v(236): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb/dut/u_uart_core/u_rxfifo
# ** Warning: (vsim-3722) ../../rtl/uart_core/uart_core.v(236): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart_core/uart_core.v(236): [TFMPC] - Missing connection for port 'aempty'.
#
# ** Warning: (vsim-3017) ../../rtl/uart_core/uart_core.v(252): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb/dut/u_uart_core/u_txfifo
# ** Warning: (vsim-3722) ../../rtl/uart_core/uart_core.v(252): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart_core/uart_core.v(252): [TFMPC] - Missing connection for port 'aempty'.
#
# do modelsim.do
# 1200: USB Reset -----
# 5418: Set Address = 1 -----
5742,5 → 5708,5
# Number of timeout error is : 0
# Number of error is : 0
# -----------------------------------------------------------------
# ** Note: $finish : ../tb/tb.v(246)
# ** Note: $finish : ../tb/tb.v(247)
# Time: 4225639240 ps Iteration: 0 Instance: /tb
/trunk/verify/tb/tb.v
96,6 → 96,7
 
// USB Misc
.phy_tx_mode(1'b1),
.usb_rst(),
 
// Interrupts
.dropped_frame(),
120,9 → 121,9
.ep1_we( ),
.ep1_full( 1'b0 ),
// End point 1 'IN' FIFO i/f
.ep1_din( ep1_us_din ),
.ep1_re( ep1_us_re ),
.ep1_empty( ep1_us_empty ),
.ep1_din( 8'h0 ),
.ep1_re( ),
.ep1_empty( 1'b0 ),
.ep1_bf_en( 1'b0 ),
.ep1_bf_size( 7'h0 ),
 
129,9 → 130,9
// End point 2 configuration
.ep2_cfg( `ISO | `OUT | 14'd0256 ),
// End point 2 'OUT' FIFO i/f
.ep2_dout( ep2_us_dout ),
.ep2_we( ep2_us_we ),
.ep2_full( ep2_us_full ),
.ep2_dout( ),
.ep2_we( ),
.ep2_full( 1'b0 ),
// End point 2 'IN' FIFO i/f
.ep2_din( 8'h0 ),
.ep2_re( ),
146,9 → 147,9
.ep3_we( ),
.ep3_full( 1'b0 ),
// End point 3 'IN' FIFO i/f
.ep3_din( ep3_us_din ),
.ep3_re( ep3_us_re ),
.ep3_empty( ep3_us_empty ),
.ep3_din( 8'h0 ),
.ep3_re( ),
.ep3_empty( 1'b0 ),
.ep3_bf_en( 1'b0 ),
.ep3_bf_size( 7'h0 ),
 
155,9 → 156,9
// End point 4 configuration
.ep4_cfg( `BULK | `OUT | 14'd064 ),
// End point 4 'OUT' FIFO i/f
.ep4_dout( ep4_us_dout ),
.ep4_we( ep4_us_we ),
.ep4_full( ep4_us_full ),
.ep4_dout( ),
.ep4_we( ),
.ep4_full( 1'b0 ),
// End point 4 'IN' FIFO i/f
.ep4_din( 8'h0 ),
.ep4_re( ),
172,9 → 173,9
.ep5_we( ),
.ep5_full( 1'b0 ),
// End point 5 'IN' FIFO i/f
.ep5_din( ep5_us_din ),
.ep5_re( ep5_us_re ),
.ep5_empty( ep5_us_empty ),
.ep5_din( 8'h0 ),
.ep5_re( ),
.ep5_empty( 1'b0 ),
.ep5_bf_en( 1'b0 ),
.ep5_bf_size( 7'h0 ),
 

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