OpenCores
URL https://opencores.org/ocsvn/v6502/v6502/trunk

Subversion Repositories v6502

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /v6502
    from Rev 5 to Rev 6
    ↔ Reverse comparison
  •

Rev 5 → Rev 6

/trunk/mcpla.vhd
620,33 → 620,33
------------------------------------
-- RELATIVE --
------------------------------------
constant BRA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10000000000"; -- 0x80 BRA
constant BRA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10000000001"; -- 0x80 BRA
constant BRA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10000000010"; -- 0x80 BRA
constant BCC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10010000000"; -- 0x90 BCC
constant BCC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10010000001"; -- 0x90 BCC
constant BCC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10010000010"; -- 0x90 BCC
constant BCS_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10110000000"; -- 0xB0 BCS
constant BCS_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10110000001"; -- 0xB0 BCS
constant BCS_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10110000010"; -- 0xB0 BCS
constant BEQ_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11110000000"; -- 0xF0 BEQ
constant BEQ_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11110000001"; -- 0xF0 BEQ
constant BEQ_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11110000010"; -- 0xF0 BEQ
constant BNE_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11010000000"; -- 0xD0 BNE
constant BNE_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11010000001"; -- 0xD0 BNE
constant BNE_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11010000010"; -- 0xD0 BNE
constant BPL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00010000000"; -- 0x10 BPL
constant BPL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00010000001"; -- 0x10 BPL
constant BPL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00010000010"; -- 0x10 BPL
constant BMI_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00110000000"; -- 0x30 BMI
constant BMI_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00110000001"; -- 0x30 BMI
constant BMI_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00110000010"; -- 0x30 BMI
constant BVC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01010000000"; -- 0x50 BVC
constant BVC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01010000001"; -- 0x50 BVC
constant BVC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01010000010"; -- 0x50 BVC
constant BVS_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01110000000"; -- 0x70 BVS
constant BVS_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01110000001"; -- 0x70 BVS
constant BVS_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01110000010"; -- 0x70 BVS
constant BRA_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10000000000"; -- 0x80 BRA
constant BRA_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10000000001"; -- 0x80 BRA
constant BRA_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10000000010"; -- 0x80 BRA
constant BCC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10010000000"; -- 0x90 BCC
constant BCC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10010000001"; -- 0x90 BCC
constant BCC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10010000010"; -- 0x90 BCC
constant BCS_OP0: STD_LOGIC_VECTOR(10 downto 0) := "10110000000"; -- 0xB0 BCS
constant BCS_OP1: STD_LOGIC_VECTOR(10 downto 0) := "10110000001"; -- 0xB0 BCS
constant BCS_OP2: STD_LOGIC_VECTOR(10 downto 0) := "10110000010"; -- 0xB0 BCS
constant BEQ_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11110000000"; -- 0xF0 BEQ
constant BEQ_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11110000001"; -- 0xF0 BEQ
constant BEQ_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11110000010"; -- 0xF0 BEQ
constant BNE_OP0: STD_LOGIC_VECTOR(10 downto 0) := "11010000000"; -- 0xD0 BNE
constant BNE_OP1: STD_LOGIC_VECTOR(10 downto 0) := "11010000001"; -- 0xD0 BNE
constant BNE_OP2: STD_LOGIC_VECTOR(10 downto 0) := "11010000010"; -- 0xD0 BNE
constant BPL_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00010000000"; -- 0x10 BPL
constant BPL_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00010000001"; -- 0x10 BPL
constant BPL_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00010000010"; -- 0x10 BPL
constant BMI_OP0: STD_LOGIC_VECTOR(10 downto 0) := "00110000000"; -- 0x30 BMI
constant BMI_OP1: STD_LOGIC_VECTOR(10 downto 0) := "00110000001"; -- 0x30 BMI
constant BMI_OP2: STD_LOGIC_VECTOR(10 downto 0) := "00110000010"; -- 0x30 BMI
constant BVC_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01010000000"; -- 0x50 BVC
constant BVC_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01010000001"; -- 0x50 BVC
constant BVC_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01010000010"; -- 0x50 BVC
constant BVS_OP0: STD_LOGIC_VECTOR(10 downto 0) := "01110000000"; -- 0x70 BVS
constant BVS_OP1: STD_LOGIC_VECTOR(10 downto 0) := "01110000001"; -- 0x70 BVS
constant BVS_OP2: STD_LOGIC_VECTOR(10 downto 0) := "01110000010"; -- 0x70 BVS
-- ALU microcode
constant NOP_A: STD_LOGIC_VECTOR(4 downto 0) := "00000"; -- ALU no operation
697,18 → 697,20
-- PR microcode
constant NOP_P: STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- PR no operation
constant PLD_P: STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- PR load
constant FLD_P: STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- NVZC load
constant SEC_P: STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- 1 => C
constant CLC_P: STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- 0 => C
constant SEI_P: STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- 1 => I
constant CLI_P: STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- 0 => I
constant SED_P: STD_LOGIC_VECTOR(3 downto 0) := "0111"; -- 1 => D
constant CLD_P: STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- 0 => D
constant CLV_P: STD_LOGIC_VECTOR(3 downto 0) := "1010"; -- 0 => V
constant AUC_P: STD_LOGIC_VECTOR(3 downto 0) := "1011"; -- auc => ACR
constant HAC_P: STD_LOGIC_VECTOR(3 downto 0) := "1100"; -- hold ACR
constant SID_P: STD_LOGIC_VECTOR(3 downto 0) := "1101"; -- 1 => I/D
constant LDZ_P: STD_LOGIC_VECTOR(3 downto 0) := "1110"; -- Z load
constant FLD_P: STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- NZ load
constant FLC_P: STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- NZC load
constant FLV_P: STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- NVZC load
constant SEC_P: STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- 1 => C
constant CLC_P: STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- 0 => C
constant SEI_P: STD_LOGIC_VECTOR(3 downto 0) := "0111"; -- 1 => I
constant CLI_P: STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- 0 => I
constant SED_P: STD_LOGIC_VECTOR(3 downto 0) := "1001"; -- 1 => D
constant CLD_P: STD_LOGIC_VECTOR(3 downto 0) := "1010"; -- 0 => D
constant CLV_P: STD_LOGIC_VECTOR(3 downto 0) := "1011"; -- 0 => V
constant AUC_P: STD_LOGIC_VECTOR(3 downto 0) := "1100"; -- auc => ACR
constant HAC_P: STD_LOGIC_VECTOR(3 downto 0) := "1101"; -- hold ACR
constant SID_P: STD_LOGIC_VECTOR(3 downto 0) := "1110"; -- 1 => I/D
constant LDZ_P: STD_LOGIC_VECTOR(3 downto 0) := "1111"; -- Z load
 
-- register operation microcode REGOP
constant NOP_R: STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- no operation
935,16 → 937,16
when RTS_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & NOP_R & EXT_O; -- PC+1; PC->MEM; EI
 
-- ASL (A)
when ASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & SHL_A & ALD_R & ARD_O; -- A SHIFT LEFT; EI
when ASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLC_P & SHL_A & ALD_R & ARD_O; -- A SHIFT LEFT; EI
 
-- LSR (A)
when LSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & SHR_A & ALD_R & ARD_O; -- A SHIFT RIGHT; EI
when LSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLC_P & SHR_A & ALD_R & ARD_O; -- A SHIFT RIGHT; EI
-- ROL (A)
when ROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & ROL_A & ALD_R & ARD_O; -- A ROTATE LEFT; EI
when ROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLC_P & ROL_A & ALD_R & ARD_O; -- A ROTATE LEFT; EI
 
-- ROR (A)
when ROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & ROR_A & ALD_R & ARD_O; -- A ROTATE RIGHT; EI
when ROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLC_P & ROR_A & ALD_R & ARD_O; -- A ROTATE RIGHT; EI
 
-- XYX
when XYX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & XRD_O; -- X->O;
983,21 → 985,21
when IMLDY_OP0 => q <= ORD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & NOP_A & YLD_R & EXT_O; -- MEM->Y; PC +1; EI
 
-- ADC #xx (immediate)
when IMADC_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & SUM_A & ALD_R & ARD_O; -- A=A+EXT; PC +1; EI
when IMADC_OP1 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
when IMADC_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLV_P & SUM_A & ALD_R & ARD_O; -- A=A+EXT; PC +1; EI
when IMADC_OP1 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
 
-- SBC #xx (immediate)
when IMSBC_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & SUB_A & ALD_R & ARD_O; -- A=A-EXT; PC +1; EI
when IMSBC_OP1 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAA); PC +1; EI
when IMSBC_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLV_P & SUB_A & ALD_R & ARD_O; -- A=A-EXT; PC +1; EI
when IMSBC_OP1 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAA); PC +1; EI
 
-- CMP #xx (immediate)
when IMCMP_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & CMP_A & NOP_R & ARD_O; -- A-MEM; PC +1; EI
when IMCMP_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-MEM; PC +1; EI
 
-- CPX #xx (immediate)
when IMCPX_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & CMP_A & NOP_R & XRD_O; -- X-MEM; PC +1; EI
when IMCPX_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLC_P & CMP_A & NOP_R & XRD_O; -- X-MEM; PC +1; EI
 
-- CPY #xx (immediate)
when IMCPY_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & CMP_A & NOP_R & YRD_O; -- Y-MEM; PC +1; EI
when IMCPY_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLC_P & CMP_A & NOP_R & YRD_O; -- Y-MEM; PC +1; EI
 
-- AND #xx (immediate)
when IMAND_OP0 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & INC_PC & NOP_M & FLD_P & AND_A & ALD_R & ARD_O; -- A AND MEM -> A; PC +1;
1045,25 → 1047,25
 
-- ADC $xx (zero page)
when ZPADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
when ZPADC_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUM_A & ALD_R & ARD_O; -- A=A+MEM; EI
when ZPADC_OP2 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
when ZPADC_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALD_R & ARD_O; -- A=A+MEM; EI
when ZPADC_OP2 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
 
-- SBC $xx (zero page)
when ZPSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
when ZPSBC_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUB_A & ALD_R & ARD_O; -- A=A-MEM; EI
when ZPSBC_OP2 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAS); PC +1; EI
when ZPSBC_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALD_R & ARD_O; -- A=A-MEM; EI
when ZPSBC_OP2 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAS); PC +1; EI
 
-- CMP $xx (zeropage)
when ZPCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
when ZPCMP_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & ARD_O; -- A-MEM; EI
when ZPCMP_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-MEM; EI
 
-- CPX $xx (zeropage)
when ZPCPX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
when ZPCPX_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & XRD_O; -- X-MEM; EI
when ZPCPX_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & XRD_O; -- X-MEM; EI
 
-- CPY $xx (zeropage)
when ZPCPY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
when ZPCPY_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & YRD_O; -- Y-MEM; EI
when ZPCPY_OP1 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & YRD_O; -- Y-MEM; EI
 
-- AND $xx (zeropage)
when ZPAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1084,25 → 1086,25
-- ASL $xx (zero page)
when ZPASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
when ZPASL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
when ZPASL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SHL_A & OLD_R & ORD_O; -- O SHIFT LEFT;
when ZPASL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & SHL_A & OLD_R & ORD_O; -- O SHIFT LEFT;
when ZPASL_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
 
-- LSR $xx (zero page)
when ZPLSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
when ZPLSR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
when ZPLSR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SHR_A & OLD_R & ORD_O; -- O SHIFT RIGHT;
when ZPLSR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & SHR_A & OLD_R & ORD_O; -- O SHIFT RIGHT;
when ZPLSR_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
 
-- ROL $xx (zero page)
when ZPROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
when ZPROL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
when ZPROL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & ROL_A & OLD_R & ORD_O; -- O ROTATE LEFT;
when ZPROL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & ROL_A & OLD_R & ORD_O; -- O ROTATE LEFT;
when ZPROL_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
 
-- ROR $xx (zero page)
when ZPROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
when ZPROR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1; EI
when ZPROR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & ROR_A & OLD_R & ORD_O; -- O ROTATE RIGHT;
when ZPROR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & ROR_A & OLD_R & ORD_O; -- O ROTATE RIGHT;
when ZPROR_OP3 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1; EI
 
-- INC $xx (zero page)
1162,19 → 1164,19
-- ADC $xx,X (zero page indexed)
when ZXADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP; PC+1
when ZXADC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
when ZXADC_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUM_A & ALD_R & ARD_O; -- A=A+MEM; EI
when ZXADC_OP3 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); EI
when ZXADC_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALD_R & ARD_O; -- A=A+MEM; EI
when ZXADC_OP3 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); EI
 
-- SBC $xx,X (zero page indexed)
when ZXSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP; PC+1
when ZXSBC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
when ZXSBC_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUB_A & ALD_R & ARD_O; -- A=A-MEM; EI
when ZXSBC_OP3 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAS); EI
when ZXSBC_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALD_R & ARD_O; -- A=A-MEM; EI
when ZXSBC_OP3 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAS); EI
 
-- CMP $xx,X (zero page indexed)
when ZXCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP; PC+1
when ZXCMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP-+=X; PC+1;
when ZXCMP_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & ARD_O; -- A-MEM; EI
when ZXCMP_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-MEM; EI
 
-- AND $xx,X (zero page indexed)
when ZXAND_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP; PC+1
1195,7 → 1197,7
when ZXASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
when ZXASL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X PC+1;
when ZXASL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O;
when ZXASL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SHL_A & OLD_R & ORD_O; -- O SHIFT LEFT;
when ZXASL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & SHL_A & OLD_R & ORD_O; -- O SHIFT LEFT;
when ZXASL_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
 
-- LSR $xx,X (zero page indexed)
1202,7 → 1204,7
when ZXLSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP
when ZXLSR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
when ZXLSR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O;
when ZXLSR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SHR_A & OLD_R & ORD_O; -- O SHIFT RIGHT;
when ZXLSR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & SHR_A & OLD_R & ORD_O; -- O SHIFT RIGHT;
when ZXLSR_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
 
-- ROL $xx,X (zero page indexed)
1209,7 → 1211,7
when ZXROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
when ZXROL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
when ZXROL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O;
when ZXROL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & ROL_A & OLD_R & ORD_O; -- O ROTATE LEFT;
when ZXROL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & ROL_A & OLD_R & ORD_O; -- O ROTATE LEFT;
when ZXROL_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
 
-- ROR $xx,X (zero page indexed)
1216,7 → 1218,7
when ZXROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & OLD_R & EXT_O; -- ZP->MP;
when ZXROR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & SWC_A & NOP_R & XRD_O; -- MP+=X; PC+1;
when ZXROR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O;
when ZXROR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & ROR_A & OLD_R & ORD_O; -- O ROTATE RIGHT;
when ZXROR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & ROR_A & OLD_R & ORD_O; -- O ROTATE RIGHT;
when ZXROR_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
 
-- INC $xx,X (zero page indexed)
1282,8 → 1284,8
when IYADC_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
when IYADC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
when IYADC_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP + CARRY
when IYADC_OP4 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUM_A & ALD_R & ARD_O; -- MP->MEM; A=A+EXT
when IYADC_OP5 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
when IYADC_OP4 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALD_R & ARD_O; -- MP->MEM; A=A+EXT
when IYADC_OP5 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
 
-- SBC ($xx),Y (zeropage - indirect - indexed)
when IYSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1290,15 → 1292,15
when IYSBC_OP1 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
when IYSBC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
when IYSBC_OP3 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP + CARRY
when IYSBC_OP4 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUB_A & ALD_R & ARD_O; -- MP->MEM; A=A-EXT
when IYSBC_OP5 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAS_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAS); PC +1; EI
when IYSBC_OP4 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALD_R & ARD_O; -- MP->MEM; A=A-EXT
when IYSBC_OP5 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAS_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAS); PC +1; EI
 
-- CMP ($xx),Y (zeropage - indirect - indexed)
when IYCMP_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
when IYCMP_OP1 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & INC_PC & INC_M & AUC_P & SWC_A & OLD_R & YRD_O; -- MP->MEM; MEM+Y->O; (LSB POINTER)
when IYCMP_OP2 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & HAC_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; MEM->MP; (MSB POINTER)
when IYCMP_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM MP_MSB+CARRY, EI
when IYCMP_OP4 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM; EI
when IYCMP_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLC_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM MP_MSB+CARRY, EI
when IYCMP_OP4 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM; EI
 
-- AND ($xx),Y (zeropage - indirect - indexed)
when IYAND_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & NOP_PC & ZPL_M & NOP_P & NOP_A & NOP_R & EXT_O; -- ZP->MP; PC+1
1358,21 → 1360,21
when IXADC_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
when IXADC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
when IXADC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
when IXADC_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUM_A & ALD_R & ARD_O; -- MP->MEM; A=A XOR MEM; EI=1
when IXADC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
when IXADC_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALD_R & ARD_O; -- MP->MEM; A=A XOR MEM; EI=1
when IXADC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
 
-- SBC ($xx,X) (zero page - indexed - indirect)
when IXSBC_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
when IXSBC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
when IXSBC_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
when IXSBC_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUB_A & ALD_R & ARD_O; -- MP->MEM; A=A XOR MEM; EI=1
when IXSBC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAS_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
when IXSBC_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALD_R & ARD_O; -- MP->MEM; A=A XOR MEM; EI=1
when IXSBC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAS_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
 
-- CMP ($xx,X) (zero page - indexed - indirect)
when IXCMP_OP0 => q <= EXT_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ZPL_M & NOP_P & SWC_A & NOP_R & XRD_O; -- ZP+X->MP; PC+1
when IXCMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & INC_M & NOP_P & NOP_A & OLD_R & EXT_O; -- O<=LSB; MP+=1
when IXCMP_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ALL_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP<=MSB & LSB (O)
when IXCMP_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A=A XOR MEM; EI=1
when IXCMP_OP3 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A=A XOR MEM; EI=1
 
-- JMP ($xxxx,X) (absolute indexed - indirect)
when IXJMP_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1445,29 → 1447,29
-- ADC $xxxx (absolute)
when ABADC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
when ABADC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
when ABADC_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUM_A & ALD_R & ARD_O; -- A=A+EXT; EI
when ABADC_OP3 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
when ABADC_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALD_R & ARD_O; -- A=A+EXT; EI
when ABADC_OP3 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
 
-- SBC $xxxx (absolute)
when ABSBC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
when ABSBC_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
when ABSBC_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUB_A & ALD_R & ARD_O; -- A=A-EXT; EI
when ABSBC_OP3 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAA); PC +1; EI
when ABSBC_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALD_R & ARD_O; -- A=A-EXT; EI
when ABSBC_OP3 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAA); PC +1; EI
 
-- CMP $xxxx (absolute)
when ABCMP_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
when ABCMP_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
when ABCMP_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & ARD_O; -- A-EXT; EI
when ABCMP_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- A-EXT; EI
 
-- CPX $xxxx (absolute)
when ABCPX_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
when ABCPX_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
when ABCPX_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & XRD_O; -- X-EXT; EI
when ABCPX_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & XRD_O; -- X-EXT; EI
 
-- CPY $xxxx (absolute)
when ABCPY_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
when ABCPY_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
when ABCPY_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & YRD_O; -- Y-EXT; EI
when ABCPY_OP2 => q <= EXT_D &'0'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & YRD_O; -- Y-EXT; EI
 
-- ORA $xxxx (absolute)
when ABORA_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
1488,7 → 1490,7
when ABASL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
when ABASL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
when ABASL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
when ABASL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SHL_A & OLD_R & ORD_O; -- O SHIFT LEFT;
when ABASL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & SHL_A & OLD_R & ORD_O; -- O SHIFT LEFT;
when ABASL_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
 
-- LSR $xxxx (absolute)
1495,7 → 1497,7
when ABLSR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
when ABLSR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
when ABLSR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
when ABLSR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SHR_A & OLD_R & ORD_O; -- O SHIFT RIGHT;
when ABLSR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & SHR_A & OLD_R & ORD_O; -- O SHIFT RIGHT;
when ABLSR_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
 
-- ROL $xxxx (absolute)
1502,7 → 1504,7
when ABROL_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
when ABROL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
when ABROL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
when ABROL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & ROL_A & OLD_R & ORD_O; -- O ROTATE LEFT;
when ABROL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & ROL_A & OLD_R & ORD_O; -- O ROTATE LEFT;
when ABROL_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
 
-- ROR $xxxx (absolute)
1509,7 → 1511,7
when ABROR_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & LSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- LSB->MP; PC+1
when ABROR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & MSB_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MSB->MP; PC+1
when ABROR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; PC+1
when ABROR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & ROR_A & OLD_R & ORD_O; -- O ROTATE RIGHT;
when ABROR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & ROR_A & OLD_R & ORD_O; -- O ROTATE RIGHT;
when ABROR_OP4 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; PC+1
 
-- INC $xxxx (absolute)
1590,21 → 1592,21
when AXADC_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
when AXADC_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
when AXADC_OP2 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; A=A+EXT; MP_MSB+CARRY, EI
when AXADC_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUM_A & ALD_R & ARD_O; -- MP->MEM; A=A+EXT
when AXADC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
when AXADC_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALD_R & ARD_O; -- MP->MEM; A=A+EXT
when AXADC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
 
-- SBC $xxxx,X (absolute indexed)
when AXSBC_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
when AXSBC_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
when AXSBC_OP2 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; A=A-EXT; MP_MSB+CARRY, EI
when AXSBC_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUB_A & ALD_R & ARD_O; -- MP->MEM; A=A-EXT
when AXSBC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAS); PC +1; EI
when AXSBC_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALD_R & ARD_O; -- MP->MEM; A=A-EXT
when AXSBC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAS); PC +1; EI
 
-- CMP $xxxx,X (absolute indexed)
when AXCMP_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
when AXCMP_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
when AXCMP_OP2 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM MP_MSB+CARRY, EI
when AXCMP_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM; EI
when AXCMP_OP2 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLC_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM MP_MSB+CARRY, EI
when AXCMP_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM; EI
 
-- INC $xxxx,X (absolute indexed)
when AXINC_OP0 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
1627,7 → 1629,7
when AXASL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
when AXASL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
when AXASL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
when AXASL_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SHL_A & OLD_R & ORD_O; -- O SHIFT LEFT
when AXASL_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & SHL_A & OLD_R & ORD_O; -- O SHIFT LEFT
when AXASL_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
 
-- LSR $xxxx,X (absolute indexed)
1635,7 → 1637,7
when AXLSR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
when AXLSR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
when AXLSR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
when AXLSR_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SHR_A & OLD_R & ORD_O; -- O SHIFT RIGHT
when AXLSR_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & SHR_A & OLD_R & ORD_O; -- O SHIFT RIGHT
when AXLSR_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
 
-- ROL $xxxx,X (absolute indexed)
1643,7 → 1645,7
when AXROL_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
when AXROL_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
when AXROL_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
when AXROL_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & ROL_A & OLD_R & ORD_O; -- O ROTATE LEFT
when AXROL_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & ROL_A & OLD_R & ORD_O; -- O ROTATE LEFT
when AXROL_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
 
-- ROR $xxxx,X (absolute indexed)
1651,7 → 1653,7
when AXROR_OP1 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & XRD_O; -- MEM->MP_MSB; MEM->O+X->MP_LSB; PC+1;
when AXROR_OP2 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; MP_MSB+CARRY, EI
when AXROR_OP3 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MP->MEM; MEM->O; EI
when AXROR_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & ROR_A & OLD_R & ORD_O; -- O ROTATE RIGHT
when AXROR_OP4 => q <= ORD_D &'0'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & ROR_A & OLD_R & ORD_O; -- O ROTATE RIGHT
when AXROR_OP5 => q <= ORD_D &'0'&'0'&'0'&'1'& WRE &'0'& ADMP & NOP_PC & NOP_M & NOP_P & NOP_A & NOP_R & ORD_O; -- MP->MEM; O->MEM; EI
 
-- AND $xxxx,X (absolute indexed)
1703,21 → 1705,21
when AYADC_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
when AYADC_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
when AYADC_OP2 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; A=A+EXT; MP_MSB+CARRY, EI
when AYADC_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUM_A & ALD_R & ARD_O; -- MP->MEM; A=A+EXT
when AYADC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
when AYADC_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUM_A & ALD_R & ARD_O; -- MP->MEM; A=A+EXT
when AYADC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAA_A & ALD_R & ARD_O; -- A=A+BCD ADJ (DAA); PC +1; EI
 
-- SBC $xxxx,Y (absolute indexed)
when AYSBC_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
when AYSBC_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
when AYSBC_OP2 => q <= EXT_D &'1'&'0'&'0'&'0'& RDE &'0'& ADMP & NOP_PC & ICC_M & NOP_P & NOP_A & NOP_R & EXT_O; -- MP->MEM; A=A-EXT; MP_MSB+CARRY, EI
when AYSBC_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & SUB_A & ALD_R & ARD_O; -- MP->MEM; A=A-EXT
when AYSBC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLD_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAS); PC +1; EI
when AYSBC_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLV_P & SUB_A & ALD_R & ARD_O; -- MP->MEM; A=A-EXT
when AYSBC_OP4 => q <= BCD_D &'0'&'0'&'0'&'1'& RDE &'0'& ADPC & NOP_PC & NOP_M & FLV_P & DAS_A & ALD_R & ARD_O; -- A=A-BCD ADJ (DAS); PC +1; EI
 
-- CMP $xxxx,Y (absolute indexed)
when AYCMP_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
when AYCMP_OP1 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & ALL_M & AUC_P & SWC_A & NOP_R & YRD_O; -- MEM->MP_MSB; MEM->O+Y->MP_LSB; PC+1;
when AYCMP_OP2 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLD_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM MP_MSB+CARRY, EI
when AYCMP_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLD_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM; EI
when AYCMP_OP2 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & ICC_M & FLC_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM MP_MSB+CARRY, EI
when AYCMP_OP3 => q <= EXT_D &'1'&'0'&'0'&'1'& RDE &'0'& ADMP & NOP_PC & NOP_M & FLC_P & CMP_A & NOP_R & ARD_O; -- MP->MEM; A-MEM; EI
 
-- AND $xxxx,Y (absolute indexed)
when AYAND_OP0 => q <= ORD_D &'1'&'0'&'0'&'0'& RDE &'0'& ADPC & INC_PC & NOP_M & NOP_P & NOP_A & OLD_R & EXT_O; -- MEM->O; PC+1
/trunk/pr.vhd
36,18 → 36,20
architecture rtl of pr is
constant NOP_P: STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- PR no operation
constant PLD_P: STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- PR load
constant FLD_P: STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- NVZC load
constant SEC_P: STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- 1 => C
constant CLC_P: STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- 0 => C
constant SEI_P: STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- 1 => I
constant CLI_P: STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- 0 => I
constant SED_P: STD_LOGIC_VECTOR(3 downto 0) := "0111"; -- 1 => D
constant CLD_P: STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- 0 => D
constant CLV_P: STD_LOGIC_VECTOR(3 downto 0) := "1010"; -- 0 => V
constant AUC_P: STD_LOGIC_VECTOR(3 downto 0) := "1011"; -- auc => ACR
constant HAC_P: STD_LOGIC_VECTOR(3 downto 0) := "1100"; -- hold ACR
constant SID_P: STD_LOGIC_VECTOR(3 downto 0) := "1101"; -- 1 => I/D
constant LDZ_P: STD_LOGIC_VECTOR(3 downto 0) := "1110"; -- Z load
constant FLD_P: STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- NZ load
constant FLC_P: STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- NZC load
constant FLV_P: STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- NVZC load
constant SEC_P: STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- 1 => C
constant CLC_P: STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- 0 => C
constant SEI_P: STD_LOGIC_VECTOR(3 downto 0) := "0111"; -- 1 => I
constant CLI_P: STD_LOGIC_VECTOR(3 downto 0) := "1000"; -- 0 => I
constant SED_P: STD_LOGIC_VECTOR(3 downto 0) := "1001"; -- 1 => D
constant CLD_P: STD_LOGIC_VECTOR(3 downto 0) := "1010"; -- 0 => D
constant CLV_P: STD_LOGIC_VECTOR(3 downto 0) := "1011"; -- 0 => V
constant AUC_P: STD_LOGIC_VECTOR(3 downto 0) := "1100"; -- auc => ACR
constant HAC_P: STD_LOGIC_VECTOR(3 downto 0) := "1101"; -- hold ACR
constant SID_P: STD_LOGIC_VECTOR(3 downto 0) := "1110"; -- 1 => I/D
constant LDZ_P: STD_LOGIC_VECTOR(3 downto 0) := "1111"; -- Z load
 
signal reg: STD_LOGIC_VECTOR(7 downto 0);
signal acr: STD_LOGIC; -- carry/borrow used for effectve address calculation
66,46 → 68,50
acr <= '0';
else
case fc is
when PLD_P => reg(7 downto 6) <= din(7 downto 6); -- load NV1BDIZC
when PLD_P => reg(7 downto 6) <= din(7 downto 6); -- load NV1BDIZC
reg(5) <= '1';
reg(4 downto 0) <= din(4 downto 0);
acr <= '0';
when FLD_P => reg <= n & v & '1' & reg(4 downto 2) & z & c; -- load NVZC
when FLD_P => reg <= n & reg(6) & '1' & reg(4 downto 2) & z & reg(0); -- load NZ
acr <= '0';
when SEC_P => reg <= reg or "00000001"; -- 1 => C
when FLC_P => reg <= n & reg(6) & '1' & reg(4 downto 2) & z & c; -- load NZC
acr <= '0';
when FLV_P => reg <= n & v & '1' & reg(4 downto 2) & z & c; -- load NZCV
acr <= '0';
when SEC_P => reg <= reg or "00000001"; -- 1 => C
acr <= acr;
when CLC_P => reg <= reg and "11111110"; -- 0 => C
when CLC_P => reg <= reg and "11111110"; -- 0 => C
acr <= acr;
when CLI_P => reg <= reg and "11111011"; -- 0 => I
when CLI_P => reg <= reg and "11111011"; -- 0 => I
acr <= acr;
when SED_P => reg <= reg or "00001000"; -- 1 => D
when SED_P => reg <= reg or "00001000"; -- 1 => D
acr <= acr;
when CLD_P => reg <= reg and "11110111"; -- 0 => D
when CLD_P => reg <= reg and "11110111"; -- 0 => D
acr <= acr;
when LDZ_P => reg(1) <= z; -- z => Z
when LDZ_P => reg(1) <= z; -- z => Z
reg(7 downto 2) <= reg(7 downto 2);
reg(0) <= reg(0);
when SEI_P => reg(7 downto 5) <= reg(7 downto 5);
reg(4) <= reg(4);
reg(3) <= reg(3);
reg(2) <= '1'; -- 1 => I
reg(2) <= '1'; -- 1 => I
reg(1 downto 0) <= reg(1 downto 0);
acr <= acr;
when SID_P => reg(7 downto 5) <= reg(7 downto 5); -- set I and clear D decimal flag (used by interrupt sequence)
reg(4) <= b; -- 1 => B (if BRK)
reg(3) <= '0'; -- 0 -> D
reg(2) <= '1'; -- 1 => I
when SID_P => reg(7 downto 5) <= reg(7 downto 5); -- set I and clear D decimal flag (used by interrupt sequence)
reg(4) <= b; -- 1 => B (if BRK)
reg(3) <= '0'; -- 0 -> D
reg(2) <= '1'; -- 1 => I
reg(1 downto 0) <= reg(1 downto 0);
acr <= acr;
when CLV_P => reg <= reg and "10111111"; -- 0 => V
when CLV_P => reg <= reg and "10111111"; -- 0 => V
acr <= acr;
when AUC_P => acr <= acr_in; -- store auxiliary carry (ACR)
when AUC_P => acr <= acr_in; -- store auxiliary carry (ACR)
reg <= reg;
when HAC_P => acr <= acr; -- holds auxiliary carry (ACR)
when HAC_P => acr <= acr; -- holds auxiliary carry (ACR)
reg <= reg;
when others => reg(7) <= reg(7);
reg(6) <= i_so; -- set overflow by pin SO
reg(5 downto 0) <= reg(5 downto 0);
reg(6) <= i_so; -- set overflow by pin SO
reg(5 downto 0) <= reg(5 downto 0);
acr <= '0';
end case;
end if;
/trunk/v6502.vhd
3,9 → 3,13
-- Full RTL synchronous pipelined architecture --
-- Project by Valerio Venturi (Italy) --
-- Date: 14/04/2011 --
-- Last revision: 05/05/2011 --
-- Last revision: 19/04/2020 --
----------------------------------------------------------------------
 
-- NOTE:
-- in this version I made some changes on the pr.vhd and mcpla.vhd files because some instructions changed the V flag by mistake
 
 
library IEEE;
use IEEE.std_logic_1164.all; -- defines std_logic types
use IEEE.STD_LOGIC_unsigned.all;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.