URL
https://opencores.org/ocsvn/verilog_fixed_point_math_library/verilog_fixed_point_math_library/trunk
Subversion Repositories verilog_fixed_point_math_library
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- This comparison shows the changes necessary to convert path
/verilog_fixed_point_math_library/trunk
- from Rev 7 to Rev 8
- ↔ Reverse comparison
Rev 7 → Rev 8
/qdiv.v
41,19 → 41,26
reg [2*N+Q-3:0] reg_working_divisor; // Working copy of the divisor |
|
reg [N-1:0] reg_count; // This is obviously a lot bigger than it needs to be, as we only need |
// count to N-1+Q but, computing that number of bits requires a |
// logarithm (base 2), and I don't know how to do that in a |
// way that will work for everyone |
// count to N-1+Q but, computing that number of bits requires a |
// logarithm (base 2), and I don't know how to do that in a |
// way that will work for everyone |
|
reg reg_done; // Computation completed flag |
reg reg_sign; // The quotient's sign bit |
reg reg_overflow; // Overflow flag |
reg reg_done; // Computation completed flag |
reg reg_sign; // The quotient's sign bit |
reg reg_overflow; // Overflow flag |
|
initial reg_done = 1'b1; // Initial state is to not be doing anything |
initial reg_overflow = 1'b0; // And there should be no woverflow present |
initial reg_sign = 1'b0; // And the sign should be positive |
initial reg_done = 1'b1; // Initial state is to not be doing anything |
initial reg_overflow = 1'b0; // And there should be no woverflow present |
initial reg_sign = 1'b0; // And the sign should be positive |
|
initial reg_working_quotient = 0; |
initial reg_quotient = 0; |
initial reg_working_dividend = 0; |
initial reg_working_divisor = 0; |
initial reg_count = 0; |
|
|
assign o_quotient_out[N-2:0] = reg_working_quotient; // The division results |
assign o_quotient_out[N-2:0] = reg_quotient[N-2:0]; // The division results |
assign o_quotient_out[N-1] = reg_sign; // The sign of the quotient |
assign o_complete = reg_done; |
assign o_overflow = reg_overflow; |
62,7 → 69,7
if( reg_done && i_start ) begin // This is our startup condition |
// Need to check for a divide by zero right here, I think.... |
reg_done <= 1'b0; // We're not done |
reg_count <= N+Q-2; // Set the count |
reg_count <= N+Q-1; // Set the count |
reg_working_quotient <= 0; // Clear out the quotient register |
reg_working_dividend <= 0; // Clear out the dividend register |
reg_working_divisor <= 0; // Clear out the divisor register |
86,6 → 93,7
//stop condition |
if(reg_count == 0) begin |
reg_done <= 1'b1; // If we're done, it's time to tell the calling process |
reg_quotient <= reg_working_quotient; // Move in our working copy to the outside world |
if (reg_working_quotient[2*N+Q-3:N]>0) |
reg_overflow <= 1'b1; |
end |