URL
https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk
Subversion Repositories versatile_fifo
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/versatile_fifo
- from Rev 26 to Rev 27
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Rev 26 → Rev 27
/trunk/rtl/verilog/async_fifo_dw_simplex_top.v
0,0 → 1,74
module async_fifo_dw_simplex_top ( |
// a side |
a_d, a_wr, a_fifo_full, |
a_q, a_rd, a_fifo_empty, |
a_clk, a_rst, |
// b side |
b_d, b_wr, b_fifo_full, |
b_q, b_rd, b_fifo_empty, |
b_clk, b_rst |
); |
|
parameter data_width = 18; |
parameter addr_width = 4; |
|
// a side |
input [data_width-1:0] a_d; |
input a_wr; |
output a_fifo_full; |
output [data_width-1:0] a_q; |
input a_rd; |
output a_fifo_empty; |
input a_clk; |
input a_rst; |
|
// b side |
input [data_width-1:0] b_d; |
input b_wr; |
output b_fifo_full; |
output [data_width-1:0] b_q; |
input b_rd; |
output b_fifo_empty; |
input b_clk; |
input b_rst; |
|
// adr_gen |
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin; |
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin; |
// dpram |
wire [addr_width:1] a_dpram_adr, b_dpram_adr; |
|
adr_gen |
# ( .length(addr_width)) |
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk)); |
|
adr_gen |
# (.length(addr_width)) |
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_rst)); |
|
adr_gen |
# ( .length(addr_width)) |
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk)); |
|
adr_gen |
# (.length(addr_width)) |
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_rst)); |
|
// mux read or write adr to DPRAM |
assign a_dpram_adr = (a_wr) ? a_wadr_bin : a_radr_bin; |
assign b_dpram_adr = (b_wr) ? b_wadr_bin : b_radr_bin; |
|
vfifo_dual_port_ram_dc_dw |
# (.DATA_WIDTH(data_width), .ADDR_WIDTH(addr_width)) |
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk), |
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk)); |
|
versatile_fifo_async_cmp |
# (.ADDR_WIDTH(addr_width)) |
cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) ); |
|
versatile_fifo_async_cmp |
# (.ADDR_WIDTH(addr_width)) |
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) ); |
|
endmodule |