URL
https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk
Subversion Repositories versatile_fifo
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- This comparison shows the changes necessary to convert path
/versatile_fifo
- from Rev 31 to Rev 32
- ↔ Reverse comparison
Rev 31 → Rev 32
/trunk/rtl/verilog/versatile_fifo_dual_port_ram_sc_dw.v
27,7 → 27,7
input we_b; |
input clk; |
reg [(DATA_WIDTH-1):0] q_b; |
reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] ; |
reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] `SYN; |
always @ (posedge clk) |
begin |
q_a <= ram[adr_a]; |
/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_sw.v
22,7 → 22,7
output [(DATA_WIDTH-1):0] q_b; |
input clk_a, clk_b; |
reg [(ADDR_WIDTH-1):0] adr_b_reg; |
reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] ; |
reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] `SYN; |
always @ (posedge clk_a) |
if (we_a) |
ram[adr_a] <= d_a; |
/trunk/rtl/verilog/versatile_fifo_dual_port_ram_sc_sw.v
21,7 → 21,7
output [(DATA_WIDTH-1):0] q_b; |
input clk; |
reg [(ADDR_WIDTH-1):0] adr_b_reg; |
reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] ; |
reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] `SYN; |
always @ (posedge clk) |
if (we_a) |
ram[adr_a] <= d_a; |