URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
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- This comparison shows the changes necessary to convert path
/
- from Rev 109 to Rev 108
- ↔ Reverse comparison
Rev 109 → Rev 108
/versatile_library/trunk/rtl/verilog/versatile_library.v
6046,8 → 6046,6
parameter max_burst_width_a = 4; |
parameter max_burst_width_b = max_burst_width_a; |
parameter mode = "B3"; |
parameter memory_init = 0; |
parameter memory_file = "vl_ram.v"; |
input [data_width_a-1:0] wbsa_dat_i; |
input [addr_width_a-1:0] wbsa_adr_i; |
input [data_width_a/8-1:0] wbsa_sel_i; |
6055,7 → 6053,7
input [1:0] wbsa_bte_i; |
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i; |
output [data_width_a-1:0] wbsa_dat_o; |
output wbsa_ack_o; |
output reg wbsa_ack_o; |
output wbsa_stall_o; |
input wbsa_clk, wbsa_rst; |
|
6066,7 → 6064,7
input [1:0] wbsb_bte_i; |
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i; |
output [data_width_b-1:0] wbsb_dat_o; |
output wbsb_ack_o; |
output reg wbsb_ack_o; |
output wbsb_stall_o; |
input wbsb_clk, wbsb_rst; |
|
6102,12 → 6100,18
`undef MODULE |
assign we_b = wbsb_we_i & wbsb_ack_o; |
end else if (mode=="B4") begin : b4_inst |
`define MODULE dff |
`BASE`MODULE dffacka ( .d(wbsa_stb_i & wbsa_cyc_i), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst)); |
always @ (posedge wbsa_clk or posedge wbsa_rst) |
if (wbsa_rst) |
wbsa_ack_o <= 1'b0; |
else |
wbsa_ack_o <= wbsa_stb_i & wbsa_cyc_i; |
assign wbsa_stall_o = 1'b0; |
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i; |
`BASE`MODULE dffackb ( .d(wbsb_stb_i & wbsb_cyc_i), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst)); |
`undef MODULE |
always @ (posedge wbsb_clk or posedge wbsb_rst) |
if (wbsb_rst) |
wbsb_ack_o <= 1'b0; |
else |
wbsb_ack_o <= wbsb_stb_i & wbsb_cyc_i; |
assign wbsb_stall_o = 1'b0; |
assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i; |
end |
6114,9 → 6118,7
endgenerate |
|
`define MODULE dpram_be_2r2w |
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size), |
.b_data_width(data_width_b), .b_addr_width(addr_width_b), |
.memory_init(memory_init), .memory_file(memory_file)) |
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size)) |
`undef MODULE |
ram_i ( |
.d_a(wbsa_dat_i), |
/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
2759,8 → 2759,6
parameter max_burst_width_a = 4; |
parameter max_burst_width_b = max_burst_width_a; |
parameter mode = "B3"; |
parameter memory_init = 0; |
parameter memory_file = "vl_ram.v"; |
input [data_width_a-1:0] wbsa_dat_i; |
input [addr_width_a-1:0] wbsa_adr_i; |
input [data_width_a/8-1:0] wbsa_sel_i; |
2768,7 → 2766,7
input [1:0] wbsa_bte_i; |
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i; |
output [data_width_a-1:0] wbsa_dat_o; |
output wbsa_ack_o; |
output reg wbsa_ack_o; |
output wbsa_stall_o; |
input wbsa_clk, wbsa_rst; |
input [data_width_b-1:0] wbsb_dat_i; |
2778,7 → 2776,7
input [1:0] wbsb_bte_i; |
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i; |
output [data_width_b-1:0] wbsb_dat_o; |
output wbsb_ack_o; |
output reg wbsb_ack_o; |
output wbsb_stall_o; |
input wbsb_clk, wbsb_rst; |
wire [addr_width_a-1:0] adr_a; |
2811,17 → 2809,23
.rst(wbsb_rst)); |
assign we_b = wbsb_we_i & wbsb_ack_o; |
end else if (mode=="B4") begin : b4_inst |
vl_dff dffacka ( .d(wbsa_stb_i & wbsa_cyc_i), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst)); |
always @ (posedge wbsa_clk or posedge wbsa_rst) |
if (wbsa_rst) |
wbsa_ack_o <= 1'b0; |
else |
wbsa_ack_o <= wbsa_stb_i & wbsa_cyc_i; |
assign wbsa_stall_o = 1'b0; |
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i; |
vl_dff dffackb ( .d(wbsb_stb_i & wbsb_cyc_i), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst)); |
always @ (posedge wbsb_clk or posedge wbsb_rst) |
if (wbsb_rst) |
wbsb_ack_o <= 1'b0; |
else |
wbsb_ack_o <= wbsb_stb_i & wbsb_cyc_i; |
assign wbsb_stall_o = 1'b0; |
assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i; |
end |
endgenerate |
vl_dpram_be_2r2w # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size), |
.b_data_width(data_width_b), .b_addr_width(addr_width_b), |
.memory_init(memory_init), .memory_file(memory_file)) |
vl_dpram_be_2r2w # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size)) |
ram_i ( |
.d_a(wbsa_dat_i), |
.q_a(wbsa_dat_o), |
/versatile_library/trunk/rtl/verilog/wb.v
1134,8 → 1134,6
parameter max_burst_width_a = 4; |
parameter max_burst_width_b = max_burst_width_a; |
parameter mode = "B3"; |
parameter memory_init = 0; |
parameter memory_file = "vl_ram.v"; |
input [data_width_a-1:0] wbsa_dat_i; |
input [addr_width_a-1:0] wbsa_adr_i; |
input [data_width_a/8-1:0] wbsa_sel_i; |
1143,7 → 1141,7
input [1:0] wbsa_bte_i; |
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i; |
output [data_width_a-1:0] wbsa_dat_o; |
output wbsa_ack_o; |
output reg wbsa_ack_o; |
output wbsa_stall_o; |
input wbsa_clk, wbsa_rst; |
|
1154,7 → 1152,7
input [1:0] wbsb_bte_i; |
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i; |
output [data_width_b-1:0] wbsb_dat_o; |
output wbsb_ack_o; |
output reg wbsb_ack_o; |
output wbsb_stall_o; |
input wbsb_clk, wbsb_rst; |
|
1190,12 → 1188,18
`undef MODULE |
assign we_b = wbsb_we_i & wbsb_ack_o; |
end else if (mode=="B4") begin : b4_inst |
`define MODULE dff |
`BASE`MODULE dffacka ( .d(wbsa_stb_i & wbsa_cyc_i), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst)); |
always @ (posedge wbsa_clk or posedge wbsa_rst) |
if (wbsa_rst) |
wbsa_ack_o <= 1'b0; |
else |
wbsa_ack_o <= wbsa_stb_i & wbsa_cyc_i; |
assign wbsa_stall_o = 1'b0; |
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i; |
`BASE`MODULE dffackb ( .d(wbsb_stb_i & wbsb_cyc_i), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst)); |
`undef MODULE |
always @ (posedge wbsb_clk or posedge wbsb_rst) |
if (wbsb_rst) |
wbsb_ack_o <= 1'b0; |
else |
wbsb_ack_o <= wbsb_stb_i & wbsb_cyc_i; |
assign wbsb_stall_o = 1'b0; |
assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i; |
end |
1202,9 → 1206,7
endgenerate |
|
`define MODULE dpram_be_2r2w |
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size), |
.b_data_width(data_width_b), .b_addr_width(addr_width_b), |
.memory_init(memory_init), .memory_file(memory_file)) |
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size)) |
`undef MODULE |
ram_i ( |
.d_a(wbsa_dat_i), |
/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
2864,8 → 2864,6
parameter max_burst_width_a = 4; |
parameter max_burst_width_b = max_burst_width_a; |
parameter mode = "B3"; |
parameter memory_init = 0; |
parameter memory_file = "vl_ram.v"; |
input [data_width_a-1:0] wbsa_dat_i; |
input [addr_width_a-1:0] wbsa_adr_i; |
input [data_width_a/8-1:0] wbsa_sel_i; |
2873,7 → 2871,7
input [1:0] wbsa_bte_i; |
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i; |
output [data_width_a-1:0] wbsa_dat_o; |
output wbsa_ack_o; |
output reg wbsa_ack_o; |
output wbsa_stall_o; |
input wbsa_clk, wbsa_rst; |
input [data_width_b-1:0] wbsb_dat_i; |
2883,7 → 2881,7
input [1:0] wbsb_bte_i; |
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i; |
output [data_width_b-1:0] wbsb_dat_o; |
output wbsb_ack_o; |
output reg wbsb_ack_o; |
output wbsb_stall_o; |
input wbsb_clk, wbsb_rst; |
wire [addr_width_a-1:0] adr_a; |
2916,17 → 2914,23
.rst(wbsb_rst)); |
assign we_b = wbsb_we_i & wbsb_ack_o; |
end else if (mode=="B4") begin : b4_inst |
vl_dff dffacka ( .d(wbsa_stb_i & wbsa_cyc_i), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst)); |
always @ (posedge wbsa_clk or posedge wbsa_rst) |
if (wbsa_rst) |
wbsa_ack_o <= 1'b0; |
else |
wbsa_ack_o <= wbsa_stb_i & wbsa_cyc_i; |
assign wbsa_stall_o = 1'b0; |
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i; |
vl_dff dffackb ( .d(wbsb_stb_i & wbsb_cyc_i), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst)); |
always @ (posedge wbsb_clk or posedge wbsb_rst) |
if (wbsb_rst) |
wbsb_ack_o <= 1'b0; |
else |
wbsb_ack_o <= wbsb_stb_i & wbsb_cyc_i; |
assign wbsb_stall_o = 1'b0; |
assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i; |
end |
endgenerate |
vl_dpram_be_2r2w # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size), |
.b_data_width(data_width_b), .b_addr_width(addr_width_b), |
.memory_init(memory_init), .memory_file(memory_file)) |
vl_dpram_be_2r2w # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size)) |
ram_i ( |
.d_a(wbsa_dat_i), |
.q_a(wbsa_dat_o), |