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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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    from Rev 45 to Rev 44
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Rev 45 → Rev 44

/versatile_library/trunk/rtl/verilog/versatile_library.v
1366,34 → 1366,29
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`timescale 1ns/1ns
 
`ifdef O_DFF
`define MODULE o_dff
module `BASE`MODULE (d_i, o_pad, clk, rst);
`undef MODULE
parameter width = 1;
parameter reset_value = {width{1'b0}};
input [width-1:0] d_i;
input [width-1:0] d_i;
output [width-1:0] o_pad;
input clk, rst;
wire [width-1:0] d_i_int `SYN_KEEP;
reg [width-1:0] o_pad_int;
assign d_i_int = d_i;
genvar i;
generate
for (i=0;i<width;i=i+1) begin
always @ (posedge clk or posedge rst)
if (rst)
o_pad_int[i] <= reset_value[i];
o_pad[i] <= 1'b0;
else
o_pad_int[i] <= d_i_int[i];
assign #1 o_pad[i] = o_pad_int[i];
o_pad[i] <= d_i_int[i];
end
endgenerate
endmodule
`endif
 
`timescale 1ns/1ns
`ifdef IO_DFF_OE
`define MODULE io_dff_oe
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1426,7 → 1421,7
d_i[i] <= 1'b0;
else
d_i[i] <= io_pad[i];
assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
assign io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
end
endgenerate
endmodule
/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
576,29 → 576,23
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`timescale 1ns/1ns
module vl_o_dff (d_i, o_pad, clk, rst);
parameter width = 1;
parameter reset_value = {width{1'b0}};
input [width-1:0] d_i;
input [width-1:0] d_i;
output [width-1:0] o_pad;
input clk, rst;
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/;
reg [width-1:0] o_pad_int;
assign d_i_int = d_i;
genvar i;
generate
for (i=0;i<width;i=i+1) begin
always @ (posedge clk or posedge rst)
if (rst)
o_pad_int[i] <= reset_value[i];
o_pad[i] <= 1'b0;
else
o_pad_int[i] <= d_i_int[i];
assign #1 o_pad[i] = o_pad_int[i];
o_pad[i] <= d_i_int[i];
end
endgenerate
endmodule
`timescale 1ns/1ns
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
parameter width = 1;
input [width-1:0] d_o;
628,7 → 622,7
d_i[i] <= 1'b0;
else
d_i[i] <= io_pad[i];
assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
assign io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
end
endgenerate
endmodule
/versatile_library/trunk/rtl/verilog/io.v
39,34 → 39,29
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`timescale 1ns/1ns
 
`ifdef O_DFF
`define MODULE o_dff
module `BASE`MODULE (d_i, o_pad, clk, rst);
`undef MODULE
parameter width = 1;
parameter reset_value = {width{1'b0}};
input [width-1:0] d_i;
input [width-1:0] d_i;
output [width-1:0] o_pad;
input clk, rst;
wire [width-1:0] d_i_int `SYN_KEEP;
reg [width-1:0] o_pad_int;
assign d_i_int = d_i;
genvar i;
generate
for (i=0;i<width;i=i+1) begin
always @ (posedge clk or posedge rst)
if (rst)
o_pad_int[i] <= reset_value[i];
o_pad[i] <= 1'b0;
else
o_pad_int[i] <= d_i_int[i];
assign #1 o_pad[i] = o_pad_int[i];
o_pad[i] <= d_i_int[i];
end
endgenerate
endmodule
`endif
 
`timescale 1ns/1ns
`ifdef IO_DFF_OE
`define MODULE io_dff_oe
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
99,7 → 94,7
d_i[i] <= 1'b0;
else
d_i[i] <= io_pad[i];
assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
assign io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
end
endgenerate
endmodule
/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
684,29 → 684,23
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`timescale 1ns/1ns
module vl_o_dff (d_i, o_pad, clk, rst);
parameter width = 1;
parameter reset_value = {width{1'b0}};
input [width-1:0] d_i;
input [width-1:0] d_i;
output [width-1:0] o_pad;
input clk, rst;
wire [width-1:0] d_i_int `SYN_KEEP;
reg [width-1:0] o_pad_int;
assign d_i_int = d_i;
genvar i;
generate
for (i=0;i<width;i=i+1) begin
always @ (posedge clk or posedge rst)
if (rst)
o_pad_int[i] <= reset_value[i];
o_pad[i] <= 1'b0;
else
o_pad_int[i] <= d_i_int[i];
assign #1 o_pad[i] = o_pad_int[i];
o_pad[i] <= d_i_int[i];
end
endgenerate
endmodule
`timescale 1ns/1ns
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
parameter width = 1;
input [width-1:0] d_o;
736,7 → 730,7
d_i[i] <= 1'b0;
else
d_i[i] <= io_pad[i];
assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
assign io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
end
endgenerate
endmodule

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