URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 78 to Rev 77
- ↔ Reverse comparison
Rev 78 → Rev 77
/versatile_library/trunk/rtl/verilog/versatile_library.v
4743,7 → 4743,7
wbs_eoc <= 1'b0; |
else |
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full) |
wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111); |
wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_==3'b111); |
else if (wbs_eoc_alert & (a_rd | a_wr)) |
wbs_eoc <= 1'b1; |
|
4945,8 → 4945,7
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010; |
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 : |
(wbm_bte_o==2'b10) ? 4'd8 : |
(wbm_bte_o==2'b11) ? 4'd16: |
4'd1; |
4'd16; |
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o; |
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o; |
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest); |
4969,7 → 4968,7
.wbs_rst(wbs_rst), |
// wishbone master side |
.wbm_dat_o(writedata), |
.wbm_adr_o(address), |
.wbm_adr_o(adress), |
.wbm_sel_o(be), |
.wbm_bte_o(wbm_bte_o), |
.wbm_cti_o(wbm_cti_o), |
/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
1991,7 → 1991,7
wbs_eoc <= 1'b0; |
else |
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full) |
wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111); |
wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_==3'b111); |
else if (wbs_eoc_alert & (a_rd | a_wr)) |
wbs_eoc <= 1'b1; |
vl_cnt_shreg_ce_clear # ( .length(16)) |
2155,8 → 2155,7
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010; |
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 : |
(wbm_bte_o==2'b10) ? 4'd8 : |
(wbm_bte_o==2'b11) ? 4'd16: |
4'd1; |
4'd16; |
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o; |
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o; |
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest); |
2176,7 → 2175,7
.wbs_rst(wbs_rst), |
// wishbone master side |
.wbm_dat_o(writedata), |
.wbm_adr_o(address), |
.wbm_adr_o(adress), |
.wbm_sel_o(be), |
.wbm_bte_o(wbm_bte_o), |
.wbm_cti_o(wbm_cti_o), |
/versatile_library/trunk/rtl/verilog/wb.v
148,7 → 148,7
wbs_eoc <= 1'b0; |
else |
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full) |
wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111); |
wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_==3'b111); |
else if (wbs_eoc_alert & (a_rd | a_wr)) |
wbs_eoc <= 1'b1; |
|
350,8 → 350,7
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010; |
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 : |
(wbm_bte_o==2'b10) ? 4'd8 : |
(wbm_bte_o==2'b11) ? 4'd16: |
4'd1; |
4'd16; |
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o; |
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o; |
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest); |
374,7 → 373,7
.wbs_rst(wbs_rst), |
// wishbone master side |
.wbm_dat_o(writedata), |
.wbm_adr_o(address), |
.wbm_adr_o(adress), |
.wbm_sel_o(be), |
.wbm_bte_o(wbm_bte_o), |
.wbm_cti_o(wbm_cti_o), |
/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
2096,7 → 2096,7
wbs_eoc <= 1'b0; |
else |
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full) |
wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111); |
wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_==3'b111); |
else if (wbs_eoc_alert & (a_rd | a_wr)) |
wbs_eoc <= 1'b1; |
vl_cnt_shreg_ce_clear # ( .length(16)) |
2260,8 → 2260,7
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010; |
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 : |
(wbm_bte_o==2'b10) ? 4'd8 : |
(wbm_bte_o==2'b11) ? 4'd16: |
4'd1; |
4'd16; |
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o; |
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o; |
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest); |
2281,7 → 2280,7
.wbs_rst(wbs_rst), |
// wishbone master side |
.wbm_dat_o(writedata), |
.wbm_adr_o(address), |
.wbm_adr_o(adress), |
.wbm_sel_o(be), |
.wbm_bte_o(wbm_bte_o), |
.wbm_cti_o(wbm_cti_o), |