URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
Compare Revisions
- This comparison shows the changes necessary to convert path
/versatile_library/trunk/rtl/verilog
- from Rev 117 to Rev 116
- ↔ Reverse comparison
Rev 117 → Rev 116
/versatile_library.v
5863,7 → 5863,6
.adr_width(shadow_mem_adr_width), |
.mem_size(shadow_mem_size), |
.memory_init(shadow_mem_init), |
.memory_file(shadow_mem_file), |
.mode(mode)) |
shadow_mem0 ( |
.wbs_dat_i(wbs_dat_i), |
/versatile_library_actel.v
2623,7 → 2623,6
.adr_width(shadow_mem_adr_width), |
.mem_size(shadow_mem_size), |
.memory_init(shadow_mem_init), |
.memory_file(shadow_mem_file), |
.mode(mode)) |
shadow_mem0 ( |
.wbs_dat_i(wbs_dat_i), |
/versatile_library_altera.v
2728,7 → 2728,6
.adr_width(shadow_mem_adr_width), |
.mem_size(shadow_mem_size), |
.memory_init(shadow_mem_init), |
.memory_file(shadow_mem_file), |
.mode(mode)) |
shadow_mem0 ( |
.wbs_dat_i(wbs_dat_i), |
/wb.v
957,7 → 957,6
.adr_width(shadow_mem_adr_width), |
.mem_size(shadow_mem_size), |
.memory_init(shadow_mem_init), |
.memory_file(shadow_mem_file), |
.mode(mode)) |
shadow_mem0 ( |
.wbs_dat_i(wbs_dat_i), |