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    /versatile_library/trunk/rtl/verilog
    from Rev 146 to Rev 145
    Reverse comparison

Rev 146 → Rev 145

/versatile_library.v
4997,18 → 4997,16
`define MODULE reg_file
module `BASE`MODULE (
`undef MODULE
a1, a2, a3, wd3, we3, rd1, rd2, clk, rst );
parameter dw = 32;
parameter aw = 5;
a1, a2, a3, wd3, we3, rd1, rd2, clk
);
parameter data_width = 32;
parameter addr_width = 5;
parameter debug = 0;
input [aw-1:0] a1, a2, a3;
input [dw-1:0] wd3;
input [addr_width-1:0] a1, a2, a3;
input [data_width-1:0] wd3;
input we3;
output [dw-1:0] rd1, rd2;
output [data_width-1:0] rd1, rd2;
input clk;
wire [dw-1:0] rd1mem, rd2mem;
reg [dw-1:0] wreg;
reg sel1, sel2;
 
generate
if (debug==1) begin : debug_we
5018,37 → 5016,59
end
endgenerate
 
`ifdef ACTEL
reg [data_width-1:0] wd3_reg;
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
reg we3_reg;
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
always @ (posedge clk or posedge rst)
if (rst)
{wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
else
{wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
 
always @ (negedge clk)
if (we3_reg)
ram1[a3_reg] <= wd3;
always @ (posedge clk)
a1_reg <= a1;
assign rd1 = ram1[a1_reg];
always @ (negedge clk)
if (we3_reg)
ram2[a3_reg] <= wd3;
always @ (posedge clk)
a2_reg <= a2;
assign rd2 = ram2[a2_reg];
 
`else
 
`define MODULE dpram_1r1w
`BASE`MODULE
# ( .data_width(dw), .addr_width(aw))
# ( .data_width(data_width), .addr_width(addr_width))
ram1 (
.d_a(wd3),
.adr_a(a3),
.we_a(we3),
.clk_a(clk),
.q_b(rd1mem),
.q_b(rd1),
.adr_b(a1),
.clk_b(clk) );
`BASE`MODULE
# ( .data_width(dw), .addr_width(aw))
# ( .data_width(data_width), .addr_width(addr_width))
ram2 (
.d_a(wd3),
.adr_a(a3),
.we_a(we3),
.clk_a(clk),
.q_b(rd2mem),
.q_b(rd2),
.adr_b(a2),
.clk_b(clk) );
`undef MODULE
 
always @ (posedge clk or posedge rst)
if (rst)
{sel1, sel2, wreg} <= {1'b0,1'b0,{data_width{1'b0}}};
else
{sel1,sel2,wreg} <= {we3 & a1==a3, we3 & a2==a3,wd3};
assign rd1 = (sel1) ? wreg : rd1mem;
assign rd2 = (sel2) ? wreg : rd2mem;
`endif
 
endmodule
`endif
/versatile_library_actel.v
3396,18 → 3396,16
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
endmodule
module vl_reg_file (
a1, a2, a3, wd3, we3, rd1, rd2, clk, rst );
parameter dw = 32;
parameter aw = 5;
a1, a2, a3, wd3, we3, rd1, rd2, clk
);
parameter data_width = 32;
parameter addr_width = 5;
parameter debug = 0;
input [aw-1:0] a1, a2, a3;
input [dw-1:0] wd3;
input [addr_width-1:0] a1, a2, a3;
input [data_width-1:0] wd3;
input we3;
output [dw-1:0] rd1, rd2;
output [data_width-1:0] rd1, rd2;
input clk;
wire [dw-1:0] rd1mem, rd2mem;
reg [dw-1:0] wreg;
reg sel1, sel2;
generate
if (debug==1) begin : debug_we
always @ (posedge clk)
3415,33 → 3413,28
$display ("Value %h written at register %h : time %t", wd3, a3, $time);
end
endgenerate
vl_dpram_1r1w
# ( .data_width(dw), .addr_width(aw))
ram1 (
.d_a(wd3),
.adr_a(a3),
.we_a(we3),
.clk_a(clk),
.q_b(rd1mem),
.adr_b(a1),
.clk_b(clk) );
vl_dpram_1r1w
# ( .data_width(dw), .addr_width(aw))
ram2 (
.d_a(wd3),
.adr_a(a3),
.we_a(we3),
.clk_a(clk),
.q_b(rd2mem),
.adr_b(a2),
.clk_b(clk) );
reg [data_width-1:0] wd3_reg;
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
reg we3_reg;
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
always @ (posedge clk or posedge rst)
if (rst)
{sel1, sel2, wreg} <= {1'b0,1'b0,{data_width{1'b0}}};
{wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
else
{sel1,sel2,wreg} <= {we3 & a1==a3, we3 & a2==a3,wd3};
assign rd1 = (sel1) ? wreg : rd1mem;
assign rd2 = (sel2) ? wreg : rd2mem;
{wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
always @ (negedge clk)
if (we3_reg)
ram1[a3_reg] <= wd3;
always @ (posedge clk)
a1_reg <= a1;
assign rd1 = ram1[a1_reg];
always @ (negedge clk)
if (we3_reg)
ram2[a3_reg] <= wd3;
always @ (posedge clk)
a2_reg <= a2;
assign rd2 = ram2[a2_reg];
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
/versatile_library_altera.v
3491,18 → 3491,16
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
endmodule
module vl_reg_file (
a1, a2, a3, wd3, we3, rd1, rd2, clk, rst );
parameter dw = 32;
parameter aw = 5;
a1, a2, a3, wd3, we3, rd1, rd2, clk
);
parameter data_width = 32;
parameter addr_width = 5;
parameter debug = 0;
input [aw-1:0] a1, a2, a3;
input [dw-1:0] wd3;
input [addr_width-1:0] a1, a2, a3;
input [data_width-1:0] wd3;
input we3;
output [dw-1:0] rd1, rd2;
output [data_width-1:0] rd1, rd2;
input clk;
wire [dw-1:0] rd1mem, rd2mem;
reg [dw-1:0] wreg;
reg sel1, sel2;
generate
if (debug==1) begin : debug_we
always @ (posedge clk)
3511,32 → 3509,25
end
endgenerate
vl_dpram_1r1w
# ( .data_width(dw), .addr_width(aw))
# ( .data_width(data_width), .addr_width(addr_width))
ram1 (
.d_a(wd3),
.adr_a(a3),
.we_a(we3),
.clk_a(clk),
.q_b(rd1mem),
.q_b(rd1),
.adr_b(a1),
.clk_b(clk) );
vl_dpram_1r1w
# ( .data_width(dw), .addr_width(aw))
# ( .data_width(data_width), .addr_width(addr_width))
ram2 (
.d_a(wd3),
.adr_a(a3),
.we_a(we3),
.clk_a(clk),
.q_b(rd2mem),
.q_b(rd2),
.adr_b(a2),
.clk_b(clk) );
always @ (posedge clk or posedge rst)
if (rst)
{sel1, sel2, wreg} <= {1'b0,1'b0,{data_width{1'b0}}};
else
{sel1,sel2,wreg} <= {we3 & a1==a3, we3 & a2==a3,wd3};
assign rd1 = (sel1) ? wreg : rd1mem;
assign rd2 = (sel2) ? wreg : rd2mem;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
/memories.v
1087,18 → 1087,16
`define MODULE reg_file
module `BASE`MODULE (
`undef MODULE
a1, a2, a3, wd3, we3, rd1, rd2, clk, rst );
parameter dw = 32;
parameter aw = 5;
a1, a2, a3, wd3, we3, rd1, rd2, clk
);
parameter data_width = 32;
parameter addr_width = 5;
parameter debug = 0;
input [aw-1:0] a1, a2, a3;
input [dw-1:0] wd3;
input [addr_width-1:0] a1, a2, a3;
input [data_width-1:0] wd3;
input we3;
output [dw-1:0] rd1, rd2;
output [data_width-1:0] rd1, rd2;
input clk;
wire [dw-1:0] rd1mem, rd2mem;
reg [dw-1:0] wreg;
reg sel1, sel2;
 
generate
if (debug==1) begin : debug_we
1108,37 → 1106,59
end
endgenerate
 
`ifdef ACTEL
reg [data_width-1:0] wd3_reg;
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
reg we3_reg;
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
always @ (posedge clk or posedge rst)
if (rst)
{wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
else
{wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
 
always @ (negedge clk)
if (we3_reg)
ram1[a3_reg] <= wd3;
always @ (posedge clk)
a1_reg <= a1;
assign rd1 = ram1[a1_reg];
always @ (negedge clk)
if (we3_reg)
ram2[a3_reg] <= wd3;
always @ (posedge clk)
a2_reg <= a2;
assign rd2 = ram2[a2_reg];
 
`else
 
`define MODULE dpram_1r1w
`BASE`MODULE
# ( .data_width(dw), .addr_width(aw))
# ( .data_width(data_width), .addr_width(addr_width))
ram1 (
.d_a(wd3),
.adr_a(a3),
.we_a(we3),
.clk_a(clk),
.q_b(rd1mem),
.q_b(rd1),
.adr_b(a1),
.clk_b(clk) );
`BASE`MODULE
# ( .data_width(dw), .addr_width(aw))
# ( .data_width(data_width), .addr_width(addr_width))
ram2 (
.d_a(wd3),
.adr_a(a3),
.we_a(we3),
.clk_a(clk),
.q_b(rd2mem),
.q_b(rd2),
.adr_b(a2),
.clk_b(clk) );
`undef MODULE
 
always @ (posedge clk or posedge rst)
if (rst)
{sel1, sel2, wreg} <= {1'b0,1'b0,{data_width{1'b0}}};
else
{sel1,sel2,wreg} <= {we3 & a1==a3, we3 & a2==a3,wd3};
assign rd1 = (sel1) ? wreg : rd1mem;
assign rd2 = (sel2) ? wreg : rd2mem;
`endif
 
endmodule
`endif

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