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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path
    /versatile_library/trunk/rtl/verilog
    from Rev 148 to Rev 147
    Reverse comparison

Rev 148 → Rev 147

/versatile_library.v
5044,7 → 5044,7
 
always @ (posedge clk or posedge rst)
if (rst)
{sel1, sel2, wreg} <= {1'b0,1'b0,{dw{1'b0}}};
{sel1, sel2, wreg} <= {1'b0,1'b0,{data_width{1'b0}}};
else
{sel1,sel2,wreg} <= {we3 & a1==a3, we3 & a2==a3,wd3};
assign rd1 = (sel1) ? wreg : rd1mem;
/versatile_library_actel.v
3437,7 → 3437,7
.clk_b(clk) );
always @ (posedge clk or posedge rst)
if (rst)
{sel1, sel2, wreg} <= {1'b0,1'b0,{dw{1'b0}}};
{sel1, sel2, wreg} <= {1'b0,1'b0,{data_width{1'b0}}};
else
{sel1,sel2,wreg} <= {we3 & a1==a3, we3 & a2==a3,wd3};
assign rd1 = (sel1) ? wreg : rd1mem;
/versatile_library_altera.v
3532,7 → 3532,7
.clk_b(clk) );
always @ (posedge clk or posedge rst)
if (rst)
{sel1, sel2, wreg} <= {1'b0,1'b0,{dw{1'b0}}};
{sel1, sel2, wreg} <= {1'b0,1'b0,{data_width{1'b0}}};
else
{sel1,sel2,wreg} <= {we3 & a1==a3, we3 & a2==a3,wd3};
assign rd1 = (sel1) ? wreg : rd1mem;
/memories.v
1134,7 → 1134,7
 
always @ (posedge clk or posedge rst)
if (rst)
{sel1, sel2, wreg} <= {1'b0,1'b0,{dw{1'b0}}};
{sel1, sel2, wreg} <= {1'b0,1'b0,{data_width{1'b0}}};
else
{sel1,sel2,wreg} <= {we3 & a1==a3, we3 & a2==a3,wd3};
assign rd1 = (sel1) ? wreg : rd1mem;

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