URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
Compare Revisions
- This comparison shows the changes necessary to convert path
/versatile_library/trunk/rtl/verilog
- from Rev 5 to Rev 4
- ↔ Reverse comparison
Rev 5 → Rev 4
/memories.v
File deleted
/counters.v
40,24 → 40,9
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module cnt_shreg_wrap ( q, rst, clk); |
module cnt_shreg_ce ( cke, q, rst, clk); |
|
parameter length = 4; |
output reg [0:length-1] q; |
input rst; |
input clk; |
|
always @ (posedge clk or posedge rst) |
if (rst) |
q <= {1'b1,{length-1{1'b0}}}; |
else |
q <= {q[length-1],q[0:length-2]}; |
|
endmodule |
|
module cnt_shreg_ce_wrap ( cke, q, rst, clk); |
|
parameter length = 4; |
input cke; |
output reg [0:length-1] q; |
input rst; |
68,7 → 53,7
q <= {1'b1,{length-1{1'b0}}}; |
else |
if (cke) |
q <= {q[length-1],q[0:length-2]}; |
q <= q >> 1; |
|
endmodule |
|
75,7 → 60,8
module cnt_shreg_ce_clear ( cke, clear, q, rst, clk); |
|
parameter length = 4; |
input cke, clear; |
input cke; |
input clear; |
output reg [0:length-1] q; |
input rst; |
input clk; |
92,22 → 78,4
|
endmodule |
|
module cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk); |
|
parameter length = 4; |
input cke, clear; |
output reg [0:length-1] q; |
input rst; |
input clk; |
|
always @ (posedge clk or posedge rst) |
if (rst) |
q <= {1'b1,{length-1{1'b0}}}; |
else |
if (cke) |
if (clear) |
q <= {1'b1,{length-1{1'b0}}}; |
else |
q <= {q[length-1],q[0:length-2]}; |
|
endmodule |
/Makefile
14,7 → 14,6
|
VERILOG_FILES += $(VERILOG_FILES_CNT) |
VERILOG_FILES += counters.v |
VERILOG_FILES += memories.v |
|
VERSATILE_LIBRARIES = versatile_library.v |
VERSATILE_LIBRARIES += versatile_library_actel.v |
/registers.v
57,31 → 57,6
|
endmodule |
|
module dff_array ( d, q, clk, rst); |
|
parameter width = 1; |
parameter depth = 2; |
parameter reset_value = 1'b0; |
|
input [width-1:0] d; |
input clk, rst; |
output [width-1:0] q; |
reg [0:depth-1] q_tmp [width-1:0]; |
integer i; |
always @ (posedge clk or posedge rst) |
if (rst) begin |
for (i=0;i<depth;i=i+1) |
q_tmp[i] <= {width{reset_value}}; |
end else begin |
q_tmp[0] <= d; |
for (i=1;i<depth;i=i+1) |
q_tmp[i] <= q_tmp[i-1]; |
end |
|
assign q = q_tmp[depth-1]; |
|
endmodule |
|
module dff_ce ( d, ce, q, clk, rst); |
|
parameter width = 1; |
243,25 → 218,3
endmodule |
|
`endif |
|
// LATCH |
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1 |
`ifdef ALTERA |
module latch ( d, le, q, clk); |
input d, le; |
output q; |
input clk; |
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q)); |
endmodule |
`else |
module latch ( d, le, q, clk); |
input d, le; |
output q; |
input clk;/* |
always @ (posedge direction_set or posedge direction_clr) |
if (direction_clr) |
direction <= going_empty; |
else |
direction <= going_full;*/ |
endmodule |
`endif |