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Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path
    /versatile_library/trunk/rtl
    from Rev 124 to Rev 123
    Reverse comparison

Rev 124 → Rev 123

/verilog/versatile_library.v
4201,20 → 4201,7
parameter a_data_width = 32;
parameter a_addr_width = 8;
parameter b_data_width = 64; //a_data_width;
//localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
localparam b_addr_width =
(a_data_width==b_data_width) ? aw_m :
(a_data_width==b_data_width*2) ? aw_m+1 :
(a_data_width==b_data_width*4) ? aw_m+2 :
(a_data_width==b_data_width*8) ? aw_m+3 :
(a_data_width==b_data_width*16) ? aw_m+4 :
(a_data_width==b_data_width*32) ? aw_m+5 :
(a_data_width==b_data_width/2) ? aw_m-1 :
(a_data_width==b_data_width/4) ? aw_m-2 :
(a_data_width==b_data_width/8) ? aw_m-3 :
(a_data_width==b_data_width/16) ? aw_m-4 :
(a_data_width==b_data_width/32) ? aw_m-5 : 0;
 
localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
 
6153,20 → 6140,7
parameter dw_s = 32;
parameter aw_s = 24;
parameter dw_m = dw_s;
//localparam aw_m = dw_s * aw_s / dw_m;
localparam aw_m =
(dw_s==dw_m) ? aw_m :
(dw_s==dw_m*2) ? aw_m+1 :
(dw_s==dw_m*4) ? aw_m+2 :
(dw_s==dw_m*8) ? aw_m+3 :
(dw_s==dw_m*16) ? aw_m+4 :
(dw_s==dw_m*32) ? aw_m+5 :
(dw_s==dw_m/2) ? aw_m-1 :
(dw_s==adw_m/4) ? aw_m-2 :
(dw_s==dw_m/8) ? aw_m-3 :
(dw_s==dw_m/16) ? aw_m-4 :
(dw_s==dw_m/32) ? aw_m-5 : 0;
 
localparam aw_m = dw_s * aw_s / dw_m;
parameter wbs_max_burst_width = 4;
parameter wbs_mode = "B3";
 
/verilog/versatile_library_actel.v
1596,19 → 1596,7
parameter a_data_width = 32;
parameter a_addr_width = 8;
parameter b_data_width = 64; //a_data_width;
//localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
localparam b_addr_width =
(a_data_width==b_data_width) ? aw_m :
(a_data_width==b_data_width*2) ? aw_m+1 :
(a_data_width==b_data_width*4) ? aw_m+2 :
(a_data_width==b_data_width*8) ? aw_m+3 :
(a_data_width==b_data_width*16) ? aw_m+4 :
(a_data_width==b_data_width*32) ? aw_m+5 :
(a_data_width==b_data_width/2) ? aw_m-1 :
(a_data_width==b_data_width/4) ? aw_m-2 :
(a_data_width==b_data_width/8) ? aw_m-3 :
(a_data_width==b_data_width/16) ? aw_m-4 :
(a_data_width==b_data_width/32) ? aw_m-5 : 0;
localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
parameter memory_init = 0;
2854,19 → 2842,7
parameter dw_s = 32;
parameter aw_s = 24;
parameter dw_m = dw_s;
//localparam aw_m = dw_s * aw_s / dw_m;
localparam aw_m =
(dw_s==dw_m) ? aw_m :
(dw_s==dw_m*2) ? aw_m+1 :
(dw_s==dw_m*4) ? aw_m+2 :
(dw_s==dw_m*8) ? aw_m+3 :
(dw_s==dw_m*16) ? aw_m+4 :
(dw_s==dw_m*32) ? aw_m+5 :
(dw_s==dw_m/2) ? aw_m-1 :
(dw_s==adw_m/4) ? aw_m-2 :
(dw_s==dw_m/8) ? aw_m-3 :
(dw_s==dw_m/16) ? aw_m-4 :
(dw_s==dw_m/32) ? aw_m-5 : 0;
localparam aw_m = dw_s * aw_s / dw_m;
parameter wbs_max_burst_width = 4;
parameter wbs_mode = "B3";
parameter async = 1; // wbs_clk != wbm_clk
/verilog/wb.v
1235,20 → 1235,7
parameter dw_s = 32;
parameter aw_s = 24;
parameter dw_m = dw_s;
//localparam aw_m = dw_s * aw_s / dw_m;
localparam aw_m =
(dw_s==dw_m) ? aw_m :
(dw_s==dw_m*2) ? aw_m+1 :
(dw_s==dw_m*4) ? aw_m+2 :
(dw_s==dw_m*8) ? aw_m+3 :
(dw_s==dw_m*16) ? aw_m+4 :
(dw_s==dw_m*32) ? aw_m+5 :
(dw_s==dw_m/2) ? aw_m-1 :
(dw_s==adw_m/4) ? aw_m-2 :
(dw_s==dw_m/8) ? aw_m-3 :
(dw_s==dw_m/16) ? aw_m-4 :
(dw_s==dw_m/32) ? aw_m-5 : 0;
 
localparam aw_m = dw_s * aw_s / dw_m;
parameter wbs_max_burst_width = 4;
parameter wbs_mode = "B3";
 
/verilog/versatile_library_altera.v
1703,19 → 1703,7
parameter a_data_width = 32;
parameter a_addr_width = 8;
parameter b_data_width = 64; //a_data_width;
//localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
localparam b_addr_width =
(a_data_width==b_data_width) ? aw_m :
(a_data_width==b_data_width*2) ? aw_m+1 :
(a_data_width==b_data_width*4) ? aw_m+2 :
(a_data_width==b_data_width*8) ? aw_m+3 :
(a_data_width==b_data_width*16) ? aw_m+4 :
(a_data_width==b_data_width*32) ? aw_m+5 :
(a_data_width==b_data_width/2) ? aw_m-1 :
(a_data_width==b_data_width/4) ? aw_m-2 :
(a_data_width==b_data_width/8) ? aw_m-3 :
(a_data_width==b_data_width/16) ? aw_m-4 :
(a_data_width==b_data_width/32) ? aw_m-5 : 0;
localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
parameter memory_init = 0;
2959,19 → 2947,7
parameter dw_s = 32;
parameter aw_s = 24;
parameter dw_m = dw_s;
//localparam aw_m = dw_s * aw_s / dw_m;
localparam aw_m =
(dw_s==dw_m) ? aw_m :
(dw_s==dw_m*2) ? aw_m+1 :
(dw_s==dw_m*4) ? aw_m+2 :
(dw_s==dw_m*8) ? aw_m+3 :
(dw_s==dw_m*16) ? aw_m+4 :
(dw_s==dw_m*32) ? aw_m+5 :
(dw_s==dw_m/2) ? aw_m-1 :
(dw_s==adw_m/4) ? aw_m-2 :
(dw_s==dw_m/8) ? aw_m-3 :
(dw_s==dw_m/16) ? aw_m-4 :
(dw_s==dw_m/32) ? aw_m-5 : 0;
localparam aw_m = dw_s * aw_s / dw_m;
parameter wbs_max_burst_width = 4;
parameter wbs_mode = "B3";
parameter async = 1; // wbs_clk != wbm_clk
/verilog/memories.v
438,20 → 438,7
parameter a_data_width = 32;
parameter a_addr_width = 8;
parameter b_data_width = 64; //a_data_width;
//localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
localparam b_addr_width =
(a_data_width==b_data_width) ? aw_m :
(a_data_width==b_data_width*2) ? aw_m+1 :
(a_data_width==b_data_width*4) ? aw_m+2 :
(a_data_width==b_data_width*8) ? aw_m+3 :
(a_data_width==b_data_width*16) ? aw_m+4 :
(a_data_width==b_data_width*32) ? aw_m+5 :
(a_data_width==b_data_width/2) ? aw_m-1 :
(a_data_width==b_data_width/4) ? aw_m-2 :
(a_data_width==b_data_width/8) ? aw_m-3 :
(a_data_width==b_data_width/16) ? aw_m-4 :
(a_data_width==b_data_width/32) ? aw_m-5 : 0;
 
localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
 

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