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  • This comparison shows the changes necessary to convert path
    /versatile_library/trunk/rtl
    from Rev 14 to Rev 13
    Reverse comparison

Rev 14 → Rev 13

/verilog/versatile_library.v
1642,7 → 1642,6
 
endmodule
 
/*
module vl_rom ( adr, q, clk);
 
parameter data_width = 32;
1674,7 → 1673,7
q <= data[adr];
 
endmodule
*/
 
// Single port RAM
 
module vl_ram ( d, adr, we, q, clk);
1870,7 → 1869,7
parameter going_full = 1'b1;
input [N:0] wptr, rptr;
output fifo_empty;
output reg fifo_empty;
output fifo_full;
input wclk, rclk, rst;
 
1884,7 → 1883,7
wire async_empty, async_full;
wire fifo_full2;
wire fifo_empty2;
reg fifo_empty2;
// direction_set
always @ (wptr[N:N-1] or rptr[N:N-1])
1936,13 → 1935,11
else
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
*/
/* always @ (posedge rclk or posedge async_empty)
always @ (posedge rclk or posedge async_empty)
if (async_empty)
{fifo_empty, fifo_empty2} <= 2'b11;
else
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty));
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
 
endmodule // async_comp
 
2171,7 → 2168,7
input [2:0] wbs_cti_i;
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
output [31:0] wbs_dat_o;
output wbs_ack_o;
output reg wbs_ack_o;
input wbs_clk, wbs_rst;
 
output [31:0] wbm_dat_o;
2179,8 → 2176,7
output [3:0] wbm_sel_o;
output reg [1:0] wbm_bte_o;
output reg [2:0] wbm_cti_o;
output reg wbm_we_o;
output wbm_cyc_o;
output reg wbm_we_o, wbm_cyc_o;
output wbm_stb_o;
input [31:0] wbm_dat_i;
input wbm_ack_i;
2211,14 → 2207,14
reg wbs_eoc, wbm_eoc;
reg [1:0] wbm;
 
wire [1:16] wbs_count, wbm_count;
reg [1:16] wbs_count, wbm_count;
 
wire [35:0] a_d, a_q, b_d, b_q;
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
reg a_rd_reg;
wire b_rd_adr, b_rd_data;
wire b_rd_data_reg;
wire [35:0] temp;
reg b_rd_data_reg;
reg [35:0] temp;
 
`define WE 5
`define BTE 4:3
/verilog/versatile_library_actel.v
1308,7 → 1308,6
always @ (posedge clk)
q <= rom[adr];
endmodule
/*
module vl_rom ( adr, q, clk);
parameter data_width = 32;
parameter addr_width = 4;
1335,7 → 1334,6
always @ (posedge clk)
q <= data[adr];
endmodule
*/
// Single port RAM
module vl_ram ( d, adr, we, q, clk);
parameter data_width = 32;
1498,7 → 1496,7
parameter going_empty = 1'b0;
parameter going_full = 1'b1;
input [N:0] wptr, rptr;
output fifo_empty;
output reg fifo_empty;
output fifo_full;
input wclk, rclk, rst;
wire direction;
1505,7 → 1503,7
reg direction_set, direction_clr;
wire async_empty, async_full;
wire fifo_full2;
wire fifo_empty2;
reg fifo_empty2;
// direction_set
always @ (wptr[N:N-1] or rptr[N:N-1])
case ({wptr[N:N-1],rptr[N:N-1]})
1541,13 → 1539,11
else
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
*/
/* always @ (posedge rclk or posedge async_empty)
always @ (posedge rclk or posedge async_empty)
if (async_empty)
{fifo_empty, fifo_empty2} <= 2'b11;
else
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty));
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
endmodule // async_comp
module vl_fifo_1r1w_async (
d, wr, fifo_full, wr_clk, wr_rst,
1742,7 → 1738,7
input [2:0] wbs_cti_i;
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
output [31:0] wbs_dat_o;
output wbs_ack_o;
output reg wbs_ack_o;
input wbs_clk, wbs_rst;
output [31:0] wbm_dat_o;
output reg [31:2] wbm_adr_o;
1749,8 → 1745,7
output [3:0] wbm_sel_o;
output reg [1:0] wbm_bte_o;
output reg [2:0] wbm_cti_o;
output reg wbm_we_o;
output wbm_cyc_o;
output reg wbm_we_o, wbm_cyc_o;
output wbm_stb_o;
input [31:0] wbm_dat_i;
input wbm_ack_i;
1775,13 → 1770,13
wire wbs_eoc_alert, wbm_eoc_alert;
reg wbs_eoc, wbm_eoc;
reg [1:0] wbm;
wire [1:16] wbs_count, wbm_count;
reg [1:16] wbs_count, wbm_count;
wire [35:0] a_d, a_q, b_d, b_q;
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
reg a_rd_reg;
wire b_rd_adr, b_rd_data;
wire b_rd_data_reg;
wire [35:0] temp;
reg b_rd_data_reg;
reg [35:0] temp;
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
/verilog/wb.v
55,7 → 55,7
input [2:0] wbs_cti_i;
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
output [31:0] wbs_dat_o;
output wbs_ack_o;
output reg wbs_ack_o;
input wbs_clk, wbs_rst;
 
output [31:0] wbm_dat_o;
63,8 → 63,7
output [3:0] wbm_sel_o;
output reg [1:0] wbm_bte_o;
output reg [2:0] wbm_cti_o;
output reg wbm_we_o;
output wbm_cyc_o;
output reg wbm_we_o, wbm_cyc_o;
output wbm_stb_o;
input [31:0] wbm_dat_i;
input wbm_ack_i;
95,14 → 94,14
reg wbs_eoc, wbm_eoc;
reg [1:0] wbm;
 
wire [1:16] wbs_count, wbm_count;
reg [1:16] wbs_count, wbm_count;
 
wire [35:0] a_d, a_q, b_d, b_q;
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
reg a_rd_reg;
wire b_rd_adr, b_rd_data;
wire b_rd_data_reg;
wire [35:0] temp;
reg b_rd_data_reg;
reg [35:0] temp;
 
`define WE 5
`define BTE 4:3
/verilog/versatile_library_altera.v
1294,7 → 1294,6
always @ (posedge clk)
q <= rom[adr];
endmodule
/*
module vl_rom ( adr, q, clk);
parameter data_width = 32;
parameter addr_width = 4;
1321,7 → 1320,6
always @ (posedge clk)
q <= data[adr];
endmodule
*/
// Single port RAM
module vl_ram ( d, adr, we, q, clk);
parameter data_width = 32;
1484,7 → 1482,7
parameter going_empty = 1'b0;
parameter going_full = 1'b1;
input [N:0] wptr, rptr;
output fifo_empty;
output reg fifo_empty;
output fifo_full;
input wclk, rclk, rst;
wire direction;
1491,7 → 1489,7
reg direction_set, direction_clr;
wire async_empty, async_full;
wire fifo_full2;
wire fifo_empty2;
reg fifo_empty2;
// direction_set
always @ (wptr[N:N-1] or rptr[N:N-1])
case ({wptr[N:N-1],rptr[N:N-1]})
1527,13 → 1525,11
else
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
*/
/* always @ (posedge rclk or posedge async_empty)
always @ (posedge rclk or posedge async_empty)
if (async_empty)
{fifo_empty, fifo_empty2} <= 2'b11;
else
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty));
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
endmodule // async_comp
module vl_fifo_1r1w_async (
d, wr, fifo_full, wr_clk, wr_rst,
1728,7 → 1724,7
input [2:0] wbs_cti_i;
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
output [31:0] wbs_dat_o;
output wbs_ack_o;
output reg wbs_ack_o;
input wbs_clk, wbs_rst;
output [31:0] wbm_dat_o;
output reg [31:2] wbm_adr_o;
1735,8 → 1731,7
output [3:0] wbm_sel_o;
output reg [1:0] wbm_bte_o;
output reg [2:0] wbm_cti_o;
output reg wbm_we_o;
output wbm_cyc_o;
output reg wbm_we_o, wbm_cyc_o;
output wbm_stb_o;
input [31:0] wbm_dat_i;
input wbm_ack_i;
1761,13 → 1756,13
wire wbs_eoc_alert, wbm_eoc_alert;
reg wbs_eoc, wbm_eoc;
reg [1:0] wbm;
wire [1:16] wbs_count, wbm_count;
reg [1:16] wbs_count, wbm_count;
wire [35:0] a_d, a_q, b_d, b_q;
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
reg a_rd_reg;
wire b_rd_adr, b_rd_data;
wire b_rd_data_reg;
wire [35:0] temp;
reg b_rd_data_reg;
reg [35:0] temp;
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
/verilog/memories.v
60,7 → 60,6
 
endmodule
 
/*
module vl_rom ( adr, q, clk);
 
parameter data_width = 32;
92,7 → 91,7
q <= data[adr];
 
endmodule
*/
 
// Single port RAM
 
module vl_ram ( d, adr, we, q, clk);
288,7 → 287,7
parameter going_full = 1'b1;
input [N:0] wptr, rptr;
output fifo_empty;
output reg fifo_empty;
output fifo_full;
input wclk, rclk, rst;
 
302,7 → 301,7
wire async_empty, async_full;
wire fifo_full2;
wire fifo_empty2;
reg fifo_empty2;
// direction_set
always @ (wptr[N:N-1] or rptr[N:N-1])
354,13 → 353,11
else
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
*/
/* always @ (posedge rclk or posedge async_empty)
always @ (posedge rclk or posedge async_empty)
if (async_empty)
{fifo_empty, fifo_empty2} <= 2'b11;
else
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty));
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
 
endmodule // async_comp
 

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