URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
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- This comparison shows the changes necessary to convert path
/versatile_library/trunk/rtl
- from Rev 15 to Rev 14
- ↔ Reverse comparison
Rev 15 → Rev 14
/verilog/versatile_library.v
529,23 → 529,7
else |
direction <= going_full;*/ |
endmodule |
`endif |
|
module delay ( d, q, clk, rst); |
parameter depth = 10; |
input d; |
output q; |
input clk, rst; |
|
reg [1:depth] dffs; |
|
always @ (posedge clk or posedge rst) |
if (rst) |
dffs <= {depth{1'b0}}; |
else |
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
endmodule////////////////////////////////////////////////////////////////////// |
`endif////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
/verilog/versatile_library_actel.v
294,19 → 294,6
else |
direction <= going_full;*/ |
endmodule |
module delay ( d, q, clk, rst); |
parameter depth = 10; |
input d; |
output q; |
input clk, rst; |
reg [1:depth] dffs; |
always @ (posedge clk or posedge rst) |
if (rst) |
dffs <= {depth{1'b0}}; |
else |
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
/verilog/versatile_library_altera.v
280,19 → 280,6
input clk; |
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q)); |
endmodule |
module delay ( d, q, clk, rst); |
parameter depth = 10; |
input d; |
output q; |
input clk, rst; |
reg [1:depth] dffs; |
always @ (posedge clk or posedge rst) |
if (rst) |
dffs <= {depth{1'b0}}; |
else |
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
/verilog/registers.v
285,20 → 285,4
else |
direction <= going_full;*/ |
endmodule |
`endif |
|
module delay ( d, q, clk, rst); |
parameter depth = 10; |
input d; |
output q; |
input clk, rst; |
|
reg [1:depth] dffs; |
|
always @ (posedge clk or posedge rst) |
if (rst) |
dffs <= {depth{1'b0}}; |
else |
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
endmodule |
`endif |