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Rev 7 → Rev 6

/verilog/versatile_library.v
1603,26 → 1603,8
 
/// ROM
 
module vl_rom_init ( adr, q, clk);
parameter data_width = 32;
parameter addr_width = 8;
input [(addr_width-1):0] adr;
output reg [(data_width-1):0] q;
input clk;
reg [data_width-1:0] rom [(1<<addr_width)-1:0];
parameter memory_file = "vl_rom.vmem";
initial
begin
$readmemh(memory_file, rom);
end
always @ (posedge clk)
q <= rom[adr];
module vl_rom ( a, q, clk);
 
endmodule
 
module vl_rom ( adr, q, clk);
 
parameter data_width = 32;
parameter addr_width = 4;
 
1644,12 → 1626,12
{32'h15000000},
{32'h15000000}};
 
input [addr_width-1:0] adr;
input [addr_width-1:0] a;
output reg [data_width-1:0] q;
input clk;
 
always @ (posedge clk)
q <= data[adr];
q <= data[a];
 
endmodule
 
1661,19 → 1643,9
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input we;
output reg [(data_width-1):0] q;
output reg [(data_width-1):0] q;
input clk;
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
always @ (posedge clk)
begin
if (we)
1683,42 → 1655,6
 
endmodule
 
module vl_ram_be ( d, adr, be, we, q, clk);
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input [(addr_width/4)-1:0] be;
input we;
output reg [(data_width-1):0] q;
input clk;
 
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
 
genvar i;
generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
always @ (posedge clk)
if (we & be[i])
ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
end
endgenerate
 
always @ (posedge clk)
q <= ram[adr];
 
endmodule
 
 
// Dual port RAM
 
// ACTEL FPGA should not use logic to handle rw collision
1728,7 → 1664,7
`define SYN
`endif
 
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
module vl_dual_port_ram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
1739,17 → 1675,6
input clk_a, clk_b;
reg [(addr_width-1):0] adr_b_reg;
reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
 
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
 
always @ (posedge clk_a)
if (we_a)
ram[adr_a] <= d_a;
1758,7 → 1683,7
assign q_b = ram[adr_b_reg];
endmodule
 
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
module vl_dual_port_ram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
1770,17 → 1695,6
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
 
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
 
always @ (posedge clk_a)
begin
q_a <= ram[adr_a];
1791,7 → 1705,7
q_b <= ram[adr_b];
endmodule
 
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
module vl_dual_port_ram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, d_b, we_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
1805,17 → 1719,6
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
 
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
 
always @ (posedge clk_a)
begin
q_a <= ram[adr_a];
1950,15 → 1853,15
q, rd, fifo_empty, rd_clk, rd_rst
);
 
cnt_gray_ce_bin
adr_gen
# ( .length(addr_width))
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
cnt_gray_ce_bin
adr_gen
# (.length(addr_width))
fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
 
vl_dpram_1r1w
vl_dual_port_ram_1r1w
# (.data_width(data_width), .addr_width(addr_width))
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
 
2056,19 → 1959,19
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
 
cnt_gray_ce_bin
adr_gen
# ( .length(addr_width))
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
cnt_gray_ce_bin
adr_gen
# (.length(addr_width))
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
 
cnt_gray_ce_bin
adr_gen
# ( .length(addr_width))
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
cnt_gray_ce_bin
adr_gen
# (.length(addr_width))
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
 
2076,7 → 1979,7
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
 
vl_dp_ram_2r2w
vfifo_dual_port_ram_dc_dw
# (.data_width(data_width), .addr_width(addr_width+1))
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2085,7 → 1988,7
# (.addr_width(addr_width))
cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
 
vl_fifo_async_cmp
versatile_fifo_async_cmp
# (.addr_width(addr_width))
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
 
/verilog/versatile_library_actel.v
1277,22 → 1277,7
//// ////
//////////////////////////////////////////////////////////////////////
/// ROM
module vl_rom_init ( adr, q, clk);
parameter data_width = 32;
parameter addr_width = 8;
input [(addr_width-1):0] adr;
output reg [(data_width-1):0] q;
input clk;
reg [data_width-1:0] rom [(1<<addr_width)-1:0];
parameter memory_file = "vl_rom.vmem";
initial
begin
$readmemh(memory_file, rom);
end
always @ (posedge clk)
q <= rom[adr];
endmodule
module vl_rom ( adr, q, clk);
module vl_rom ( a, q, clk);
parameter data_width = 32;
parameter addr_width = 4;
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1312,11 → 1297,11
{32'h15000000},
{32'h15000000},
{32'h15000000}};
input [addr_width-1:0] adr;
input [addr_width-1:0] a;
output reg [data_width-1:0] q;
input clk;
always @ (posedge clk)
q <= data[adr];
q <= data[a];
endmodule
// Single port RAM
module vl_ram ( d, adr, we, q, clk);
1325,18 → 1310,9
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input we;
output reg [(data_width-1):0] q;
output reg [(data_width-1):0] q;
input clk;
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
always @ (posedge clk)
begin
if (we)
1344,38 → 1320,9
q <= ram[adr];
end
endmodule
module vl_ram_be ( d, adr, be, we, q, clk);
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input [(addr_width/4)-1:0] be;
input we;
output reg [(data_width-1):0] q;
input clk;
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
genvar i;
generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
always @ (posedge clk)
if (we & be[i])
ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
end
endgenerate
always @ (posedge clk)
q <= ram[adr];
endmodule
// Dual port RAM
// ACTEL FPGA should not use logic to handle rw collision
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
module vl_dual_port_ram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
1386,15 → 1333,6
input clk_a, clk_b;
reg [(addr_width-1):0] adr_b_reg;
reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
always @ (posedge clk_a)
if (we_a)
ram[adr_a] <= d_a;
1402,7 → 1340,7
adr_b_reg <= adr_b;
assign q_b = ram[adr_b_reg];
endmodule
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
module vl_dual_port_ram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
1414,15 → 1352,6
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
always @ (posedge clk_a)
begin
q_a <= ram[adr_a];
1432,7 → 1361,7
always @ (posedge clk_b)
q_b <= ram[adr_b];
endmodule
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
module vl_dual_port_ram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, d_b, we_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
1446,15 → 1375,6
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
always @ (posedge clk_a)
begin
q_a <= ram[adr_a];
1552,13 → 1472,13
d, wr, fifo_full, wr_clk, wr_rst,
q, rd, fifo_empty, rd_clk, rd_rst
);
cnt_gray_ce_bin
adr_gen
# ( .length(addr_width))
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
cnt_gray_ce_bin
adr_gen
# (.length(addr_width))
fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
vl_dpram_1r1w
vl_dual_port_ram_1r1w
# (.data_width(data_width), .addr_width(addr_width))
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
vl_fifo_cmp_async
1641,22 → 1561,22
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
cnt_gray_ce_bin
adr_gen
# ( .length(addr_width))
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
cnt_gray_ce_bin
adr_gen
# (.length(addr_width))
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
cnt_gray_ce_bin
adr_gen
# ( .length(addr_width))
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
cnt_gray_ce_bin
adr_gen
# (.length(addr_width))
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
vl_dp_ram_2r2w
vfifo_dual_port_ram_dc_dw
# (.data_width(data_width), .addr_width(addr_width+1))
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1663,7 → 1583,7
vl_fifo_async_cmp
# (.addr_width(addr_width))
cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
vl_fifo_async_cmp
versatile_fifo_async_cmp
# (.addr_width(addr_width))
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
endmodule
/verilog/versatile_library_altera.v
1263,22 → 1263,7
//// ////
//////////////////////////////////////////////////////////////////////
/// ROM
module vl_rom_init ( adr, q, clk);
parameter data_width = 32;
parameter addr_width = 8;
input [(addr_width-1):0] adr;
output reg [(data_width-1):0] q;
input clk;
reg [data_width-1:0] rom [(1<<addr_width)-1:0];
parameter memory_file = "vl_rom.vmem";
initial
begin
$readmemh(memory_file, rom);
end
always @ (posedge clk)
q <= rom[adr];
endmodule
module vl_rom ( adr, q, clk);
module vl_rom ( a, q, clk);
parameter data_width = 32;
parameter addr_width = 4;
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1298,11 → 1283,11
{32'h15000000},
{32'h15000000},
{32'h15000000}};
input [addr_width-1:0] adr;
input [addr_width-1:0] a;
output reg [data_width-1:0] q;
input clk;
always @ (posedge clk)
q <= data[adr];
q <= data[a];
endmodule
// Single port RAM
module vl_ram ( d, adr, we, q, clk);
1311,18 → 1296,9
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input we;
output reg [(data_width-1):0] q;
output reg [(data_width-1):0] q;
input clk;
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
always @ (posedge clk)
begin
if (we)
1330,38 → 1306,9
q <= ram[adr];
end
endmodule
module vl_ram_be ( d, adr, be, we, q, clk);
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input [(addr_width/4)-1:0] be;
input we;
output reg [(data_width-1):0] q;
input clk;
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
genvar i;
generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
always @ (posedge clk)
if (we & be[i])
ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
end
endgenerate
always @ (posedge clk)
q <= ram[adr];
endmodule
// Dual port RAM
// ACTEL FPGA should not use logic to handle rw collision
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
module vl_dual_port_ram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
1372,15 → 1319,6
input clk_a, clk_b;
reg [(addr_width-1):0] adr_b_reg;
reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
always @ (posedge clk_a)
if (we_a)
ram[adr_a] <= d_a;
1388,7 → 1326,7
adr_b_reg <= adr_b;
assign q_b = ram[adr_b_reg];
endmodule
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
module vl_dual_port_ram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
1400,15 → 1338,6
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
always @ (posedge clk_a)
begin
q_a <= ram[adr_a];
1418,7 → 1347,7
always @ (posedge clk_b)
q_b <= ram[adr_b];
endmodule
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
module vl_dual_port_ram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, d_b, we_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
1432,15 → 1361,6
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
always @ (posedge clk_a)
begin
q_a <= ram[adr_a];
1538,13 → 1458,13
d, wr, fifo_full, wr_clk, wr_rst,
q, rd, fifo_empty, rd_clk, rd_rst
);
cnt_gray_ce_bin
adr_gen
# ( .length(addr_width))
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
cnt_gray_ce_bin
adr_gen
# (.length(addr_width))
fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
vl_dpram_1r1w
vl_dual_port_ram_1r1w
# (.data_width(data_width), .addr_width(addr_width))
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
vl_fifo_cmp_async
1627,22 → 1547,22
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
cnt_gray_ce_bin
adr_gen
# ( .length(addr_width))
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
cnt_gray_ce_bin
adr_gen
# (.length(addr_width))
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
cnt_gray_ce_bin
adr_gen
# ( .length(addr_width))
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
cnt_gray_ce_bin
adr_gen
# (.length(addr_width))
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
vl_dp_ram_2r2w
vfifo_dual_port_ram_dc_dw
# (.data_width(data_width), .addr_width(addr_width+1))
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1649,7 → 1569,7
vl_fifo_async_cmp
# (.addr_width(addr_width))
cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
vl_fifo_async_cmp
versatile_fifo_async_cmp
# (.addr_width(addr_width))
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
endmodule
/verilog/memories.v
42,26 → 42,8
 
/// ROM
 
module vl_rom_init ( adr, q, clk);
parameter data_width = 32;
parameter addr_width = 8;
input [(addr_width-1):0] adr;
output reg [(data_width-1):0] q;
input clk;
reg [data_width-1:0] rom [(1<<addr_width)-1:0];
parameter memory_file = "vl_rom.vmem";
initial
begin
$readmemh(memory_file, rom);
end
always @ (posedge clk)
q <= rom[adr];
module vl_rom ( a, q, clk);
 
endmodule
 
module vl_rom ( adr, q, clk);
 
parameter data_width = 32;
parameter addr_width = 4;
 
83,12 → 65,12
{32'h15000000},
{32'h15000000}};
 
input [addr_width-1:0] adr;
input [addr_width-1:0] a;
output reg [data_width-1:0] q;
input clk;
 
always @ (posedge clk)
q <= data[adr];
q <= data[a];
 
endmodule
 
100,19 → 82,9
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input we;
output reg [(data_width-1):0] q;
output reg [(data_width-1):0] q;
input clk;
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
always @ (posedge clk)
begin
if (we)
122,42 → 94,6
 
endmodule
 
module vl_ram_be ( d, adr, be, we, q, clk);
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input [(addr_width/4)-1:0] be;
input we;
output reg [(data_width-1):0] q;
input clk;
 
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
 
genvar i;
generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
always @ (posedge clk)
if (we & be[i])
ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
end
endgenerate
 
always @ (posedge clk)
q <= ram[adr];
 
endmodule
 
 
// Dual port RAM
 
// ACTEL FPGA should not use logic to handle rw collision
167,7 → 103,7
`define SYN
`endif
 
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
module vl_dual_port_ram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
178,17 → 114,6
input clk_a, clk_b;
reg [(addr_width-1):0] adr_b_reg;
reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
 
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
 
always @ (posedge clk_a)
if (we_a)
ram[adr_a] <= d_a;
197,7 → 122,7
assign q_b = ram[adr_b_reg];
endmodule
 
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
module vl_dual_port_ram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
209,17 → 134,6
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
 
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
 
always @ (posedge clk_a)
begin
q_a <= ram[adr_a];
230,7 → 144,7
q_b <= ram[adr_b];
endmodule
 
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
module vl_dual_port_ram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, d_b, we_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
244,17 → 158,6
input clk_a, clk_b;
reg [(data_width-1):0] q_b;
reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
 
parameter init = 0;
parameter memory_file = "vl_ram.vmem";
generate if (init) begin : init_mem
initial
begin
$readmemh(memory_file, ram);
end
end
endgenerate
 
always @ (posedge clk_a)
begin
q_a <= ram[adr_a];
389,15 → 292,15
q, rd, fifo_empty, rd_clk, rd_rst
);
 
cnt_gray_ce_bin
adr_gen
# ( .length(addr_width))
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
cnt_gray_ce_bin
adr_gen
# (.length(addr_width))
fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
 
vl_dpram_1r1w
vl_dual_port_ram_1r1w
# (.data_width(data_width), .addr_width(addr_width))
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
 
407,7 → 310,7
 
endmodule
 
module vl_fifo_2r2w_async (
module vl_fifo_2r2w (
// a side
a_d, a_wr, a_fifo_full,
a_q, a_rd, a_fifo_empty,
455,7 → 358,7
endmodule
 
module vl_fifo_2r2w_async_simplex (
module vl_fifo_2r2w_simplex (
// a side
a_d, a_wr, a_fifo_full,
a_q, a_rd, a_fifo_empty,
495,19 → 398,19
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
 
cnt_gray_ce_bin
adr_gen
# ( .length(addr_width))
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
cnt_gray_ce_bin
adr_gen
# (.length(addr_width))
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
 
cnt_gray_ce_bin
adr_gen
# ( .length(addr_width))
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
cnt_gray_ce_bin
adr_gen
# (.length(addr_width))
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
 
515,7 → 418,7
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
 
vl_dp_ram_2r2w
vfifo_dual_port_ram_dc_dw
# (.data_width(data_width), .addr_width(addr_width+1))
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
524,7 → 427,7
# (.addr_width(addr_width))
cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
 
vl_fifo_async_cmp
versatile_fifo_async_cmp
# (.addr_width(addr_width))
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
 

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