URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
Compare Revisions
- This comparison shows the changes necessary to convert path
/versatile_library/trunk/rtl
- from Rev 82 to Rev 81
- ↔ Reverse comparison
Rev 82 → Rev 81
/verilog/versatile_library.v
4936,7 → 4936,6
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i; |
reg last_cyc; |
reg [3:0] counter; |
reg read_busy; |
|
always @ (posedge clk or posedge rst) |
if (rst) |
4944,15 → 4943,17
else |
last_cyc <= wbm_cyc_o; |
|
/* |
always @ (posedge clk or posedge rst) |
if (rst) |
read_busy <= 1'b0; |
read <= 1'b0; |
else |
if (read & !waitrequest) |
read_busy <= 1'b1; |
else if (wbm_ack_i & wbm_cti_o!=3'b010) |
read_busy <= 1'b0; |
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy; |
if (!last_cyc & wbm_cyc_o & !wbm_we_o) |
read <= 1'b1; |
else if (!waitrequest) |
read <= 1'b0; |
*/ |
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & counter!=4'd0; |
|
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010; |
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 : |
4959,7 → 4960,7
(wbm_bte_o==2'b10) ? 4'd8 : |
(wbm_bte_o==2'b11) ? 4'd16: |
4'd1; |
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest); |
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest); |
|
always @ (posedge clk or posedge rst) |
if (rst) begin |
4973,7 → 4974,7
end else if (!waitrequest & wbm_stb_o) begin |
counter <= counter - 4'd1; |
end |
end |
end |
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0; |
|
`define MODULE wb3wb3_bridge |
/verilog/versatile_library_actel.v
2148,27 → 2148,28
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i; |
reg last_cyc; |
reg [3:0] counter; |
reg read_busy; |
always @ (posedge clk or posedge rst) |
if (rst) |
last_cyc <= 1'b0; |
else |
last_cyc <= wbm_cyc_o; |
/* |
always @ (posedge clk or posedge rst) |
if (rst) |
read_busy <= 1'b0; |
read <= 1'b0; |
else |
if (read & !waitrequest) |
read_busy <= 1'b1; |
else if (wbm_ack_i & wbm_cti_o!=3'b010) |
read_busy <= 1'b0; |
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy; |
if (!last_cyc & wbm_cyc_o & !wbm_we_o) |
read <= 1'b1; |
else if (!waitrequest) |
read <= 1'b0; |
*/ |
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & counter!=4'd0; |
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010; |
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 : |
(wbm_bte_o==2'b10) ? 4'd8 : |
(wbm_bte_o==2'b11) ? 4'd16: |
4'd1; |
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest); |
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest); |
always @ (posedge clk or posedge rst) |
if (rst) begin |
counter <= 4'd0; |
2181,7 → 2182,7
end else if (!waitrequest & wbm_stb_o) begin |
counter <= counter - 4'd1; |
end |
end |
end |
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0; |
vl_wb3wb3_bridge wbwb3inst ( |
// wishbone slave side |
/verilog/wb.v
341,7 → 341,6
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i; |
reg last_cyc; |
reg [3:0] counter; |
reg read_busy; |
|
always @ (posedge clk or posedge rst) |
if (rst) |
349,15 → 348,17
else |
last_cyc <= wbm_cyc_o; |
|
/* |
always @ (posedge clk or posedge rst) |
if (rst) |
read_busy <= 1'b0; |
read <= 1'b0; |
else |
if (read & !waitrequest) |
read_busy <= 1'b1; |
else if (wbm_ack_i & wbm_cti_o!=3'b010) |
read_busy <= 1'b0; |
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy; |
if (!last_cyc & wbm_cyc_o & !wbm_we_o) |
read <= 1'b1; |
else if (!waitrequest) |
read <= 1'b0; |
*/ |
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & counter!=4'd0; |
|
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010; |
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 : |
364,7 → 365,7
(wbm_bte_o==2'b10) ? 4'd8 : |
(wbm_bte_o==2'b11) ? 4'd16: |
4'd1; |
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest); |
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest); |
|
always @ (posedge clk or posedge rst) |
if (rst) begin |
378,7 → 379,7
end else if (!waitrequest & wbm_stb_o) begin |
counter <= counter - 4'd1; |
end |
end |
end |
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0; |
|
`define MODULE wb3wb3_bridge |
/verilog/versatile_library_altera.v
2253,27 → 2253,28
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i; |
reg last_cyc; |
reg [3:0] counter; |
reg read_busy; |
always @ (posedge clk or posedge rst) |
if (rst) |
last_cyc <= 1'b0; |
else |
last_cyc <= wbm_cyc_o; |
/* |
always @ (posedge clk or posedge rst) |
if (rst) |
read_busy <= 1'b0; |
read <= 1'b0; |
else |
if (read & !waitrequest) |
read_busy <= 1'b1; |
else if (wbm_ack_i & wbm_cti_o!=3'b010) |
read_busy <= 1'b0; |
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy; |
if (!last_cyc & wbm_cyc_o & !wbm_we_o) |
read <= 1'b1; |
else if (!waitrequest) |
read <= 1'b0; |
*/ |
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & counter!=4'd0; |
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010; |
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 : |
(wbm_bte_o==2'b10) ? 4'd8 : |
(wbm_bte_o==2'b11) ? 4'd16: |
4'd1; |
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest); |
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest); |
always @ (posedge clk or posedge rst) |
if (rst) begin |
counter <= 4'd0; |
2286,7 → 2287,7
end else if (!waitrequest & wbm_stb_o) begin |
counter <= counter - 4'd1; |
end |
end |
end |
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0; |
vl_wb3wb3_bridge wbwb3inst ( |
// wishbone slave side |