URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
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- This comparison shows the changes necessary to convert path
/versatile_library/trunk
- from Rev 111 to Rev 110
- ↔ Reverse comparison
Rev 111 → Rev 110
/rtl/verilog/versatile_library.v
4344,7 → 4344,7
if (a_data_width==32 & b_data_width==16) begin : dpram_3216 |
logic [31:0] temp; |
`define MODULE dpram_be_2r2w |
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file)) |
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(memory_init), .memory_file(memory_file)) |
`undef MODULE |
dpram6464 ( |
.d_a(d_a), |
4374,7 → 4374,7
if (a_data_width==32 & b_data_width==64) begin : dpram_3264 |
logic [63:0] temp; |
`define MODULE dpram_be_2r2w |
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file)) |
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(memory_init), .memory_file(memory_file)) |
`undef MODULE |
dpram6464 ( |
.d_a({d_a,d_a}), |
/rtl/verilog/versatile_library_actel.v
1709,7 → 1709,7
generate |
if (a_data_width==32 & b_data_width==16) begin : dpram_3216 |
logic [31:0] temp; |
vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file)) |
vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(memory_init), .memory_file(memory_file)) |
dpram6464 ( |
.d_a(d_a), |
.q_a(q_a), |
1734,7 → 1734,7
generate |
if (a_data_width==32 & b_data_width==64) begin : dpram_3264 |
logic [63:0] temp; |
vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file)) |
vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(memory_init), .memory_file(memory_file)) |
dpram6464 ( |
.d_a({d_a,d_a}), |
.q_a(temp), |
/rtl/verilog/versatile_library_altera.v
1816,7 → 1816,7
generate |
if (a_data_width==32 & b_data_width==16) begin : dpram_3216 |
logic [31:0] temp; |
vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file)) |
vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(memory_init), .memory_file(memory_file)) |
dpram6464 ( |
.d_a(d_a), |
.q_a(q_a), |
1841,7 → 1841,7
generate |
if (a_data_width==32 & b_data_width==64) begin : dpram_3264 |
logic [63:0] temp; |
vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file)) |
vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(memory_init), .memory_file(memory_file)) |
dpram6464 ( |
.d_a({d_a,d_a}), |
.q_a(temp), |
/rtl/verilog/memories.v
575,7 → 575,7
if (a_data_width==32 & b_data_width==16) begin : dpram_3216 |
logic [31:0] temp; |
`define MODULE dpram_be_2r2w |
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file)) |
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(memory_init), .memory_file(memory_file)) |
`undef MODULE |
dpram6464 ( |
.d_a(d_a), |
605,7 → 605,7
if (a_data_width==32 & b_data_width==64) begin : dpram_3264 |
logic [63:0] temp; |
`define MODULE dpram_be_2r2w |
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file)) |
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(memory_init), .memory_file(memory_file)) |
`undef MODULE |
dpram6464 ( |
.d_a({d_a,d_a}), |