URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
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- This comparison shows the changes necessary to convert path
/versatile_library/trunk
- from Rev 13 to Rev 12
- ↔ Reverse comparison
Rev 13 → Rev 12
/rtl/verilog/versatile_library.v
2201,6 → 2201,7
parameter wbm_adr1 = 2'b01; |
parameter wbm_data = 2'b10; |
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reg wbs_we_reg; |
reg [1:0] wbs_bte_reg; |
reg wbs; |
wire wbs_eoc_alert, wbm_eoc_alert; |
2209,6 → 2210,9
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reg [1:16] wbs_count, wbm_count; |
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reg wbs_ack_o_rd; |
wire wbs_ack_o_wr; |
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wire [35:0] a_d, a_q, b_d, b_q; |
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty; |
reg a_rd_reg; |
2264,9 → 2268,9
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always @ (posedge wbs_clk or posedge wbs_rst) |
if (wbs_rst) |
wbs_bte_reg <= 2'b00; |
{wbs_we_reg,wbs_bte_reg} <= {1'b0,2'b00}; |
else |
wbs_bte_reg <= wbs_bte_i; |
{wbs_we_reg,wbs_bte_reg} <= {wbs_we_i,wbs_bte_i}; |
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// wbm FIFO |
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]); |
/rtl/verilog/versatile_library_actel.v
1765,6 → 1765,7
parameter wbm_adr0 = 2'b00; |
parameter wbm_adr1 = 2'b01; |
parameter wbm_data = 2'b10; |
reg wbs_we_reg; |
reg [1:0] wbs_bte_reg; |
reg wbs; |
wire wbs_eoc_alert, wbm_eoc_alert; |
1771,6 → 1772,8
reg wbs_eoc, wbm_eoc; |
reg [1:0] wbm; |
reg [1:16] wbs_count, wbm_count; |
reg wbs_ack_o_rd; |
wire wbs_ack_o_wr; |
wire [35:0] a_d, a_q, b_d, b_q; |
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty; |
reg a_rd_reg; |
1816,9 → 1819,9
assign wbs_dat_o = a_q[35:4]; |
always @ (posedge wbs_clk or posedge wbs_rst) |
if (wbs_rst) |
wbs_bte_reg <= 2'b00; |
{wbs_we_reg,wbs_bte_reg} <= {1'b0,2'b00}; |
else |
wbs_bte_reg <= wbs_bte_i; |
{wbs_we_reg,wbs_bte_reg} <= {wbs_we_i,wbs_bte_i}; |
// wbm FIFO |
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]); |
always @ (posedge wbm_clk or posedge wbm_rst) |
/rtl/verilog/wb.v
88,6 → 88,7
parameter wbm_adr1 = 2'b01; |
parameter wbm_data = 2'b10; |
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reg wbs_we_reg; |
reg [1:0] wbs_bte_reg; |
reg wbs; |
wire wbs_eoc_alert, wbm_eoc_alert; |
96,6 → 97,9
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reg [1:16] wbs_count, wbm_count; |
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reg wbs_ack_o_rd; |
wire wbs_ack_o_wr; |
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wire [35:0] a_d, a_q, b_d, b_q; |
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty; |
reg a_rd_reg; |
151,9 → 155,9
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always @ (posedge wbs_clk or posedge wbs_rst) |
if (wbs_rst) |
wbs_bte_reg <= 2'b00; |
{wbs_we_reg,wbs_bte_reg} <= {1'b0,2'b00}; |
else |
wbs_bte_reg <= wbs_bte_i; |
{wbs_we_reg,wbs_bte_reg} <= {wbs_we_i,wbs_bte_i}; |
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// wbm FIFO |
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]); |
/rtl/verilog/versatile_library_altera.v
1751,6 → 1751,7
parameter wbm_adr0 = 2'b00; |
parameter wbm_adr1 = 2'b01; |
parameter wbm_data = 2'b10; |
reg wbs_we_reg; |
reg [1:0] wbs_bte_reg; |
reg wbs; |
wire wbs_eoc_alert, wbm_eoc_alert; |
1757,6 → 1758,8
reg wbs_eoc, wbm_eoc; |
reg [1:0] wbm; |
reg [1:16] wbs_count, wbm_count; |
reg wbs_ack_o_rd; |
wire wbs_ack_o_wr; |
wire [35:0] a_d, a_q, b_d, b_q; |
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty; |
reg a_rd_reg; |
1802,9 → 1805,9
assign wbs_dat_o = a_q[35:4]; |
always @ (posedge wbs_clk or posedge wbs_rst) |
if (wbs_rst) |
wbs_bte_reg <= 2'b00; |
{wbs_we_reg,wbs_bte_reg} <= {1'b0,2'b00}; |
else |
wbs_bte_reg <= wbs_bte_i; |
{wbs_we_reg,wbs_bte_reg} <= {wbs_we_i,wbs_bte_i}; |
// wbm FIFO |
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]); |
always @ (posedge wbm_clk or posedge wbm_rst) |