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    /versatile_library/trunk
    from Rev 36 to Rev 35
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Rev 36 → Rev 35

/rtl/verilog/versatile_library.v
844,24 → 844,6
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module vl_mux_andor ( a, sel, dout);
 
parameter width = 32;
parameter nr_of_ports = 4;
 
input [nr_of_ports*width-1:0] a;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
 
always @ (a, sel)
begin
dout = a[width-1:0] & {width{sel[0]}};
for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
dout = (a[i*width-1:(i-1)*width] & {width{sel[i]}}) | dout;
end
 
endmodule
 
module vl_mux2_andor ( a1, a0, sel, dout);
 
parameter width = 32;
870,10 → 852,6
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
883,7 → 861,7
 
// or
assign dout = tmp[1] | tmp[0];
*/
 
endmodule
 
module vl_mux3_andor ( a2, a1, a0, sel, dout);
894,11 → 872,6
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
/*
 
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
909,7 → 882,7
 
// or
assign dout = tmp[2] | tmp[1] | tmp[0];
*/
 
endmodule
 
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
920,10 → 893,6
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
935,7 → 904,7
 
// or
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
 
endmodule
 
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
946,10 → 915,6
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
962,7 → 927,7
 
// or
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
 
endmodule
 
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
973,10 → 938,6
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
990,7 → 951,7
 
// or
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
 
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
/rtl/verilog/versatile_library_actel.v
437,19 → 437,6
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module vl_mux_andor ( a, sel, dout);
parameter width = 32;
parameter nr_of_ports = 4;
input [nr_of_ports*width-1:0] a;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
always @ (a, sel)
begin
dout = a[width-1:0] & {width{sel[0]}};
for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
dout = (a[i*width-1:(i-1)*width] & {width{sel[i]}}) | dout;
end
endmodule
module vl_mux2_andor ( a1, a0, sel, dout);
parameter width = 32;
localparam nr_of_ports = 2;
456,10 → 443,6
input [width-1:0] a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
467,7 → 450,6
assign tmp[1] = {width{sel[1]}} & a1;
// or
assign dout = tmp[1] | tmp[0];
*/
endmodule
module vl_mux3_andor ( a2, a1, a0, sel, dout);
parameter width = 32;
475,10 → 457,6
input [width-1:0] a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
487,7 → 465,6
assign tmp[2] = {width{sel[2]}} & a2;
// or
assign dout = tmp[2] | tmp[1] | tmp[0];
*/
endmodule
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
parameter width = 32;
495,10 → 472,6
input [width-1:0] a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
508,7 → 481,6
assign tmp[3] = {width{sel[3]}} & a3;
// or
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
endmodule
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
parameter width = 32;
516,10 → 488,6
input [width-1:0] a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
530,7 → 498,6
assign tmp[4] = {width{sel[4]}} & a4;
// or
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
endmodule
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
parameter width = 32;
538,10 → 505,6
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
553,7 → 516,6
assign tmp[5] = {width{sel[5]}} & a5;
// or
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
/rtl/verilog/versatile_library_altera.v
545,19 → 545,6
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module vl_mux_andor ( a, sel, dout);
parameter width = 32;
parameter nr_of_ports = 4;
input [nr_of_ports*width-1:0] a;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
always @ (a, sel)
begin
dout = a[width-1:0] & {width{sel[0]}};
for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
dout = (a[i*width-1:(i-1)*width] & {width{sel[i]}}) | dout;
end
endmodule
module vl_mux2_andor ( a1, a0, sel, dout);
parameter width = 32;
localparam nr_of_ports = 2;
564,10 → 551,6
input [width-1:0] a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
575,7 → 558,6
assign tmp[1] = {width{sel[1]}} & a1;
// or
assign dout = tmp[1] | tmp[0];
*/
endmodule
module vl_mux3_andor ( a2, a1, a0, sel, dout);
parameter width = 32;
583,10 → 565,6
input [width-1:0] a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
595,7 → 573,6
assign tmp[2] = {width{sel[2]}} & a2;
// or
assign dout = tmp[2] | tmp[1] | tmp[0];
*/
endmodule
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
parameter width = 32;
603,10 → 580,6
input [width-1:0] a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
616,7 → 589,6
assign tmp[3] = {width{sel[3]}} & a3;
// or
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
endmodule
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
parameter width = 32;
624,10 → 596,6
input [width-1:0] a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
638,7 → 606,6
assign tmp[4] = {width{sel[4]}} & a4;
// or
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
endmodule
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
parameter width = 32;
646,10 → 613,6
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
661,7 → 624,6
assign tmp[5] = {width{sel[5]}} & a5;
// or
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
/rtl/verilog/logic.v
39,24 → 39,6
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module vl_mux_andor ( a, sel, dout);
 
parameter width = 32;
parameter nr_of_ports = 4;
 
input [nr_of_ports*width-1:0] a;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
 
always @ (a, sel)
begin
dout = a[width-1:0] & {width{sel[0]}};
for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
dout = (a[i*width-1:(i-1)*width] & {width{sel[i]}}) | dout;
end
 
endmodule
 
module vl_mux2_andor ( a1, a0, sel, dout);
 
parameter width = 32;
65,10 → 47,6
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
78,7 → 56,7
 
// or
assign dout = tmp[1] | tmp[0];
*/
 
endmodule
 
module vl_mux3_andor ( a2, a1, a0, sel, dout);
89,11 → 67,6
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
/*
 
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
104,7 → 77,7
 
// or
assign dout = tmp[2] | tmp[1] | tmp[0];
*/
 
endmodule
 
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
115,10 → 88,6
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
130,7 → 99,7
 
// or
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
 
endmodule
 
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
141,10 → 110,6
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
157,7 → 122,7
 
// or
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
 
endmodule
 
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
168,10 → 133,6
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
185,5 → 146,5
 
// or
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
 
endmodule

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