URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
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/versatile_library/trunk
- from Rev 40 to Rev 39
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/rtl/verilog/versatile_counter_generator.php
File deleted
rtl/verilog/versatile_counter_generator.php
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: rtl/verilog/CSV.class.php
===================================================================
--- rtl/verilog/CSV.class.php (revision 40)
+++ rtl/verilog/CSV.class.php (nonexistent)
@@ -1,91 +0,0 @@
-file = fopen($fileName,'r');
-
- $this->parseHeader();
-
- }
-
- protected function getLine() {
-
- $line = fgetcsv($this->file);
-
- if($this->isEmpty($line)) {
- return false;
- } else {
- return $line;
- }
-
- }
-
- function parseHeader() {
-
- do {
-
- $this->header = $this->getLine();
-
- } while($this->header === false and !feof($this->file));
-
- return (count($this->header) > 0);
-
- }
-
- function getRow() {
-
- $array = $this->getLine();
-
- if($array === false) {
-
- return false;
-
- } else {
-
- $return = array();
-
- foreach($array as $key => $val) {
- $return[$this->header[$key]] = $val;
- }
-
- return $return;
-
- }
-
- }
-
- function getRows() {
-
- $return = array();
-
- while($row = $this->getRow()) {
- $return[] = $row;
- }
-
- return $return;
-
- }
-
- function isEmpty($row) {
- if($row === false or $row === array(null)) {
- return true;
- } else {
- foreach($row as $cur) {
- if(trim($cur) != '') {
- return false;
- }
- }
- return true;
- }
- }
-
- function __destruct() {
- fclose($this->file);
- }
-
-}
Index: rtl/verilog/defines.v
===================================================================
--- rtl/verilog/defines.v (revision 40)
+++ rtl/verilog/defines.v (nonexistent)
@@ -1,211 +0,0 @@
-`ifndef BASE
-`define BASE vl_
-`endif
-
-`ifdef ALL
-
-`define GBUF
-`define SYNC_RST
-`define PLL
-
-`define MULTS
-`define MULTS18X18
-`define MULT
-`define SHIFT_UNIT_32
-`define LOGIC_UNIT
-
-`define CNT_SHREG_WRAP
-`define CNT_SHREG_CE_WRAP
-`define CNT_SHREG_CE_CLEAR
-`define CNT_SHREG_CE_CLEAR_WRAP
-
-`define MUX_ANDOR
-`define MUX2_ANDOR
-`define MUX3_ANDOR
-`define MUX4_ANDOR
-`define MUX5_ANDOR
-`define MUX6_ANDOR
-
-`define ROM_INIT
-`define RAM
-`define RAM_BE
-`define DPRAM_1R1W
-`define DPRAM_2R1W
-`define DPRAM_2R2W
-`define FIFO_1R1W_FILL_LEVEL_SYNC
-`define FIFO_2R2W_SYNC_SIMPLEX
-`define FIFO_CMP_ASYNC
-`define FIFO_1R1W_ASYNC
-`define FIFO_2R2W_ASYNC
-`define FIFO_2R2W_ASYNC_SIMPLEX
-
-`define DFF
-`define DFF_ARRAY
-`define DFF_CE
-`define DFF_CE_CLEAR
-`define DF_CE_SET
-`define SPR
-`define SRP
-`define DFF_SR
-`define LATCH
-`define SHREG
-`define SHREG_CE
-`define DELAY
-`define DELAY_EMPTYFLAG
-
-`define WB3WB3_BRIDGE
-`define WB3_ARBITER_TYPE1
-`define WB_BOOT_ROM
-`define WB_DPRAM
-
-`endif
-
-`ifdef PLL
-`ifndef SYNC_RST
-`define SYNC_RST
-`endif
-`endif
-
-`ifdef SYNC_RST
-`ifndef GBUF
-`define GBUF
-`endif
-`endif
-
-`ifdef WB_DPRAM
-`ifndef DPRAM_2R2W
-`define DPRAM_2R2W
-`endif
-`ifndef SPR
-`define SPR
-`endif
-`endif
-
-`ifdef WB3_ARBITER_TYPE1
-`ifndef MUX_ANDOR
-`define MUX_ANDOR
-`endif
-`endif
-
-`ifdef WB3WB3_BRIDGE
-`ifndef CNT_SHREG_CE_CLEAR
-`define CNT_SHREG_CE_CLEAR
-`endif
-`ifndef DFF
-`define DFF
-`endif
-`ifndef DFF_CE
-`define DFF_CE
-`endif
-`ifndef CNT_SHREG_CE_CLEAR
-`define CNT_SHREG_CE_CLEAR
-`endif
-`ifndef FIFO_2R2W_ASYNC_SIMPLEX
-`define FIFO_2R2W_ASYNC_SIMPLEX
-`endif
-`endif
-
-`ifdef MULTS18X18
-`ifndef MULTS
-`define MULTS
-`endif
-`endif
-
-`ifdef SHIFT_UNIT_32
-`ifndef MULTS
-`define MULTS
-`endif
-`endif
-
-`ifdef MUX2_ANDOR
-`ifndef MUX_ANDOR
-`define MUX_ANDOR
-`endif
-`endif
-
-`ifdef MUX3_ANDOR
-`ifndef MUX_ANDOR
-`define MUX_ANDOR
-`endif
-`endif
-
-`ifdef MUX4_ANDOR
-`ifndef MUX_ANDOR
-`define MUX_ANDOR
-`endif
-`endif
-
-`ifdef MUX5_ANDOR
-`ifndef MUX_ANDOR
-`define MUX_ANDOR
-`endif
-`endif
-
-`ifdef MUX6_ANDOR
-`ifndef MUX_ANDOR
-`define MUX_ANDOR
-`endif
-`endif
-
-`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
-`ifndef CNT_BIN_CE
-`define CNT_BIN_CE
-`endif
-`ifndef DPRAM_1R1W
-`define DPRAM_1R1W
-`endif
-`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
-`define CNT_BIN_CE_REW_Q_ZQ_L1
-`endif
-`endif
-
-`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
-`ifndef CNT_LFSR_CE
-`define CNT_LFSR_CE
-`endif
-`ifndef DPRAM_2R2W
-`define DPRAM_2R2W
-`endif
-`ifndef CNT_BIN_CE_REW_ZQ_L1
-`define CNT_BIN_CE_REW_ZQ_L1
-`endif
-`endif
-
-`ifdef FIFO_2R2W_ASYNC_SIMPLEX
-`ifndef CNT_GRAY_CE_BIN
-`define CNT_GRAY_CE_BIN
-`endif
-`ifndef DPRAM_2R2W
-`define DPRAM_2R2W
-`endif
-`ifndef FIFO_CMP_ASYNC
-`define FIFO_CMP_ASYNC
-`endif
-`endif
-
-`ifdef FIFO_2R2W_ASYNC
-`ifndef FIFO_1R1W_ASYNC
-`define FIFO_1R1W_ASYNC
-`endif
-`endif
-
-`ifdef FIFO_1R1W_ASYNC
-`ifndef CNT_GRAY_CE_BIN
-`define CNT_GRAY_CE_BIN
-`endif
-`ifndef DPRAM_1R1W
-`define DPRAM_1R1W
-`endif
-`ifndef FIFO_CMP_ASYNC
-`define FIFO_CMP_ASYNC
-`endif
-`endif
-
-`ifdef FIFO_CMP_ASYNC
-`ifndef DFF_SR
-`define DFF_SR
-`endif
-`ifndef DFF
-`define DFF
-`endif
-`endif
Index: rtl/verilog/versatile_library.v
===================================================================
--- rtl/verilog/versatile_library.v (revision 40)
+++ rtl/verilog/versatile_library.v (revision 39)
@@ -1,214 +1,3 @@
-`ifndef BASE
-`define BASE vl_
-`endif
-
-`ifdef ALL
-
-`define GBUF
-`define SYNC_RST
-`define PLL
-
-`define MULTS
-`define MULTS18X18
-`define MULT
-`define SHIFT_UNIT_32
-`define LOGIC_UNIT
-
-`define CNT_SHREG_WRAP
-`define CNT_SHREG_CE_WRAP
-`define CNT_SHREG_CE_CLEAR
-`define CNT_SHREG_CE_CLEAR_WRAP
-
-`define MUX_ANDOR
-`define MUX2_ANDOR
-`define MUX3_ANDOR
-`define MUX4_ANDOR
-`define MUX5_ANDOR
-`define MUX6_ANDOR
-
-`define ROM_INIT
-`define RAM
-`define RAM_BE
-`define DPRAM_1R1W
-`define DPRAM_2R1W
-`define DPRAM_2R2W
-`define FIFO_1R1W_FILL_LEVEL_SYNC
-`define FIFO_2R2W_SYNC_SIMPLEX
-`define FIFO_CMP_ASYNC
-`define FIFO_1R1W_ASYNC
-`define FIFO_2R2W_ASYNC
-`define FIFO_2R2W_ASYNC_SIMPLEX
-
-`define DFF
-`define DFF_ARRAY
-`define DFF_CE
-`define DFF_CE_CLEAR
-`define DF_CE_SET
-`define SPR
-`define SRP
-`define DFF_SR
-`define LATCH
-`define SHREG
-`define SHREG_CE
-`define DELAY
-`define DELAY_EMPTYFLAG
-
-`define WB3WB3_BRIDGE
-`define WB3_ARBITER_TYPE1
-`define WB_BOOT_ROM
-`define WB_DPRAM
-
-`endif
-
-`ifdef PLL
-`ifndef SYNC_RST
-`define SYNC_RST
-`endif
-`endif
-
-`ifdef SYNC_RST
-`ifndef GBUF
-`define GBUF
-`endif
-`endif
-
-`ifdef WB_DPRAM
-`ifndef DPRAM_2R2W
-`define DPRAM_2R2W
-`endif
-`ifndef SPR
-`define SPR
-`endif
-`endif
-
-`ifdef WB3_ARBITER_TYPE1
-`ifndef MUX_ANDOR
-`define MUX_ANDOR
-`endif
-`endif
-
-`ifdef WB3WB3_BRIDGE
-`ifndef CNT_SHREG_CE_CLEAR
-`define CNT_SHREG_CE_CLEAR
-`endif
-`ifndef DFF
-`define DFF
-`endif
-`ifndef DFF_CE
-`define DFF_CE
-`endif
-`ifndef CNT_SHREG_CE_CLEAR
-`define CNT_SHREG_CE_CLEAR
-`endif
-`ifndef FIFO_2R2W_ASYNC_SIMPLEX
-`define FIFO_2R2W_ASYNC_SIMPLEX
-`endif
-`endif
-
-`ifdef MULTS18X18
-`ifndef MULTS
-`define MULTS
-`endif
-`endif
-
-`ifdef SHIFT_UNIT_32
-`ifndef MULTS
-`define MULTS
-`endif
-`endif
-
-`ifdef MUX2_ANDOR
-`ifndef MUX_ANDOR
-`define MUX_ANDOR
-`endif
-`endif
-
-`ifdef MUX3_ANDOR
-`ifndef MUX_ANDOR
-`define MUX_ANDOR
-`endif
-`endif
-
-`ifdef MUX4_ANDOR
-`ifndef MUX_ANDOR
-`define MUX_ANDOR
-`endif
-`endif
-
-`ifdef MUX5_ANDOR
-`ifndef MUX_ANDOR
-`define MUX_ANDOR
-`endif
-`endif
-
-`ifdef MUX6_ANDOR
-`ifndef MUX_ANDOR
-`define MUX_ANDOR
-`endif
-`endif
-
-`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
-`ifndef CNT_BIN_CE
-`define CNT_BIN_CE
-`endif
-`ifndef DPRAM_1R1W
-`define DPRAM_1R1W
-`endif
-`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
-`define CNT_BIN_CE_REW_Q_ZQ_L1
-`endif
-`endif
-
-`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
-`ifndef CNT_LFSR_CE
-`define CNT_LFSR_CE
-`endif
-`ifndef DPRAM_2R2W
-`define DPRAM_2R2W
-`endif
-`ifndef CNT_BIN_CE_REW_ZQ_L1
-`define CNT_BIN_CE_REW_ZQ_L1
-`endif
-`endif
-
-`ifdef FIFO_2R2W_ASYNC_SIMPLEX
-`ifndef CNT_GRAY_CE_BIN
-`define CNT_GRAY_CE_BIN
-`endif
-`ifndef DPRAM_2R2W
-`define DPRAM_2R2W
-`endif
-`ifndef FIFO_CMP_ASYNC
-`define FIFO_CMP_ASYNC
-`endif
-`endif
-
-`ifdef FIFO_2R2W_ASYNC
-`ifndef FIFO_1R1W_ASYNC
-`define FIFO_1R1W_ASYNC
-`endif
-`endif
-
-`ifdef FIFO_1R1W_ASYNC
-`ifndef CNT_GRAY_CE_BIN
-`define CNT_GRAY_CE_BIN
-`endif
-`ifndef DPRAM_1R1W
-`define DPRAM_1R1W
-`endif
-`ifndef FIFO_CMP_ASYNC
-`define FIFO_CMP_ASYNC
-`endif
-`endif
-
-`ifdef FIFO_CMP_ASYNC
-`ifndef DFF_SR
-`define DFF_SR
-`endif
-`ifndef DFF
-`define DFF
-`endif
-`endif
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile library, clock and reset ////
@@ -256,7 +45,7 @@
// use to enable global buffers for high fan out signals such as clock and reset
`ifdef ACTEL
-`ifdef GBUF
+
`timescale 1 ns/100 ps
// Version: 8.4 8.4.0.33
module gbuf(GL,CLK);
@@ -271,9 +60,7 @@
endmodule
`timescale 1 ns/1 ns
-`define MODULE gbuf
-module `BASE`MODULE ( i, o);
-`undef MODULE
+module vl_gbuf ( i, o);
input i;
output o;
`ifdef SIM_GBUF
@@ -282,45 +69,33 @@
gbuf gbuf_i0 ( .CLK(i), .GL(o));
`endif
endmodule
-`endif
`else
-`ifdef ALTERA
-`ifdef GBUF
+`ifdef ALTERA
//altera
-`define MODULE gbuf
-module `BASE`MODULE ( i, o);
-`undef MODULE
+module vl_gbuf ( i, o);
input i;
output o;
assign o = i;
endmodule
-`endif
`else
-`ifdef GBUF
`timescale 1 ns/100 ps
-`define MODULE
-module `BASE`MODULE ( i, o);
-`undef MODULE
+module vl_gbuf ( i, o);
input i;
output o;
assign o = i;
endmodule
-`endif
`endif // ALTERA
`endif //ACTEL
-`ifdef SYNC_RST
// sync reset
// input active lo async reset, normally from external reset generator and/or switch
// output active high global reset sync with two DFFs
`timescale 1 ns/100 ps
-`define MODULE sync_rst
-module `BASE`MODULE ( rst_n_i, rst_o, clk);
-`undef MODULE
+module vl_sync_rst ( rst_n_i, rst_o, clk);
input rst_n_i, clk;
output rst_o;
reg [1:0] tmp;
@@ -329,20 +104,14 @@
tmp <= 2'b11;
else
tmp <= {1'b0,tmp[1]};
-`define MODULE gbuf
-`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
-`undef MODULE
+vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
endmodule
-`endif
-`ifdef PLL
// vl_pll
`ifdef ACTEL
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
-`define MODULE pll
-module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
-`undef MODULE
+module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
parameter index = 0;
parameter number_of_clk = 1;
parameter period_time_0 = 20000;
@@ -432,9 +201,7 @@
genvar i;
generate for (i=0;i>1) ^ q_next;
endmodule
-`endif
-`ifdef CNT_GRAY_CE
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
@@ -2989,12 +2554,8 @@
//////////////////////////////////////////////////////////////////////
// GRAY counter
+module vl_cnt_gray_ce ( cke, q, rst, clk);
-`define MODULE cnt_gray_ce
-module `BASE`MODULE (
-`undef MODULE
- cke, q, rst, clk);
-
parameter length = 4;
input cke;
output reg [length:1] q;
@@ -3025,8 +2586,6 @@
q <= (q_next>>1) ^ q_next;
endmodule
-`endif
-`ifdef CNT_GRAY_CE_BIN
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
@@ -3070,12 +2629,8 @@
//////////////////////////////////////////////////////////////////////
// GRAY counter
+module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
-`define MODULE cnt_gray_ce_bin
-module `BASE`MODULE (
-`undef MODULE
- cke, q, q_bin, rst, clk);
-
parameter length = 4;
input cke;
output reg [length:1] q;
@@ -3109,7 +2664,6 @@
assign q_bin = qi;
endmodule
-`endif
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile library, counters ////
@@ -3152,10 +2706,7 @@
//// ////
//////////////////////////////////////////////////////////////////////
-`ifdef CNT_SHREG_WRAP
-`define MODULE cnt_shreg_wrap
-module `BASE`MODULE ( q, rst, clk);
-`undef MODULE
+module vl_cnt_shreg_wrap ( q, rst, clk);
parameter length = 4;
output reg [0:length-1] q;
@@ -3169,12 +2720,8 @@
q <= {q[length-1],q[0:length-2]};
endmodule
-`endif
-`ifdef CNT_SHREG_CE_WRAP
-`define MODULE cnt_shreg_ce_wrap
-module `BASE`MODULE ( cke, q, rst, clk);
-`undef MODULE
+module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
parameter length = 4;
input cke;
@@ -3190,12 +2737,8 @@
q <= {q[length-1],q[0:length-2]};
endmodule
-`endif
-`ifdef CNT_SHREG_CE_CLEAR
-`define MODULE cnt_shreg_ce_clear
-module `BASE`MODULE ( cke, clear, q, rst, clk);
-`undef MODULE
+module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
parameter length = 4;
input cke, clear;
@@ -3214,12 +2757,8 @@
q <= q >> 1;
endmodule
-`endif
-`ifdef CNT_SHREG_CE_CLEAR_WRAP
-`define MODULE cnt_shreg_ce_clear_wrap
-module `BASE`MODULE ( cke, clear, q, rst, clk);
-`undef MODULE
+module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
parameter length = 4;
input cke, clear;
@@ -3238,7 +2777,6 @@
q <= {q[length-1],q[0:length-2]};
endmodule
-`endif
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile library, memories ////
@@ -3281,12 +2819,9 @@
//// ////
//////////////////////////////////////////////////////////////////////
-`ifdef ROM_INIT
/// ROM
-`define MODULE rom_init
-module `BASE`MODULE ( adr, q, clk);
-`undef MODULE
+module vl_rom_init ( adr, q, clk);
parameter data_width = 32;
parameter addr_width = 8;
input [(addr_width-1):0] adr;
@@ -3303,7 +2838,6 @@
q <= rom[adr];
endmodule
-`endif
/*
module vl_rom ( adr, q, clk);
@@ -3338,13 +2872,9 @@
endmodule
*/
-
-`ifdef RAM
-`define MODULE ram
// Single port RAM
-module `BASE`MODULE ( d, adr, we, q, clk);
-`undef MODULE
+module vl_ram ( d, adr, we, q, clk);
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d;
@@ -3371,13 +2901,8 @@
end
endmodule
-`endif
-`ifdef RAM_BE
-`define MODULE ram_be
-module `BASE`MODULE ( d, adr, be, we, q, clk);
-`undef MODULE
-
+module vl_ram_be ( d, adr, be, we, q, clk);
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d;
@@ -3411,8 +2936,8 @@
q <= ram[adr];
endmodule
-`endif
+
// Dual port RAM
// ACTEL FPGA should not use logic to handle rw collision
@@ -3422,10 +2947,7 @@
`define SYN
`endif
-`ifdef DPRAM_1R1W
-`define MODULE dpram_1r1w
-module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
-`undef MODULE
+module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
@@ -3453,15 +2975,9 @@
always @ (posedge clk_b)
adr_b_reg <= adr_b;
assign q_b = ram[adr_b_reg];
-
endmodule
-`endif
-`ifdef DPRAM_2R1W
-`define MODULE dpram_2r1w
-module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
-`undef MODULE
-
+module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
@@ -3493,13 +3009,8 @@
always @ (posedge clk_b)
q_b <= ram[adr_b];
endmodule
-`endif
-`ifdef DPRAM_2R2W
-`define MODULE dpram_2r2w
-module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
-`undef MODULE
-
+module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
parameter data_width = 32;
parameter addr_width = 8;
input [(data_width-1):0] d_a;
@@ -3537,15 +3048,11 @@
ram[adr_b] <= d_b;
end
endmodule
-`endif
// Content addresable memory, CAM
-`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
// FIFO
-`define MODULE fifo_1r1w_fill_level_sync
-module `BASE`MODULE (
-`undef MODULE
+module vl_fifo_1r1w_fill_level_sync (
d, wr, fifo_full,
q, rd, fifo_empty,
fill_level,
@@ -3569,36 +3076,28 @@
wire [addr_width:1] wadr, radr;
-`define MODULE cnt_bin_ce
-`BASE`MODULE
+vl_cnt_bin_ce
# ( .length(addr_width))
fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
-`BASE`MODULE
+
+vl_cnt_bin_ce
# (.length(addr_width))
fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
-`undef MODULE
-`define MODULE dpram_1r1w
-`BASE`MODULE
+vl_dpram_1r1w
# (.data_width(data_width), .addr_width(addr_width))
dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
-`undef MODULE
-`define MODULE cnt_bin_ce_rew_q_zq_l1
-`BASE`MODULE
+vl_cnt_bin_ce_rew_q_zq_l1
# (.length(addr_width+1), .level1_value(1<
/rtl/verilog/versatile_library_actel.v
161,7 → 161,7
endgenerate // index==0 |
genvar i; |
generate for (i=0;i<number_of_clk;i=i+1) begin: clock |
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i])); |
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i])); |
end |
endgenerate |
endmodule |
332,7 → 332,7
endmodule |
// LATCH |
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1 |
module vl_latch ( d, le, q, clk); |
module latch ( d, le, q, clk); |
input d, le; |
output q; |
input clk;/* |
544,9 → 544,131
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce ( |
cke, q, rst, clk); |
module vl_cnt_bin ( q, rst, clk); |
parameter length = 4; |
output [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 0; |
parameter level1_value = 15; |
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = qi + {{length-1{1'b0}},1'b1}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
qi <= q_next; |
assign q = qi; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_clear ( clear, q, rst, clk); |
parameter length = 4; |
input clear; |
output [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 0; |
parameter level1_value = 15; |
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
qi <= q_next; |
assign q = qi; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce ( cke, q, rst, clk); |
parameter length = 4; |
input cke; |
output [length:1] q; |
input rst; |
608,11 → 730,311
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce_rew_zq_l1 ( |
cke, rew, zq, level1, rst, clk); |
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk); |
parameter length = 4; |
input clear; |
input cke; |
output [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 0; |
parameter level1_value = 15; |
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
assign q = qi; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk); |
parameter length = 4; |
input clear; |
input cke; |
output [length:1] q; |
output reg level1; |
output reg level2; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 15; |
parameter level1_value = 8; |
parameter level2_value = 15; |
wire rew; |
assign rew = 1'b0; |
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
assign q = qi; |
always @ (posedge clk or posedge rst) |
if (rst) |
level1 <= 1'b0; |
else |
if (cke) |
if (clear) |
level1 <= 1'b0; |
else if (q_next == level1_value) |
level1 <= 1'b1; |
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
always @ (posedge clk or posedge rst) |
if (rst) |
level2 <= 1'b0; |
else |
if (cke) |
if (clear) |
level2 <= 1'b0; |
else if (q_next == level2_value) |
level2 <= 1'b1; |
else if (qi == level2_value & rew) |
level2 <= 1'b0; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk); |
parameter length = 4; |
input clear; |
input set; |
input cke; |
input rew; |
output [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 0; |
parameter level1_value = 15; |
reg [length:1] qi; |
wire [length:1] q_next, q_next_fw, q_next_rew; |
assign q_next_fw = clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1}; |
assign q_next_rew = clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1}; |
assign q_next = rew ? q_next_rew : q_next_fw; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
assign q = qi; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk); |
parameter length = 4; |
input cke; |
input rew; |
output reg level1; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 1; |
parameter level1_value = 15; |
wire clear; |
assign clear = 1'b0; |
reg [length:1] qi; |
wire [length:1] q_next, q_next_fw, q_next_rew; |
assign q_next_fw = qi + {{length-1{1'b0}},1'b1}; |
assign q_next_rew = qi - {{length-1{1'b0}},1'b1}; |
assign q_next = rew ? q_next_rew : q_next_fw; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
always @ (posedge clk or posedge rst) |
if (rst) |
level1 <= 1'b0; |
else |
if (cke) |
if (clear) |
level1 <= 1'b0; |
else if (q_next == level1_value) |
level1 <= 1'b1; |
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk); |
parameter length = 4; |
input cke; |
input rew; |
output reg zq; |
output reg level1; |
input rst; |
694,8 → 1116,7
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce_rew_q_zq_l1 ( |
cke, rew, q, zq, level1, rst, clk); |
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk); |
parameter length = 4; |
input cke; |
input rew; |
781,12 → 1202,868
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_zq ( zq, rst, clk); |
parameter length = 4; |
output reg zq; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
reg lfsr_fb; |
wire [length:1] q_next; |
reg [32:1] polynom; |
integer i; |
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10010000000000000000; // 0x90000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
qi <= q_next; |
always @ (posedge clk or posedge rst) |
if (rst) |
zq <= 1'b1; |
else |
zq <= q_next == {length{1'b0}}; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk); |
parameter length = 4; |
input cke; |
output reg zq; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
reg lfsr_fb; |
wire [length:1] q_next; |
reg [32:1] polynom; |
integer i; |
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10010000000000000000; // 0x90000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
always @ (posedge clk or posedge rst) |
if (rst) |
zq <= 1'b1; |
else |
if (cke) |
zq <= q_next == {length{1'b0}}; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk); |
parameter length = 4; |
input cke; |
output [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
reg lfsr_fb; |
wire [length:1] q_next; |
reg [32:1] polynom; |
integer i; |
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10010000000000000000; // 0x90000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
assign q = qi; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk); |
parameter length = 4; |
input clear; |
input cke; |
output [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
reg lfsr_fb; |
wire [length:1] q_next; |
reg [32:1] polynom; |
integer i; |
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10010000000000000000; // 0x90000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next = clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
assign q = qi; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk); |
parameter length = 4; |
input cke; |
output [length:1] q; |
output reg zq; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
reg lfsr_fb; |
wire [length:1] q_next; |
reg [32:1] polynom; |
integer i; |
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10010000000000000000; // 0x90000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
assign q = qi; |
always @ (posedge clk or posedge rst) |
if (rst) |
zq <= 1'b1; |
else |
if (cke) |
zq <= q_next == {length{1'b0}}; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk); |
parameter length = 4; |
input cke; |
input rew; |
output reg level1; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
wire clear; |
assign clear = 1'b0; |
reg [length:1] qi; |
reg lfsr_fb, lfsr_fb_rew; |
wire [length:1] q_next, q_next_fw, q_next_rew; |
reg [32:1] polynom_rew; |
integer j; |
reg [32:1] polynom; |
integer i; |
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10010000000000000000; // 0x90000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next_fw = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
always @ (qi) |
begin |
case (length) |
2: polynom_rew = 32'b11; |
3: polynom_rew = 32'b110; |
4: polynom_rew = 32'b1100; |
5: polynom_rew = 32'b10100; |
6: polynom_rew = 32'b110000; |
7: polynom_rew = 32'b1100000; |
8: polynom_rew = 32'b10111000; |
9: polynom_rew = 32'b100010000; |
10: polynom_rew = 32'b1001000000; |
11: polynom_rew = 32'b10100000000; |
12: polynom_rew = 32'b100000101001; |
13: polynom_rew = 32'b1000000001100; |
14: polynom_rew = 32'b10000000010101; |
15: polynom_rew = 32'b110000000000000; |
16: polynom_rew = 32'b1101000000001000; |
17: polynom_rew = 32'b10010000000000000; |
18: polynom_rew = 32'b100000010000000000; |
19: polynom_rew = 32'b1000000000000100011; |
20: polynom_rew = 32'b10000010000000000000; |
21: polynom_rew = 32'b101000000000000000000; |
22: polynom_rew = 32'b1100000000000000000000; |
23: polynom_rew = 32'b10000100000000000000000; |
24: polynom_rew = 32'b111000010000000000000000; |
25: polynom_rew = 32'b1001000000000000000000000; |
26: polynom_rew = 32'b10000000000000000000100011; |
27: polynom_rew = 32'b100000000000000000000010011; |
28: polynom_rew = 32'b1100100000000000000000000000; |
29: polynom_rew = 32'b10100000000000000000000000000; |
30: polynom_rew = 32'b100000000000000000000000101001; |
31: polynom_rew = 32'b1001000000000000000000000000000; |
32: polynom_rew = 32'b10000000001000000000000000000011; |
default: polynom_rew = 32'b0; |
endcase |
// rotate left |
polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] }; |
lfsr_fb_rew = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom_rew[i]) |
lfsr_fb_rew = lfsr_fb_rew ~^ qi[i]; |
end |
end |
assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]}; |
assign q_next = rew ? q_next_rew : q_next_fw; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
always @ (posedge clk or posedge rst) |
if (rst) |
level1 <= 1'b0; |
else |
if (cke) |
if (clear) |
level1 <= 1'b0; |
else if (q_next == level1_value) |
level1 <= 1'b1; |
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// GRAY counter |
module vl_cnt_gray_ce_bin ( |
cke, q, q_bin, rst, clk); |
module vl_cnt_gray ( q, rst, clk); |
parameter length = 4; |
output reg [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = qi + {{length-1{1'b0}},1'b1}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
qi <= q_next; |
always @ (posedge clk or posedge rst) |
if (rst) |
q <= {length{1'b0}}; |
else |
q <= (q_next>>1) ^ q_next; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// GRAY counter |
module vl_cnt_gray_ce ( cke, q, rst, clk); |
parameter length = 4; |
input cke; |
output reg [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = qi + {{length-1{1'b0}},1'b1}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
always @ (posedge clk or posedge rst) |
if (rst) |
q <= {length{1'b0}}; |
else |
if (cke) |
q <= (q_next>>1) ^ q_next; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// GRAY counter |
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk); |
parameter length = 4; |
input cke; |
output reg [length:1] q; |
output [length:1] q_bin; |
input rst; |
input clk; |
/rtl/verilog/wb.v
40,12 → 40,9
//// //// |
////////////////////////////////////////////////////////////////////// |
|
`ifdef WB3WB3_BRIDGE |
// async wb3 - wb3 bridge |
`timescale 1ns/1ns |
`define MODULE wb3wb3_bridge |
module `BASE`MODULE ( |
`undef MODULE |
module vl_wb3wb3_bridge ( |
// wishbone slave side |
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst, |
// wishbone master side |
122,9 → 119,7
else if (wbs_eoc_alert & (a_rd | a_wr)) |
wbs_eoc <= 1'b1; |
|
`define MODULE cnt_shreg_ce_clear |
`BASE`MODULE # ( .length(16)) |
`undef MODULE |
vl_cnt_shreg_ce_clear # ( .length(16)) |
cnt0 ( |
.cke(wbs_ack_o), |
.clear(wbs_eoc), |
210,18 → 205,12
1'b0; |
assign b_rd = b_rd_adr | b_rd_data; |
|
`define MODULE dff |
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst)); |
`undef MODULE |
`define MODULE dff_ce |
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst)); |
`undef MODULE |
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst)); |
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst)); |
|
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp; |
|
`define MODULE cnt_shreg_ce_clear |
vl_cnt_shreg_ce_clear # ( .length(16)) |
`undef MODULE |
cnt1 ( |
.cke(wbm_ack_i), |
.clear(wbm_eoc), |
243,9 → 232,7
end |
|
//async_fifo_dw_simplex_top |
`define MODULE fifo_2r2w_async_simplex |
`BASE`MODULE |
`undef MODULE |
vl_fifo_2r2w_async_simplex |
# ( .data_width(36), .addr_width(addr_width)) |
fifo ( |
// a side |
269,15 → 256,8
); |
|
endmodule |
`undef WE |
`undef BTE |
`undef CTI |
`endif |
|
`ifdef WB3_ARBITER_TYPE1 |
`define MODULE wb3_arbiter_type1 |
module vl_wb3_arbiter_type1 ( |
`undef MODULE |
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, |
wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i, |
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, |
364,15 → 344,13
|
assign sel = select | state; |
|
`define MODULE mux_andor |
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i)); |
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i)); |
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i)); |
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i)); |
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i)); |
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i)); |
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i)); |
`undef MODULE |
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i)); |
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i)); |
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i)); |
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i)); |
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i)); |
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i)); |
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i)); |
assign wbs_cyc_i = |sel; |
|
assign wbm_dat_i = {nr_of_ports{wbs_dat_o}}; |
381,13 → 359,9
assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel; |
|
endmodule |
`endif |
|
`ifdef WB_BOOT_ROM |
// WB ROM |
`define MODULE wb_boot_rom |
module `BASE`MODULE ( |
`undef MODULE |
module vl_wb_boot_rom ( |
wb_adr_i, wb_stb_i, wb_cyc_i, |
wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst); |
|
448,12 → 422,8
assign wb_ack_o = wb_ack; |
|
endmodule |
`endif |
|
`ifdef WB_DPRAM |
`define MODULE wb_dpram |
module `BASE`MODULE ( |
`undef MODULE |
module vl_wb_dpram ( |
// wishbone slave side a |
wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o, |
wbsa_clk, wbsa_rst, |
483,9 → 453,7
|
wire wbsa_dat_tmp, wbsb_dat_tmp; |
|
`define MODULE dpram_2r2w |
`BASE`MODULE # ( |
`undef MODULE |
vl_dpram_2r2w # ( |
.data_width(data_width), .addr_width(addr_width) ) |
dpram0( |
.d_a(wbsa_dat_i), |
513,10 → 481,7
assign wbsb_dat_o = wbsb_dat_tmp; |
endgenerate |
|
`define MODULE spr |
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst)); |
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst)); |
`undef MODULE |
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst)); |
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst)); |
|
endmodule |
`endif |
/rtl/verilog/versatile_library_altera.v
179,7 → 179,7
`endif |
genvar i; |
generate for (i=0;i<number_of_clk;i=i+1) begin: clock |
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i])); |
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i])); |
end |
endgenerate |
endmodule |
652,9 → 652,131
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce ( |
cke, q, rst, clk); |
module vl_cnt_bin ( q, rst, clk); |
parameter length = 4; |
output [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 0; |
parameter level1_value = 15; |
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = qi + {{length-1{1'b0}},1'b1}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
qi <= q_next; |
assign q = qi; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_clear ( clear, q, rst, clk); |
parameter length = 4; |
input clear; |
output [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 0; |
parameter level1_value = 15; |
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
qi <= q_next; |
assign q = qi; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce ( cke, q, rst, clk); |
parameter length = 4; |
input cke; |
output [length:1] q; |
input rst; |
716,11 → 838,311
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce_rew_zq_l1 ( |
cke, rew, zq, level1, rst, clk); |
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk); |
parameter length = 4; |
input clear; |
input cke; |
output [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 0; |
parameter level1_value = 15; |
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
assign q = qi; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk); |
parameter length = 4; |
input clear; |
input cke; |
output [length:1] q; |
output reg level1; |
output reg level2; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 15; |
parameter level1_value = 8; |
parameter level2_value = 15; |
wire rew; |
assign rew = 1'b0; |
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
assign q = qi; |
always @ (posedge clk or posedge rst) |
if (rst) |
level1 <= 1'b0; |
else |
if (cke) |
if (clear) |
level1 <= 1'b0; |
else if (q_next == level1_value) |
level1 <= 1'b1; |
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
always @ (posedge clk or posedge rst) |
if (rst) |
level2 <= 1'b0; |
else |
if (cke) |
if (clear) |
level2 <= 1'b0; |
else if (q_next == level2_value) |
level2 <= 1'b1; |
else if (qi == level2_value & rew) |
level2 <= 1'b0; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk); |
parameter length = 4; |
input clear; |
input set; |
input cke; |
input rew; |
output [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 0; |
parameter level1_value = 15; |
reg [length:1] qi; |
wire [length:1] q_next, q_next_fw, q_next_rew; |
assign q_next_fw = clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1}; |
assign q_next_rew = clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1}; |
assign q_next = rew ? q_next_rew : q_next_fw; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
assign q = qi; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk); |
parameter length = 4; |
input cke; |
input rew; |
output reg level1; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 1; |
parameter level1_value = 15; |
wire clear; |
assign clear = 1'b0; |
reg [length:1] qi; |
wire [length:1] q_next, q_next_fw, q_next_rew; |
assign q_next_fw = qi + {{length-1{1'b0}},1'b1}; |
assign q_next_rew = qi - {{length-1{1'b0}},1'b1}; |
assign q_next = rew ? q_next_rew : q_next_fw; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
always @ (posedge clk or posedge rst) |
if (rst) |
level1 <= 1'b0; |
else |
if (cke) |
if (clear) |
level1 <= 1'b0; |
else if (q_next == level1_value) |
level1 <= 1'b1; |
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk); |
parameter length = 4; |
input cke; |
input rew; |
output reg zq; |
output reg level1; |
input rst; |
802,8 → 1224,7
//// //// |
////////////////////////////////////////////////////////////////////// |
// binary counter |
module vl_cnt_bin_ce_rew_q_zq_l1 ( |
cke, rew, q, zq, level1, rst, clk); |
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk); |
parameter length = 4; |
input cke; |
input rew; |
889,12 → 1310,868
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_zq ( zq, rst, clk); |
parameter length = 4; |
output reg zq; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
reg lfsr_fb; |
wire [length:1] q_next; |
reg [32:1] polynom; |
integer i; |
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10010000000000000000; // 0x90000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
qi <= q_next; |
always @ (posedge clk or posedge rst) |
if (rst) |
zq <= 1'b1; |
else |
zq <= q_next == {length{1'b0}}; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk); |
parameter length = 4; |
input cke; |
output reg zq; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
reg lfsr_fb; |
wire [length:1] q_next; |
reg [32:1] polynom; |
integer i; |
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10010000000000000000; // 0x90000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
always @ (posedge clk or posedge rst) |
if (rst) |
zq <= 1'b1; |
else |
if (cke) |
zq <= q_next == {length{1'b0}}; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk); |
parameter length = 4; |
input cke; |
output [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
reg lfsr_fb; |
wire [length:1] q_next; |
reg [32:1] polynom; |
integer i; |
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10010000000000000000; // 0x90000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
assign q = qi; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk); |
parameter length = 4; |
input clear; |
input cke; |
output [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
reg lfsr_fb; |
wire [length:1] q_next; |
reg [32:1] polynom; |
integer i; |
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10010000000000000000; // 0x90000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next = clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
assign q = qi; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk); |
parameter length = 4; |
input cke; |
output [length:1] q; |
output reg zq; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
reg lfsr_fb; |
wire [length:1] q_next; |
reg [32:1] polynom; |
integer i; |
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10010000000000000000; // 0x90000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
assign q = qi; |
always @ (posedge clk or posedge rst) |
if (rst) |
zq <= 1'b1; |
else |
if (cke) |
zq <= q_next == {length{1'b0}}; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// LFSR counter |
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk); |
parameter length = 4; |
input cke; |
input rew; |
output reg level1; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
wire clear; |
assign clear = 1'b0; |
reg [length:1] qi; |
reg lfsr_fb, lfsr_fb_rew; |
wire [length:1] q_next, q_next_fw, q_next_rew; |
reg [32:1] polynom_rew; |
integer j; |
reg [32:1] polynom; |
integer i; |
always @ (qi) |
begin |
case (length) |
2: polynom = 32'b11; // 0x3 |
3: polynom = 32'b110; // 0x6 |
4: polynom = 32'b1100; // 0xC |
5: polynom = 32'b10100; // 0x14 |
6: polynom = 32'b110000; // 0x30 |
7: polynom = 32'b1100000; // 0x60 |
8: polynom = 32'b10111000; // 0xb8 |
9: polynom = 32'b100010000; // 0x110 |
10: polynom = 32'b1001000000; // 0x240 |
11: polynom = 32'b10100000000; // 0x500 |
12: polynom = 32'b100000101001; // 0x829 |
13: polynom = 32'b1000000001100; // 0x100C |
14: polynom = 32'b10000000010101; // 0x2015 |
15: polynom = 32'b110000000000000; // 0x6000 |
16: polynom = 32'b1101000000001000; // 0xD008 |
17: polynom = 32'b10010000000000000; // 0x12000 |
18: polynom = 32'b100000010000000000; // 0x20400 |
19: polynom = 32'b1000000000000100011; // 0x40023 |
20: polynom = 32'b10010000000000000000; // 0x90000 |
21: polynom = 32'b101000000000000000000; // 0x140000 |
22: polynom = 32'b1100000000000000000000; // 0x300000 |
23: polynom = 32'b10000100000000000000000; // 0x420000 |
24: polynom = 32'b111000010000000000000000; // 0xE10000 |
25: polynom = 32'b1001000000000000000000000; // 0x1200000 |
26: polynom = 32'b10000000000000000000100011; // 0x2000023 |
27: polynom = 32'b100000000000000000000010011; // 0x4000013 |
28: polynom = 32'b1100100000000000000000000000; // 0xC800000 |
29: polynom = 32'b10100000000000000000000000000; // 0x14000000 |
30: polynom = 32'b100000000000000000000000101001; // 0x20000029 |
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000 |
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003 |
default: polynom = 32'b0; |
endcase |
lfsr_fb = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom[i]) |
lfsr_fb = lfsr_fb ~^ qi[i]; |
end |
end |
assign q_next_fw = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb}; |
always @ (qi) |
begin |
case (length) |
2: polynom_rew = 32'b11; |
3: polynom_rew = 32'b110; |
4: polynom_rew = 32'b1100; |
5: polynom_rew = 32'b10100; |
6: polynom_rew = 32'b110000; |
7: polynom_rew = 32'b1100000; |
8: polynom_rew = 32'b10111000; |
9: polynom_rew = 32'b100010000; |
10: polynom_rew = 32'b1001000000; |
11: polynom_rew = 32'b10100000000; |
12: polynom_rew = 32'b100000101001; |
13: polynom_rew = 32'b1000000001100; |
14: polynom_rew = 32'b10000000010101; |
15: polynom_rew = 32'b110000000000000; |
16: polynom_rew = 32'b1101000000001000; |
17: polynom_rew = 32'b10010000000000000; |
18: polynom_rew = 32'b100000010000000000; |
19: polynom_rew = 32'b1000000000000100011; |
20: polynom_rew = 32'b10000010000000000000; |
21: polynom_rew = 32'b101000000000000000000; |
22: polynom_rew = 32'b1100000000000000000000; |
23: polynom_rew = 32'b10000100000000000000000; |
24: polynom_rew = 32'b111000010000000000000000; |
25: polynom_rew = 32'b1001000000000000000000000; |
26: polynom_rew = 32'b10000000000000000000100011; |
27: polynom_rew = 32'b100000000000000000000010011; |
28: polynom_rew = 32'b1100100000000000000000000000; |
29: polynom_rew = 32'b10100000000000000000000000000; |
30: polynom_rew = 32'b100000000000000000000000101001; |
31: polynom_rew = 32'b1001000000000000000000000000000; |
32: polynom_rew = 32'b10000000001000000000000000000011; |
default: polynom_rew = 32'b0; |
endcase |
// rotate left |
polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] }; |
lfsr_fb_rew = qi[length]; |
for (i=length-1; i>=1; i=i-1) begin |
if (polynom_rew[i]) |
lfsr_fb_rew = lfsr_fb_rew ~^ qi[i]; |
end |
end |
assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]}; |
assign q_next = rew ? q_next_rew : q_next_fw; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
always @ (posedge clk or posedge rst) |
if (rst) |
level1 <= 1'b0; |
else |
if (cke) |
if (clear) |
level1 <= 1'b0; |
else if (q_next == level1_value) |
level1 <= 1'b1; |
else if (qi == level1_value & rew) |
level1 <= 1'b0; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// GRAY counter |
module vl_cnt_gray_ce_bin ( |
cke, q, q_bin, rst, clk); |
module vl_cnt_gray ( q, rst, clk); |
parameter length = 4; |
output reg [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = qi + {{length-1{1'b0}},1'b1}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
qi <= q_next; |
always @ (posedge clk or posedge rst) |
if (rst) |
q <= {length{1'b0}}; |
else |
q <= (q_next>>1) ^ q_next; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// GRAY counter |
module vl_cnt_gray_ce ( cke, q, rst, clk); |
parameter length = 4; |
input cke; |
output reg [length:1] q; |
input rst; |
input clk; |
parameter clear_value = 0; |
parameter set_value = 1; |
parameter wrap_value = 8; |
parameter level1_value = 15; |
reg [length:1] qi; |
wire [length:1] q_next; |
assign q_next = qi + {{length-1{1'b0}},1'b1}; |
always @ (posedge clk or posedge rst) |
if (rst) |
qi <= {length{1'b0}}; |
else |
if (cke) |
qi <= q_next; |
always @ (posedge clk or posedge rst) |
if (rst) |
q <= {length{1'b0}}; |
else |
if (cke) |
q <= (q_next>>1) ^ q_next; |
endmodule |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// GRAY counter |
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk); |
parameter length = 4; |
input cke; |
output reg [length:1] q; |
output [length:1] q_bin; |
input rst; |
input clk; |
/rtl/verilog/logic.v
39,10 → 39,7
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
`ifdef MUX_ANDOR |
`define MODULE mux_andor |
module `BASE`MODULE ( a, sel, dout); |
`undef MODULE |
module vl_mux_andor ( a, sel, dout); |
|
parameter width = 32; |
parameter nr_of_ports = 4; |
62,12 → 59,8
end |
|
endmodule |
`endif |
|
`ifdef MUX2_ANDOR |
`define MODULE mux2_andor |
module `BASE`MODULE ( a1, a0, sel, dout); |
`undef MODULE |
module vl_mux2_andor ( a1, a0, sel, dout); |
|
parameter width = 32; |
localparam nr_of_ports = 2; |
75,19 → 68,13
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
|
`define MODULE mux_andor |
`BASE`MODULE |
vl_mux_andor |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a1,a0}), .sel(sel), .dout(dout)); |
`undef MODULE |
|
|
endmodule |
`endif |
|
`ifdef MUX3_ANDOR |
`define MODULE mux3_andor |
module `BASE`MODULE ( a2, a1, a0, sel, dout); |
`undef MODULE |
module vl_mux3_andor ( a2, a1, a0, sel, dout); |
|
parameter width = 32; |
localparam nr_of_ports = 3; |
95,18 → 82,13
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
|
`define MODULE mux_andor |
`BASE`MODULE |
vl_mux_andor |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout)); |
`undef MODULE |
|
endmodule |
`endif |
|
`ifdef MUX4_ANDOR |
`define MODULE mux4_andor |
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout); |
`undef MODULE |
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout); |
|
parameter width = 32; |
localparam nr_of_ports = 4; |
114,19 → 96,13
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
|
`define MODULE mux_andor |
`BASE`MODULE |
vl_mux_andor |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout)); |
`undef MODULE |
|
endmodule |
`endif |
|
`ifdef MUX5_ANDOR |
`define MODULE mux5_andor |
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout); |
`undef MODULE |
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout); |
|
parameter width = 32; |
localparam nr_of_ports = 5; |
134,19 → 110,13
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
|
`define MODULE mux_andor |
`BASE`MODULE |
vl_mux_andor |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout)); |
`undef MODULE |
|
endmodule |
`endif |
|
`ifdef MUX6_ANDOR |
`define MODULE mux6_andor |
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout); |
`undef MODULE |
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout); |
|
parameter width = 32; |
localparam nr_of_ports = 6; |
154,11 → 124,8
input [nr_of_ports-1:0] sel; |
output [width-1:0] dout; |
|
`define MODULE mux_andor |
`BASE`MODULE |
vl_mux_andor |
# ( .width(width), .nr_of_ports(nr_of_ports)) |
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout)); |
`undef MODULE |
|
endmodule |
`endif |
/rtl/verilog/Makefile
1,5 → 1,4
VERILOG_FILES = defines.v |
VERILOG_FILES += clk_and_reset.v |
VERILOG_FILES = clk_and_reset.v |
VERILOG_FILES += registers.v |
VERILOG_FILES += logic.v |
|
31,9 → 30,11
VERSATILE_LIBRARIES = versatile_library.v |
VERSATILE_LIBRARIES += versatile_library_actel.v |
VERSATILE_LIBRARIES += versatile_library_altera.v |
OUT_FILE ?= custom.v |
VERSATILE_LIBRARIES += $(OUT_FILE) |
|
svn_export: |
svn export http://opencores.org/ocsvn/versatile_counter/versatile_counter/trunk/rtl/verilog/versatile_counter_generator.php |
svn export http://opencores.org/ocsvn/versatile_counter/versatile_counter/trunk/rtl/verilog/CSV.class.php |
|
#.PHONY: $(VERILOG_FILES_CNT) |
$(VERILOG_FILES_CNT): |
./versatile_counter_generator.php cnt_bin.csv > vl_cnt_bin.v |
59,15 → 60,11
cat $(VERILOG_FILES) | sed -r -e 's/\/\/E2_([a-z]+)/`\1/' > versatile_library.v |
|
versatile_library_actel.v: $(VERILOG_FILES) |
vppreproc --noline --noblank +define+ACTEL +define+ALL $(VERILOG_FILES) | sed -r -e 's/\/\/E2_([a-z]+)/`\1/' > versatile_library_actel.v |
vppreproc --noline --noblank +define+ACTEL $(VERILOG_FILES) | sed -r -e 's/\/\/E2_([a-z]+)/`\1/' > versatile_library_actel.v |
|
versatile_library_altera.v: $(VERILOG_FILES) |
vppreproc --noline --noblank +define+ALTERA +define+ALL $(VERILOG_FILES) | sed -r -e 's/\/\/E2_([a-z]+)/`\1/' > versatile_library_altera.v |
|
$(OUT_FILE): $(VERILOG_FILES) |
vppreproc --noline --noblank $(DEFINE_FILE) $(VERILOG_FILES) | sed -r -e 's/\/\/E2_([a-z]+)/`\1/' > $(OUT_FILE) |
vppreproc --noline --noblank +define+ALTERA $(VERILOG_FILES) | sed -r -e 's/\/\/E2_([a-z]+)/`\1/' > versatile_library_altera.v |
|
|
all: $(VERSATILE_LIBRARIES) |
|
clean: |
/rtl/verilog/clk_and_reset.v
45,7 → 45,7
// use to enable global buffers for high fan out signals such as clock and reset |
|
`ifdef ACTEL |
`ifdef GBUF |
|
`timescale 1 ns/100 ps |
// Version: 8.4 8.4.0.33 |
module gbuf(GL,CLK); |
60,9 → 60,7
|
endmodule |
`timescale 1 ns/1 ns |
`define MODULE gbuf |
module `BASE`MODULE ( i, o); |
`undef MODULE |
module vl_gbuf ( i, o); |
input i; |
output o; |
//E2_ifdef SIM_GBUF |
71,45 → 69,33
gbuf gbuf_i0 ( .CLK(i), .GL(o)); |
//E2_endif |
endmodule |
`endif |
|
`else |
|
`ifdef ALTERA |
`ifdef GBUF |
`ifdef ALTERA |
//altera |
`define MODULE gbuf |
module `BASE`MODULE ( i, o); |
`undef MODULE |
module vl_gbuf ( i, o); |
input i; |
output o; |
assign o = i; |
endmodule |
`endif |
|
`else |
|
`ifdef GBUF |
`timescale 1 ns/100 ps |
`define MODULE |
module `BASE`MODULE ( i, o); |
`undef MODULE |
module vl_gbuf ( i, o); |
input i; |
output o; |
assign o = i; |
endmodule |
`endif |
`endif // ALTERA |
`endif //ACTEL |
|
`ifdef SYNC_RST |
// sync reset |
// input active lo async reset, normally from external reset generator and/or switch |
// output active high global reset sync with two DFFs |
`timescale 1 ns/100 ps |
`define MODULE sync_rst |
module `BASE`MODULE ( rst_n_i, rst_o, clk); |
`undef MODULE |
module vl_sync_rst ( rst_n_i, rst_o, clk); |
input rst_n_i, clk; |
output rst_o; |
reg [1:0] tmp; |
118,20 → 104,14
tmp <= 2'b11; |
else |
tmp <= {1'b0,tmp[1]}; |
`define MODULE gbuf |
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o)); |
`undef MODULE |
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o)); |
endmodule |
`endif |
|
`ifdef PLL |
// vl_pll |
`ifdef ACTEL |
/////////////////////////////////////////////////////////////////////////////// |
`timescale 1 ps/1 ps |
`define MODULE pll |
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o); |
`undef MODULE |
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o); |
parameter index = 0; |
parameter number_of_clk = 1; |
parameter period_time_0 = 20000; |
221,9 → 201,7
|
genvar i; |
generate for (i=0;i<number_of_clk;i=i+1) begin: clock |
`define MODULE sync_rst |
`BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i])); |
`undef MODULE |
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i])); |
end |
endgenerate |
endmodule |
236,9 → 214,7
`ifdef ALTERA |
|
`timescale 1 ps/1 ps |
`define MODULE pll |
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o); |
`undef MODULE |
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o); |
parameter index = 0; |
parameter number_of_clk = 1; |
parameter period_time_0 = 20000; |
363,9 → 339,7
|
genvar i; |
generate for (i=0;i<number_of_clk;i=i+1) begin: clock |
`define MODULE sync_rst |
`BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i])); |
`undef MODULE |
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i])); |
end |
endgenerate |
endmodule |
376,9 → 350,7
|
// generic PLL |
`timescale 1 ps/1 ps |
`define MODULE pll |
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o); |
`undef MODULE |
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o); |
parameter index = 0; |
parameter number_of_clk = 1; |
parameter period_time_0 = 20000; |
405,9 → 377,7
|
genvar i; |
generate for (i=0;i<number_of_clk;i=i+1) begin: clock |
`define MODULE sync_rst |
`BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i])); |
`undef MODULE |
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i])); |
end |
endgenerate |
|
417,5 → 387,3
|
`endif //altera |
`endif //actel |
`undef MODULE |
`endif |
/rtl/verilog/cnt_lfsr_ce_q_zq.csv
1,5 → 1,5
Name,type,,,, |
cnt_lfsr_ce_q_zq,LFSR,,,, |
vl_cnt_lfsr_ce_q_zq,LFSR,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,1,0,, |
/rtl/verilog/memories.v
40,12 → 40,9
//// //// |
////////////////////////////////////////////////////////////////////// |
|
`ifdef ROM_INIT |
/// ROM |
`define MODULE rom_init |
module `BASE`MODULE ( adr, q, clk); |
`undef MODULE |
|
module vl_rom_init ( adr, q, clk); |
parameter data_width = 32; |
parameter addr_width = 8; |
input [(addr_width-1):0] adr; |
62,7 → 59,6
q <= rom[adr]; |
|
endmodule |
`endif |
|
/* |
module vl_rom ( adr, q, clk); |
97,13 → 93,9
|
endmodule |
*/ |
|
`ifdef RAM |
`define MODULE ram |
// Single port RAM |
module `BASE`MODULE ( d, adr, we, q, clk); |
`undef MODULE |
|
module vl_ram ( d, adr, we, q, clk); |
parameter data_width = 32; |
parameter addr_width = 8; |
input [(data_width-1):0] d; |
130,13 → 122,8
end |
|
endmodule |
`endif |
|
`ifdef RAM_BE |
`define MODULE ram_be |
module `BASE`MODULE ( d, adr, be, we, q, clk); |
`undef MODULE |
|
module vl_ram_be ( d, adr, be, we, q, clk); |
parameter data_width = 32; |
parameter addr_width = 8; |
input [(data_width-1):0] d; |
170,8 → 157,8
q <= ram[adr]; |
|
endmodule |
`endif |
|
|
// Dual port RAM |
|
// ACTEL FPGA should not use logic to handle rw collision |
181,10 → 168,7
`define SYN |
`endif |
|
`ifdef DPRAM_1R1W |
`define MODULE dpram_1r1w |
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b ); |
`undef MODULE |
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b ); |
parameter data_width = 32; |
parameter addr_width = 8; |
input [(data_width-1):0] d_a; |
212,15 → 196,9
always @ (posedge clk_b) |
adr_b_reg <= adr_b; |
assign q_b = ram[adr_b_reg]; |
|
endmodule |
`endif |
|
`ifdef DPRAM_2R1W |
`define MODULE dpram_2r1w |
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b ); |
`undef MODULE |
|
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b ); |
parameter data_width = 32; |
parameter addr_width = 8; |
input [(data_width-1):0] d_a; |
252,13 → 230,8
always @ (posedge clk_b) |
q_b <= ram[adr_b]; |
endmodule |
`endif |
|
`ifdef DPRAM_2R2W |
`define MODULE dpram_2r2w |
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b ); |
`undef MODULE |
|
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b ); |
parameter data_width = 32; |
parameter addr_width = 8; |
input [(data_width-1):0] d_a; |
296,15 → 269,11
ram[adr_b] <= d_b; |
end |
endmodule |
`endif |
|
// Content addresable memory, CAM |
|
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC |
// FIFO |
`define MODULE fifo_1r1w_fill_level_sync |
module `BASE`MODULE ( |
`undef MODULE |
module vl_fifo_1r1w_fill_level_sync ( |
d, wr, fifo_full, |
q, rd, fifo_empty, |
fill_level, |
328,36 → 297,28
|
wire [addr_width:1] wadr, radr; |
|
`define MODULE cnt_bin_ce |
`BASE`MODULE |
vl_cnt_bin_ce |
# ( .length(addr_width)) |
fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk)); |
`BASE`MODULE |
|
vl_cnt_bin_ce |
# (.length(addr_width)) |
fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk)); |
`undef MODULE |
|
`define MODULE dpram_1r1w |
`BASE`MODULE |
vl_dpram_1r1w |
# (.data_width(data_width), .addr_width(addr_width)) |
dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk)); |
`undef MODULE |
|
`define MODULE cnt_bin_ce_rew_q_zq_l1 |
`BASE`MODULE |
vl_cnt_bin_ce_rew_q_zq_l1 |
# (.length(addr_width+1), .level1_value(1<<addr_width)) |
fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk)); |
`undef MODULE |
|
endmodule |
`endif |
|
`ifdef FIFO_2R2W_SYNC_SIMPLEX |
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource |
// RAM is supposed to be larger than the two FIFOs |
// LFSR counters used adr pointers |
`define MODULE fifo_2r2w_sync_simplex |
module `BASE`MODULE ( |
`undef MODULE |
module vl_fifo_2r2w_sync_simplex ( |
// a side |
a_d, a_wr, a_fifo_full, |
a_q, a_rd, a_fifo_empty, |
400,52 → 361,42
// dpram |
wire [addr_width:0] a_dpram_adr, b_dpram_adr; |
|
`define MODULE cnt_lfsr_ce |
`BASE`MODULE |
vl_cnt_lfsr_ce |
# ( .length(addr_width)) |
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk)); |
|
`BASE`MODULE |
vl_cnt_lfsr_ce |
# (.length(addr_width)) |
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk)); |
|
`BASE`MODULE |
vl_cnt_lfsr_ce |
# ( .length(addr_width)) |
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk)); |
|
`BASE`MODULE |
vl_cnt_lfsr_ce |
# (.length(addr_width)) |
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk)); |
`undef MODULE |
|
// mux read or write adr to DPRAM |
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr}; |
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr}; |
|
`define MODULE dpram_2r2w |
`BASE`MODULE |
vl_dpram_2r2w |
# (.data_width(data_width), .addr_width(addr_width+1)) |
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk), |
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk)); |
`undef MODULE |
|
`define MODULE cnt_bin_ce_rew_zq_l1 |
`BASE`MODULE |
|
vl_cnt_bin_ce_rew_zq_l1 |
# (.length(addr_width), .level1_value(fifo_full_level)) |
a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk)); |
|
`BASE`MODULE |
vl_cnt_bin_ce_rew_zq_l1 |
# (.length(addr_width), .level1_value(fifo_full_level)) |
b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk)); |
`undef MODULE |
|
endmodule |
`endif |
|
`ifdef FIFO_CMP_ASYNC |
`define MODULE fifo_cmp_async |
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst ); |
`undef MODULE |
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst ); |
|
parameter addr_width = 4; |
parameter N = addr_width-1; |
498,9 → 449,8
default : direction_clr <= 1'b0; |
endcase |
|
`define MODULE dff_sr |
`ifndef GENERATE_DIRECTION_AS_LATCH |
`BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction)); |
vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction)); |
`endif |
|
`ifdef GENERATE_DIRECTION_AS_LATCH |
514,9 → 464,8
assign async_empty = (wptr == rptr) && (direction==going_empty); |
assign async_full = (wptr == rptr) && (direction==going_full); |
|
`BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2)); |
`BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full)); |
`undef MODULE |
vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2)); |
vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full)); |
|
/* |
always @ (posedge wclk or posedge rst or posedge async_full) |
532,17 → 481,12
{fifo_empty, fifo_empty2} <= 2'b11; |
else |
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */ |
`define MODULE dff |
`BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty)); |
`BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty)); |
`undef MODULE |
vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty)); |
vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty)); |
|
endmodule // async_compb |
`endif |
|
`ifdef FIFO_1R1W_ASYNC |
`define MODULE fifo_1r1w_async |
module `BASE`MODULE ( |
`undef MODULE |
module vl_fifo_1r1w_async ( |
d, wr, fifo_full, wr_clk, wr_rst, |
q, rd, fifo_empty, rd_clk, rd_rst |
); |
565,35 → 509,25
|
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin; |
|
`define MODULE cnt_gray_ce_bin |
`BASE`MODULE |
vl_cnt_gray_ce_bin |
# ( .length(addr_width)) |
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk)); |
|
`BASE`MODULE |
vl_cnt_gray_ce_bin |
# (.length(addr_width)) |
fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk)); |
`undef MODULE |
|
`define MODULE dpram_1r1w |
`BASE`MODULE |
vl_dpram_1r1w |
# (.data_width(data_width), .addr_width(addr_width)) |
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk)); |
`undef MODULE |
|
`define MODULE fifo_cmp_async |
`BASE`MODULE |
vl_fifo_cmp_async |
# (.addr_width(addr_width)) |
cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) ); |
`undef MODULE |
|
endmodule |
`endif |
|
`ifdef FIFO_2R2W_ASYNC |
`define MODULE fifo_2r2w_async |
module `BASE`MODULE ( |
`undef MODULE |
module vl_fifo_2r2w_async ( |
// a side |
a_d, a_wr, a_fifo_full, |
a_q, a_rd, a_fifo_empty, |
627,27 → 561,21
input b_clk; |
input b_rst; |
|
`define MODULE fifo_1r1w_async |
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width)) |
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width)) |
vl_fifo_1r1w_async_a ( |
.d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst), |
.q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst) |
); |
|
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width)) |
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width)) |
vl_fifo_1r1w_async_b ( |
.d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst), |
.q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst) |
); |
`undef MODULE |
|
|
endmodule |
`endif |
|
`ifdef FIFO_2R2W_ASYNC_SIMPLEX |
`define MODULE fifo_2r2w_async_simplex |
module `BASE`MODULE ( |
`undef MODULE |
module vl_fifo_2r2w_async_simplex ( |
// a side |
a_d, a_wr, a_fifo_full, |
a_q, a_rd, a_fifo_empty, |
687,44 → 615,37
// dpram |
wire [addr_width:0] a_dpram_adr, b_dpram_adr; |
|
`define MODULE cnt_gray_ce_bin |
`BASE`MODULE |
vl_cnt_gray_ce_bin |
# ( .length(addr_width)) |
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk)); |
|
`BASE`MODULE |
vl_cnt_gray_ce_bin |
# (.length(addr_width)) |
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk)); |
|
`BASE`MODULE |
vl_cnt_gray_ce_bin |
# ( .length(addr_width)) |
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk)); |
|
`BASE`MODULE |
vl_cnt_gray_ce_bin |
# (.length(addr_width)) |
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk)); |
`undef MODULE |
|
// mux read or write adr to DPRAM |
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin}; |
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin}; |
|
`define MODULE dpram_2r2w |
`BASE`MODULE |
vl_dpram_2r2w |
# (.data_width(data_width), .addr_width(addr_width+1)) |
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk), |
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk)); |
`undef MODULE |
|
`define MODULE fifo_cmp_async |
`BASE`MODULE |
vl_fifo_cmp_async |
# (.addr_width(addr_width)) |
cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) ); |
|
`BASE`MODULE |
vl_fifo_cmp_async |
# (.addr_width(addr_width)) |
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) ); |
`undef MODULE |
|
endmodule |
`endif |
/rtl/verilog/cnt_bin_ce_clear_l1_l2.csv
1,5 → 1,5
Name,type,,,, |
cnt_bin_ce_clear_l1_l2,binary,,,, |
vl_cnt_bin_ce_clear_l1_l2,binary,,,, |
,,,,, |
clear,set,cke,rew,, |
1,0,1,0,, |
/rtl/verilog/registers.v
40,10 → 40,8
//// //// |
////////////////////////////////////////////////////////////////////// |
|
`ifdef DFF |
`define MODULE dff |
module `BASE`MODULE ( d, q, clk, rst); |
`undef MODULE |
module vl_dff ( d, q, clk, rst); |
|
parameter width = 1; |
parameter reset_value = 0; |
|
58,12 → 56,8
q <= d; |
|
endmodule |
`endif |
|
`ifdef DFF_ARRAY |
`define MODULE dff_array |
module `BASE`MODULE ( d, q, clk, rst); |
`undef MODULE |
module vl_dff_array ( d, q, clk, rst); |
|
parameter width = 1; |
parameter depth = 2; |
87,12 → 81,8
assign q = q_tmp[depth-1]; |
|
endmodule |
`endif |
|
`ifdef DFF_CE |
`define MODULE dff_ce |
module `BASE`MODULE ( d, ce, q, clk, rst); |
`undef MODULE |
module vl_dff_ce ( d, ce, q, clk, rst); |
|
parameter width = 1; |
parameter reset_value = 0; |
109,12 → 99,8
q <= d; |
|
endmodule |
`endif |
|
`ifdef DFF_CE_CLEAR |
`define MODULE dff_ce_clear |
module `BASE`MODULE ( d, ce, clear, q, clk, rst); |
`undef MODULE |
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst); |
|
parameter width = 1; |
parameter reset_value = 0; |
134,12 → 120,8
q <= d; |
|
endmodule |
`endif |
|
`ifdef DF_CE_SET |
`define MODULE dff_ce_set |
module `BASE`MODULE ( d, ce, set, q, clk, rst); |
`undef MODULE |
module vl_dff_ce_set ( d, ce, set, q, clk, rst); |
|
parameter width = 1; |
parameter reset_value = 0; |
159,13 → 141,9
q <= d; |
|
endmodule |
`endif |
|
`ifdef SPR |
`define MODULE spr |
module `BASE`MODULE ( sp, r, q, clk, rst); |
`undef MODULE |
|
module vl_spr ( sp, r, q, clk, rst); |
|
parameter width = 1; |
parameter reset_value = 0; |
|
183,13 → 161,9
q <= 1'b0; |
|
endmodule |
`endif |
|
`ifdef SRP |
`define MODULE srp |
module `BASE`MODULE ( s, rp, q, clk, rst); |
`undef MODULE |
|
module vl_srp ( s, rp, q, clk, rst); |
|
parameter width = 1; |
parameter reset_value = 0; |
|
207,11 → 181,9
q <= 1'b1; |
|
endmodule |
`endif |
|
|
`ifdef ALTERA |
|
`ifdef DFF_SR |
// megafunction wizard: %LPM_FF% |
// GENERATION: STANDARD |
// VERSION: WM1.0 |
250,10 → 222,7
// synopsys translate_off |
`timescale 1 ps / 1 ps |
// synopsys translate_on |
`define MODULE dff_sr |
module `BASE`MODULE ( |
`undef MODULE |
|
module vl_dff_sr ( |
aclr, |
aset, |
clock, |
333,15 → 302,13
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE |
// Retrieval info: LIB_FILE: lpm |
`endif |
|
|
`else |
|
`ifdef DFF_SR |
`define MODULE dff_sr |
module `BASE`MODULE ( aclr, aset, clock, data, q); |
`undef MODULE |
|
module vl_dff_sr ( aclr, aset, clock, data, q); |
|
input aclr; |
input aset; |
input clock; |
357,7 → 324,6
q <= data; |
|
endmodule |
`endif |
|
`endif |
|
364,24 → 330,14
// LATCH |
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1 |
`ifdef ALTERA |
|
`ifdef LATCH |
`define MODULE latch |
module `BASE`MODULE ( d, le, q, clk); |
`undef MODULE |
module vl_latch ( d, le, q, clk); |
input d, le; |
output q; |
input clk; |
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q)); |
endmodule |
`endif |
|
`else |
|
`ifdef LATCH |
`define MODULE latch |
module `BASE`MODULE ( d, le, q, clk); |
`undef MODULE |
module latch ( d, le, q, clk); |
input d, le; |
output q; |
input clk;/* |
393,13 → 349,7
endmodule |
`endif |
|
`endif |
|
`ifdef SHREG |
`define MODULE shreg |
module `BASE`MODULE ( d, q, clk, rst); |
`undef MODULE |
|
module vl_shreg ( d, q, clk, rst); |
parameter depth = 10; |
input d; |
output q; |
414,12 → 364,8
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
endmodule |
`endif |
|
`ifdef SHREG_CE |
`define MODULE shreg_ce |
module `BASE`MODULE ( d, ce, q, clk, rst); |
`undef MODULE |
module vl_shreg_ce ( d, ce, q, clk, rst); |
parameter depth = 10; |
input d, ce; |
output q; |
435,12 → 381,8
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
endmodule |
`endif |
|
`ifdef DELAY |
`define MODULE delay |
module `BASE`MODULE ( d, q, clk, rst); |
`undef MODULE |
module vl_delay ( d, q, clk, rst); |
parameter depth = 10; |
input d; |
output q; |
455,12 → 397,8
dffs <= {d,dffs[1:depth-1]}; |
assign q = dffs[depth]; |
endmodule |
`endif |
|
`ifdef DELAY_EMPTYFLAG |
`define MODULE delay_emptyflag |
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst); |
`undef MODULE |
parameter depth = 10; |
input d; |
output q, emptyflag; |
476,4 → 414,3
assign q = dffs[depth]; |
assign emptyflag = !(|dffs); |
endmodule |
`endif |
/rtl/verilog/cnt_lfsr_ce_q.csv
1,5 → 1,5
Name,type,,,, |
cnt_lfsr_ce_q,LFSR,,,, |
vl_cnt_lfsr_ce_q,LFSR,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,1,0,, |
/rtl/verilog/cnt_lfsr_ce_clear_q.csv
1,5 → 1,5
Name,type,,,, |
cnt_lfsr_ce_clear_q,LFSR,,,, |
vl_cnt_lfsr_ce_clear_q,LFSR,,,, |
,,,,, |
clear,set,cke,rew,, |
1,0,1,0,, |
/rtl/verilog/cnt_bin_ce_rew_q_zq_l1.csv
1,5 → 1,5
Name,type,,,, |
cnt_bin_ce_rew_q_zq_l1,binary,,,, |
vl_cnt_bin_ce_rew_q_zq_l1,binary,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,1,1,, |
/rtl/verilog/cnt_bin_ce_rew_zq_l1.csv
1,5 → 1,5
Name,type,,,, |
cnt_bin_ce_rew_zq_l1,binary,,,, |
vl_cnt_bin_ce_rew_zq_l1,binary,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,1,1,, |
/rtl/verilog/cnt_bin.csv
1,5 → 1,5
Name,type,,,, |
cnt_bin,binary,,,, |
vl_cnt_bin,binary,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,0,0,, |
/rtl/verilog/cnt_bin_clear.csv
1,5 → 1,5
Name,type,,,, |
cnt_bin_clear,binary,,,, |
vl_cnt_bin_clear,binary,,,, |
,,,,, |
clear,set,cke,rew,, |
1,0,0,0,, |
/rtl/verilog/cnt_bin_ce_clear.csv
1,5 → 1,5
Name,type,,,, |
cnt_bin_ce_clear,binary,,,, |
vl_cnt_bin_ce_clear,binary,,,, |
,,,,, |
clear,set,cke,rew,, |
1,0,1,0,, |
/rtl/verilog/cnt_lfsr_ce_rew_l1.csv
1,5 → 1,5
Name,type,,,, |
cnt_lfsr_ce_rew_l1,LFSR,,,, |
vl_cnt_lfsr_ce_rew_l1,LFSR,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,1,1,, |
/rtl/verilog/cnt_lfsr_ce_zq.csv
1,5 → 1,5
Name,type,,,, |
cnt_lfsr_ce_zq,LFSR,,,, |
vl_cnt_lfsr_ce_zq,LFSR,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,1,0,, |
/rtl/verilog/cnt_bin_ce_rew_l1.csv
1,5 → 1,5
Name,type,,,, |
cnt_bin_ce_rew_l1,binary,,,, |
vl_cnt_bin_ce_rew_l1,binary,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,1,1,, |
/rtl/verilog/cnt_gray_ce_bin.csv
1,5 → 1,5
Name,type,,,, |
cnt_gray_ce_bin,GRAY,,,, |
vl_cnt_gray_ce_bin,GRAY,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,1,0,, |
/rtl/verilog/cnt_gray.csv
1,5 → 1,5
Name,type,,,, |
cnt_gray,GRAY,,,, |
vl_cnt_gray,GRAY,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,0,0,, |
/rtl/verilog/cnt_lfsr.csv
1,5 → 1,5
Name,type,,,, |
cnt_lfsr,LFSR,,,, |
vl_cnt_lfsr,LFSR,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,0,0,, |
/rtl/verilog/counters.v
40,10 → 40,7
//// //// |
////////////////////////////////////////////////////////////////////// |
|
`ifdef CNT_SHREG_WRAP |
`define MODULE cnt_shreg_wrap |
module `BASE`MODULE ( q, rst, clk); |
`undef MODULE |
module vl_cnt_shreg_wrap ( q, rst, clk); |
|
parameter length = 4; |
output reg [0:length-1] q; |
57,12 → 54,8
q <= {q[length-1],q[0:length-2]}; |
|
endmodule |
`endif |
|
`ifdef CNT_SHREG_CE_WRAP |
`define MODULE cnt_shreg_ce_wrap |
module `BASE`MODULE ( cke, q, rst, clk); |
`undef MODULE |
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk); |
|
parameter length = 4; |
input cke; |
78,12 → 71,8
q <= {q[length-1],q[0:length-2]}; |
|
endmodule |
`endif |
|
`ifdef CNT_SHREG_CE_CLEAR |
`define MODULE cnt_shreg_ce_clear |
module `BASE`MODULE ( cke, clear, q, rst, clk); |
`undef MODULE |
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk); |
|
parameter length = 4; |
input cke, clear; |
102,12 → 91,8
q <= q >> 1; |
|
endmodule |
`endif |
|
`ifdef CNT_SHREG_CE_CLEAR_WRAP |
`define MODULE cnt_shreg_ce_clear_wrap |
module `BASE`MODULE ( cke, clear, q, rst, clk); |
`undef MODULE |
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk); |
|
parameter length = 4; |
input cke, clear; |
126,4 → 111,3
q <= {q[length-1],q[0:length-2]}; |
|
endmodule |
`endif |
/rtl/verilog/cnt_gray_ce.csv
1,5 → 1,5
Name,type,,,, |
cnt_gray_ce,GRAY,,,, |
vl_cnt_gray_ce,GRAY,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,1,0,, |
/rtl/verilog/cnt_lfsr_ce.csv
1,5 → 1,5
Name,type,,,, |
cnt_lfsr_ce,LFSR,,,, |
vl_cnt_lfsr_ce,LFSR,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,1,0,, |
/rtl/verilog/cnt_bin_ce_clear_set_rew.csv
1,5 → 1,5
Name,type,,,, |
cnt_bin_ce_clear_set_rew,binary,,,, |
vl_cnt_bin_ce_clear_set_rew,binary,,,, |
,,,,, |
clear,set,cke,rew,, |
1,1,1,1,, |
/rtl/verilog/arith.v
40,11 → 40,8
//// //// |
////////////////////////////////////////////////////////////////////// |
|
`ifdef MULTS |
// signed multiplication |
`define MODULE mults |
module `BASE`MODULE (a,b,p); |
`undef MODULE |
module vl_mults (a,b,p); |
parameter operand_a_width = 18; |
parameter operand_b_width = 18; |
parameter result_hi = 35; |
62,11 → 59,8
assign p = result[result_hi:result_lo]; |
|
endmodule |
`endif |
`ifdef MULTS18X18 |
`define MODULE mults18x18 |
module `BASE`MODULE (a,b,p); |
`undef MODULE |
|
module vl_mults18x18 (a,b,p); |
input [17:0] a,b; |
output [35:0] p; |
vl_mult |
73,13 → 67,9
# (.operand_a_width(18), .operand_b_width(18)) |
mult0 (.a(a), .b(b), .p(p)); |
endmodule |
`endif |
|
`ifdef MULT |
`define MODULE mult |
// unsigned multiplication |
module `BASE`MODULE (a,b,p); |
`undef MODULE |
module vl_mult (a,b,p); |
parameter operand_a_width = 18; |
parameter operand_b_width = 18; |
parameter result_hi = 35; |
94,10 → 84,7
assign p = result[result_hi:result_lo]; |
|
endmodule |
`endif |
|
`ifdef SHIFT_UNIT_32 |
`define MODULE shift_unit_32 |
// shift unit |
// supporting the following shift functions |
// SLL |
104,8 → 91,7
// SRL |
// SRA |
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) |
module `BASE`MODULE( din, s, dout, opcode); |
`undef MODULE |
module vl_shift_unit_32( din, s, dout, opcode); |
input [31:0] din; // data in operand |
input [4:0] s; // shift operand |
input [1:0] opcode; |
146,12 → 132,11
assign sign[2] = sign[3] & (&din[31:24]); |
assign sign[1] = sign[2] & (&din[23:16]); |
assign sign[0] = sign[1] & (&din[15:8]); |
`define MODULE mults |
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3])); |
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24] ,din[23:16], din[15:8]}), .b({1'b0,s1}), .p(tmp[2])); |
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16] ,din[15:8], din[7:0]}), .b({1'b0,s1}), .p(tmp[1])); |
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8] ,din[7:0], 8'h00}), .b({1'b0,s1}), .p(tmp[0])); |
`undef MODULE |
vl_mults `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3])); |
vl_mults `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24] ,din[23:16], din[15:8]}), .b({1'b0,s1}), .p(tmp[2])); |
vl_mults `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16] ,din[15:8], din[7:0]}), .b({1'b0,s1}), .p(tmp[1])); |
vl_mults `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8] ,din[7:0], 8'h00}), .b({1'b0,s1}), .p(tmp[0])); |
|
// second stage is multiplexer based |
// shift on byte level |
|
187,9 → 172,7
tmp[3]; |
|
endmodule |
`endif |
|
`ifdef LOGIC_UNIT |
// logic unit |
// supporting the following logic functions |
// a and b |
196,9 → 179,7
// a or b |
// a xor b |
// not b |
`define MODULE logic_unit |
module `BASE`MODULE( a, b, result, opcode); |
`undef MODULE |
module vl_logic_unit( a, b, result, opcode); |
parameter width = 32; |
parameter opcode_and = 2'b00; |
parameter opcode_or = 2'b01; |
228,4 → 209,3
assign ovfl = ( a[width-1] & b[width-1] & ~result[width-1]) | |
(~a[width-1] & ~b[width-1] & result[width-1]); |
endmodule |
`endif |
/rtl/verilog/cnt_bin_ce.csv
1,5 → 1,5
Name,type,,,, |
cnt_bin_ce,binary,,,, |
vl_cnt_bin_ce,binary,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,1,0,, |
/rtl/verilog/cnt_lfsr_zq.csv
1,5 → 1,5
Name,type,,,, |
cnt_lfsr_zq,LFSR,,,, |
vl_cnt_lfsr_zq,LFSR,,,, |
,,,,, |
clear,set,cke,rew,, |
0,0,0,0,, |