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https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
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/versatile_library/trunk
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Rev 59 → Rev 60
/rtl/verilog/versatile_library.v
2,7 → 2,11
`define BASE vl_ |
`endif |
|
// default SYN_KEEP definition |
`define SYN_KEEP /*synthesis syn_keep = 1*/ |
|
`ifdef ACTEL |
`undef SYN_KEEP |
`define SYN_KEEP /*synthesis syn_keep = 1*/ |
`endif |
|
1036,7 → 1040,7
input d, le; |
input clk; |
always @ (le or d) |
if le |
if (le) |
d <= q; |
endmodule |
`endif |
3520,9 → 3524,9
|
reg [data_width-1:0] ram [(1<<addr_width)-1:0]; |
|
parameter init = 0; |
parameter memory_init = 0; |
parameter memory_file = "vl_ram.vmem"; |
generate if (init) begin : init_mem |
generate if (memory_init) begin : init_mem |
initial |
begin |
$readmemh(memory_file, ram); |
3530,6 → 3534,24
end |
endgenerate |
|
`ifdef SYSTEMVERILOG |
// use a multi-dimensional packed array |
//to model individual bytes within the word |
|
logic [dat_width/8-1:0][7:0] ram[0:1<<(adr_width-2)-1];// # words = 1 << address width |
always_ff@(posedge clk) |
begin |
if(we) begin // note: we should have a for statement to support any bus width |
if(be[3]) ram[adr[adr_size-2:0]][3] <= d[31:24]; |
if(be[2]) ram[adr[adr_size-2:0]][2] <= d[23:16]; |
if(be[1]) ram[adr[adr_size-2:0]][1] <= d[15:8]; |
if(be[0]) ram[adr[adr_size-2:0]][0] <= d[7:0]; |
end |
q <= ram[raddr]; |
end |
|
`else |
|
genvar i; |
generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram |
always @ (posedge clk) |
3541,6 → 3563,8
always @ (posedge clk) |
q <= ram[adr]; |
|
`endif |
|
endmodule |
`endif |
|
4638,7 → 4662,7
endmodule |
`endif |
|
`ifdef WB_B4_RAM_BE |
`ifdef WB_B3_RAM_BE |
// WB RAM with byte enable |
`define MODULE wb_b3_ram_be |
module `BASE`MODULE ( |
4646,55 → 4670,116
wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i, |
wb_dat_o, wb_ack_o, wb_clk, wb_rst); |
|
parameter dat_width = 32; |
parameter adr_width = 8; |
parameter nr_of_ports = 3; |
parameter wb_arbiter_type = 1; |
parameter adr_size = 26; |
parameter adr_lo = 2; |
parameter dat_size = 32; |
parameter memory_init = 1; |
parameter memory_file = "vl_ram.vmem"; |
|
input [dat_width-1:0] wb_dat_i; |
input [adr_width-1:0] wb_adr_i; |
input [2:0] wb_cti_i; |
input [dat_width/8-1:0] wb_sel_i; |
input wb_we_i, wb_stb_i, wb_cyc_i; |
output [dat_width-1:0] wb_dat_o; |
reg [dat_width-1:0] wb_dat_o; |
output wb_stall_o; |
localparam aw = (adr_size - adr_lo) * nr_of_ports; |
localparam dw = dat_size * nr_of_ports; |
localparam sw = dat_size/8 * nr_of_ports; |
localparam cw = 3 * nr_of_ports; |
localparam bw = 2 * nr_of_ports; |
|
input [dw-1:0] wb_dat_i; |
input [aw-1:0] wb_adr_i; |
input [cw-1:0] wb_cti_i; |
input [sw-1:0] wb_sel_i; |
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i; |
output [dw-1:0] wb_dat_o; |
reg [dw-1:0] wb_dat_o; |
output wb_ack_o; |
reg wb_ack_o; |
input wb_clk, wb_rst; |
|
wire [dat_width/8-1:0] cke; |
wire [sw-1:0] cke; |
|
// local wb slave |
wire [dat_size-1:0] wbs_dat_i; |
wire [adr_size-1:0] wbs_adr_i; |
wire [2:0] wbs_cti_i; |
wire [(dat_size/8)-1:0] wbs_sel_i; |
wire wbs_we_i, wbs_stb_i, wbs_cyc_i; |
wire [dat_size-1:0] wbs_dat_o; |
reg wbs_ack_o; |
|
generate |
if (dat_width==32) begin |
reg [7:0] ram3 [1<<(adr_width-2)-1:0]; |
reg [7:0] ram2 [1<<(adr_width-2)-1:0]; |
reg [7:0] ram1 [1<<(adr_width-2)-1:0]; |
reg [7:0] ram0 [1<<(adr_width-2)-1:0]; |
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}}; |
always @ (posedge wb_clk) |
begin |
if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24]; |
if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16]; |
if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8]; |
if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0]; |
end |
always @ (posedge wb_clk or posedge wb_rst) |
begin |
if (wb_rst) |
wb_dat_o <= 32'h0; |
else |
wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]}; |
end |
if (nr_of_ports == 1) begin |
assign wbs_dat_i = wb_dat_i; |
assign wbs_adr_i = wb_adr_i; |
assign wbs_cti_i = wb_cti_i; |
assign wbs_sel_i = wb_sel_i; |
assign wbs_we_i = wb_we_i; |
assign wbs_stb_i = wb_stb_i; |
assign wbs_cyc_i = wb_cyc_i; |
assign wb_dat_o = wbs_dat_o; |
assign wb_ack_o = wbs_ack_o; |
end |
endgenerate |
|
generate |
if (nr_of_ports > 1 & wb_arbiter_type == 1) begin |
`define MODULE wb3_arbiter_type1 |
`BASE`MODULE wb_arbiter0( |
`undef MODULE |
.wbm_dat_o(wb_dat_i), |
.wbm_adr_o(wb_adr_i), |
.wbm_sel_o(wb_sel_i), |
.wbm_cti_o(wb_cti_i), |
.wbm_bte_o(wb_bte_i), |
.wbm_we_o(wb_we_i), |
.wbm_stb_o(wb_stb_i), |
.wbm_cyc_o(wb_cyc_i), |
.wbm_dat_i(wb_dat_o), |
.wbm_ack_i(wb_ack_o), |
.wbm_err_i(), |
.wbm_rty_i(), |
.wbs_dat_i(wbs_dat_i), |
.wbs_adr_i(wbs_adr_i), |
.wbs_sel_i(wbs_sel_i), |
.wbs_cti_i(wbs_cti_i), |
.wbs_bte_i(wbs_bte_i), |
.wbs_we_i(wbs_we_i), |
.wbs_stb_i(wbs_stb_i), |
.wbs_cyc_i(wbs_cyc_i), |
.wbs_dat_o(wbs_dat_o), |
.wbs_ack_o(wbs_ack_o), |
.wbs_err_o(1'b0), |
.wbs_rty_o(1'b0), |
.wb_clk(wb_clk), |
.wb_rst(wb_rst) |
); |
end |
endgenerate |
|
`define MODULE ram_be |
`BASE`MODULE # ( |
.data_width(dat_size), |
.addr_width(adr_size), |
.memory_init(1), |
.memory_file("memory_file")) |
ram0( |
`undef MODULE |
.d(wbs_dat_i), |
.adr(wbs_adr_i[adr_size-1:2]), |
.be(wbs_sel_i), |
.we(wbs_we_i), |
.q(wbs_dat_o), |
.clk(wb_clk) |
); |
|
always @ (posedge wb_clk or posedge wb_rst) |
if (wb_rst) |
wb_ack_o <= 1'b0; |
wbs_ack_o <= 1'b0; |
else |
if (wb_cti_i=3'b000 | wb_cti_i=3'b111) |
wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o; |
if (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) |
wbs_ack_o <= wbs_stb_i & wbs_cyc_i & !wbs_ack_o; |
else |
wb_ack_o <= wb_stb_i & wb_cyc_i; |
wbs_ack_o <= wbs_stb_i & wbs_cyc_i; |
|
endmodule |
`endif |
|
/rtl/verilog/versatile_library_actel.v
1,3 → 1,4
// default SYN_KEEP definition |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile library, clock and reset //// |
336,7 → 337,7
input d, le; |
input clk; |
always @ (le or d) |
if le |
if (le) |
d <= q; |
endmodule |
module vl_shreg ( d, q, clk, rst); |
1128,9 → 1129,9
output reg [(data_width-1):0] q; |
input clk; |
reg [data_width-1:0] ram [(1<<addr_width)-1:0]; |
parameter init = 0; |
parameter memory_init = 0; |
parameter memory_file = "vl_ram.vmem"; |
generate if (init) begin : init_mem |
generate if (memory_init) begin : init_mem |
initial |
begin |
$readmemh(memory_file, ram); |
1137,6 → 1138,21
end |
end |
endgenerate |
`ifdef SYSTEMVERILOG |
// use a multi-dimensional packed array |
//to model individual bytes within the word |
logic [dat_width/8-1:0][7:0] ram[0:1<<(adr_width-2)-1];// # words = 1 << address width |
always_ff@(posedge clk) |
begin |
if(we) begin // note: we should have a for statement to support any bus width |
if(be[3]) ram[adr[adr_size-2:0]][3] <= d[31:24]; |
if(be[2]) ram[adr[adr_size-2:0]][2] <= d[23:16]; |
if(be[1]) ram[adr[adr_size-2:0]][1] <= d[15:8]; |
if(be[0]) ram[adr[adr_size-2:0]][0] <= d[7:0]; |
end |
q <= ram[raddr]; |
end |
`else |
genvar i; |
generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram |
always @ (posedge clk) |
1146,6 → 1162,7
endgenerate |
always @ (posedge clk) |
q <= ram[adr]; |
`endif |
endmodule |
// ACTEL FPGA should not use logic to handle rw collision |
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b ); |
1947,51 → 1964,103
module vl_wb_b3_ram_be ( |
wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i, |
wb_dat_o, wb_ack_o, wb_clk, wb_rst); |
parameter dat_width = 32; |
parameter adr_width = 8; |
input [dat_width-1:0] wb_dat_i; |
input [adr_width-1:0] wb_adr_i; |
input [2:0] wb_cti_i; |
input [dat_width/8-1:0] wb_sel_i; |
input wb_we_i, wb_stb_i, wb_cyc_i; |
output [dat_width-1:0] wb_dat_o; |
reg [dat_width-1:0] wb_dat_o; |
output wb_stall_o; |
parameter nr_of_ports = 3; |
parameter wb_arbiter_type = 1; |
parameter adr_size = 26; |
parameter adr_lo = 2; |
parameter dat_size = 32; |
parameter memory_init = 1; |
parameter memory_file = "vl_ram.vmem"; |
localparam aw = (adr_size - adr_lo) * nr_of_ports; |
localparam dw = dat_size * nr_of_ports; |
localparam sw = dat_size/8 * nr_of_ports; |
localparam cw = 3 * nr_of_ports; |
localparam bw = 2 * nr_of_ports; |
input [dw-1:0] wb_dat_i; |
input [aw-1:0] wb_adr_i; |
input [cw-1:0] wb_cti_i; |
input [sw-1:0] wb_sel_i; |
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i; |
output [dw-1:0] wb_dat_o; |
reg [dw-1:0] wb_dat_o; |
output wb_ack_o; |
reg wb_ack_o; |
input wb_clk, wb_rst; |
wire [dat_width/8-1:0] cke; |
wire [sw-1:0] cke; |
// local wb slave |
wire [dat_size-1:0] wbs_dat_i; |
wire [adr_size-1:0] wbs_adr_i; |
wire [2:0] wbs_cti_i; |
wire [(dat_size/8)-1:0] wbs_sel_i; |
wire wbs_we_i, wbs_stb_i, wbs_cyc_i; |
wire [dat_size-1:0] wbs_dat_o; |
reg wbs_ack_o; |
generate |
if (dat_width==32) begin |
reg [7:0] ram3 [1<<(adr_width-2)-1:0]; |
reg [7:0] ram2 [1<<(adr_width-2)-1:0]; |
reg [7:0] ram1 [1<<(adr_width-2)-1:0]; |
reg [7:0] ram0 [1<<(adr_width-2)-1:0]; |
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}}; |
always @ (posedge wb_clk) |
begin |
if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24]; |
if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16]; |
if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8]; |
if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0]; |
end |
always @ (posedge wb_clk or posedge wb_rst) |
begin |
if (wb_rst) |
wb_dat_o <= 32'h0; |
else |
wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]}; |
end |
if (nr_of_ports == 1) begin |
assign wbs_dat_i = wb_dat_i; |
assign wbs_adr_i = wb_adr_i; |
assign wbs_cti_i = wb_cti_i; |
assign wbs_sel_i = wb_sel_i; |
assign wbs_we_i = wb_we_i; |
assign wbs_stb_i = wb_stb_i; |
assign wbs_cyc_i = wb_cyc_i; |
assign wb_dat_o = wbs_dat_o; |
assign wb_ack_o = wbs_ack_o; |
end |
endgenerate |
generate |
if (nr_of_ports > 1 & wb_arbiter_type == 1) begin |
vl_wb3_arbiter_type1 wb_arbiter0( |
.wbm_dat_o(wb_dat_i), |
.wbm_adr_o(wb_adr_i), |
.wbm_sel_o(wb_sel_i), |
.wbm_cti_o(wb_cti_i), |
.wbm_bte_o(wb_bte_i), |
.wbm_we_o(wb_we_i), |
.wbm_stb_o(wb_stb_i), |
.wbm_cyc_o(wb_cyc_i), |
.wbm_dat_i(wb_dat_o), |
.wbm_ack_i(wb_ack_o), |
.wbm_err_i(), |
.wbm_rty_i(), |
.wbs_dat_i(wbs_dat_i), |
.wbs_adr_i(wbs_adr_i), |
.wbs_sel_i(wbs_sel_i), |
.wbs_cti_i(wbs_cti_i), |
.wbs_bte_i(wbs_bte_i), |
.wbs_we_i(wbs_we_i), |
.wbs_stb_i(wbs_stb_i), |
.wbs_cyc_i(wbs_cyc_i), |
.wbs_dat_o(wbs_dat_o), |
.wbs_ack_o(wbs_ack_o), |
.wbs_err_o(1'b0), |
.wbs_rty_o(1'b0), |
.wb_clk(wb_clk), |
.wb_rst(wb_rst) |
); |
end |
endgenerate |
vl_ram_be # ( |
.data_width(dat_size), |
.addr_width(adr_size), |
.memory_init(1), |
.memory_file("memory_file")) |
ram0( |
.d(wbs_dat_i), |
.adr(wbs_adr_i[adr_size-1:2]), |
.be(wbs_sel_i), |
.we(wbs_we_i), |
.q(wbs_dat_o), |
.clk(wb_clk) |
); |
always @ (posedge wb_clk or posedge wb_rst) |
if (wb_rst) |
wb_ack_o <= 1'b0; |
wbs_ack_o <= 1'b0; |
else |
if (wb_cti_i=3'b000 | wb_cti_i=3'b111) |
wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o; |
if (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) |
wbs_ack_o <= wbs_stb_i & wbs_cyc_i & !wbs_ack_o; |
else |
wb_ack_o <= wb_stb_i & wb_cyc_i; |
wbs_ack_o <= wbs_stb_i & wbs_cyc_i; |
endmodule |
// WB RAM with byte enable |
module vl_wb_b4_ram_be ( |
/rtl/verilog/wb.v
467,7 → 467,7
endmodule |
`endif |
|
`ifdef WB_B4_RAM_BE |
`ifdef WB_B3_RAM_BE |
// WB RAM with byte enable |
`define MODULE wb_b3_ram_be |
module `BASE`MODULE ( |
475,55 → 475,116
wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i, |
wb_dat_o, wb_ack_o, wb_clk, wb_rst); |
|
parameter dat_width = 32; |
parameter adr_width = 8; |
parameter nr_of_ports = 3; |
parameter wb_arbiter_type = 1; |
parameter adr_size = 26; |
parameter adr_lo = 2; |
parameter dat_size = 32; |
parameter memory_init = 1; |
parameter memory_file = "vl_ram.vmem"; |
|
input [dat_width-1:0] wb_dat_i; |
input [adr_width-1:0] wb_adr_i; |
input [2:0] wb_cti_i; |
input [dat_width/8-1:0] wb_sel_i; |
input wb_we_i, wb_stb_i, wb_cyc_i; |
output [dat_width-1:0] wb_dat_o; |
reg [dat_width-1:0] wb_dat_o; |
output wb_stall_o; |
localparam aw = (adr_size - adr_lo) * nr_of_ports; |
localparam dw = dat_size * nr_of_ports; |
localparam sw = dat_size/8 * nr_of_ports; |
localparam cw = 3 * nr_of_ports; |
localparam bw = 2 * nr_of_ports; |
|
input [dw-1:0] wb_dat_i; |
input [aw-1:0] wb_adr_i; |
input [cw-1:0] wb_cti_i; |
input [sw-1:0] wb_sel_i; |
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i; |
output [dw-1:0] wb_dat_o; |
reg [dw-1:0] wb_dat_o; |
output wb_ack_o; |
reg wb_ack_o; |
input wb_clk, wb_rst; |
|
wire [dat_width/8-1:0] cke; |
wire [sw-1:0] cke; |
|
// local wb slave |
wire [dat_size-1:0] wbs_dat_i; |
wire [adr_size-1:0] wbs_adr_i; |
wire [2:0] wbs_cti_i; |
wire [(dat_size/8)-1:0] wbs_sel_i; |
wire wbs_we_i, wbs_stb_i, wbs_cyc_i; |
wire [dat_size-1:0] wbs_dat_o; |
reg wbs_ack_o; |
|
generate |
if (dat_width==32) begin |
reg [7:0] ram3 [1<<(adr_width-2)-1:0]; |
reg [7:0] ram2 [1<<(adr_width-2)-1:0]; |
reg [7:0] ram1 [1<<(adr_width-2)-1:0]; |
reg [7:0] ram0 [1<<(adr_width-2)-1:0]; |
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}}; |
always @ (posedge wb_clk) |
begin |
if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24]; |
if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16]; |
if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8]; |
if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0]; |
end |
always @ (posedge wb_clk or posedge wb_rst) |
begin |
if (wb_rst) |
wb_dat_o <= 32'h0; |
else |
wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]}; |
end |
if (nr_of_ports == 1) begin |
assign wbs_dat_i = wb_dat_i; |
assign wbs_adr_i = wb_adr_i; |
assign wbs_cti_i = wb_cti_i; |
assign wbs_sel_i = wb_sel_i; |
assign wbs_we_i = wb_we_i; |
assign wbs_stb_i = wb_stb_i; |
assign wbs_cyc_i = wb_cyc_i; |
assign wb_dat_o = wbs_dat_o; |
assign wb_ack_o = wbs_ack_o; |
end |
endgenerate |
|
generate |
if (nr_of_ports > 1 & wb_arbiter_type == 1) begin |
`define MODULE wb3_arbiter_type1 |
`BASE`MODULE wb_arbiter0( |
`undef MODULE |
.wbm_dat_o(wb_dat_i), |
.wbm_adr_o(wb_adr_i), |
.wbm_sel_o(wb_sel_i), |
.wbm_cti_o(wb_cti_i), |
.wbm_bte_o(wb_bte_i), |
.wbm_we_o(wb_we_i), |
.wbm_stb_o(wb_stb_i), |
.wbm_cyc_o(wb_cyc_i), |
.wbm_dat_i(wb_dat_o), |
.wbm_ack_i(wb_ack_o), |
.wbm_err_i(), |
.wbm_rty_i(), |
.wbs_dat_i(wbs_dat_i), |
.wbs_adr_i(wbs_adr_i), |
.wbs_sel_i(wbs_sel_i), |
.wbs_cti_i(wbs_cti_i), |
.wbs_bte_i(wbs_bte_i), |
.wbs_we_i(wbs_we_i), |
.wbs_stb_i(wbs_stb_i), |
.wbs_cyc_i(wbs_cyc_i), |
.wbs_dat_o(wbs_dat_o), |
.wbs_ack_o(wbs_ack_o), |
.wbs_err_o(1'b0), |
.wbs_rty_o(1'b0), |
.wb_clk(wb_clk), |
.wb_rst(wb_rst) |
); |
end |
endgenerate |
|
`define MODULE ram_be |
`BASE`MODULE # ( |
.data_width(dat_size), |
.addr_width(adr_size), |
.memory_init(1), |
.memory_file("memory_file")) |
ram0( |
`undef MODULE |
.d(wbs_dat_i), |
.adr(wbs_adr_i[adr_size-1:2]), |
.be(wbs_sel_i), |
.we(wbs_we_i), |
.q(wbs_dat_o), |
.clk(wb_clk) |
); |
|
always @ (posedge wb_clk or posedge wb_rst) |
if (wb_rst) |
wb_ack_o <= 1'b0; |
wbs_ack_o <= 1'b0; |
else |
if (wb_cti_i=3'b000 | wb_cti_i=3'b111) |
wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o; |
if (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) |
wbs_ack_o <= wbs_stb_i & wbs_cyc_i & !wbs_ack_o; |
else |
wb_ack_o <= wb_stb_i & wb_cyc_i; |
wbs_ack_o <= wbs_stb_i & wbs_cyc_i; |
|
endmodule |
`endif |
|
/rtl/verilog/Makefile
71,6 → 71,10
|
all: $(VERSATILE_LIBRARIES) |
|
test: all |
iverilog -DALL -tnull -svl_shift_unit_32 versatile_library.v |
iverilog -tnull -svl_shift_unit_32 versatile_library_actel.v |
iverilog -tnull -svl_shift_unit_32 versatile_library_altera.v |
clean: |
rm $(VERSATILE_LIBRARIES) |
rm $(VERILOG_FILES_CNT) |
/rtl/verilog/versatile_library_altera.v
1,3 → 1,4
// default SYN_KEEP definition |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile library, clock and reset //// |
688,7 → 689,7
input [width-1:0] d_i; |
output [width-1:0] o_pad; |
input clk, rst; |
wire [width-1:0] d_i_int `SYN_KEEP; |
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/; |
reg [width-1:0] o_pad_int; |
assign d_i_int = d_i; |
genvar i; |
711,7 → 712,7
input oe; |
inout [width-1:0] io_pad; |
input clk, rst; |
wire [width-1:0] oe_d `SYN_KEEP; |
wire [width-1:0] oe_d /*synthesis syn_keep = 1*/; |
reg [width-1:0] oe_q; |
reg [width-1:0] d_o_q; |
assign oe_d = {width{oe}}; |
1236,9 → 1237,9
output reg [(data_width-1):0] q; |
input clk; |
reg [data_width-1:0] ram [(1<<addr_width)-1:0]; |
parameter init = 0; |
parameter memory_init = 0; |
parameter memory_file = "vl_ram.vmem"; |
generate if (init) begin : init_mem |
generate if (memory_init) begin : init_mem |
initial |
begin |
$readmemh(memory_file, ram); |
1245,6 → 1246,21
end |
end |
endgenerate |
`ifdef SYSTEMVERILOG |
// use a multi-dimensional packed array |
//to model individual bytes within the word |
logic [dat_width/8-1:0][7:0] ram[0:1<<(adr_width-2)-1];// # words = 1 << address width |
always_ff@(posedge clk) |
begin |
if(we) begin // note: we should have a for statement to support any bus width |
if(be[3]) ram[adr[adr_size-2:0]][3] <= d[31:24]; |
if(be[2]) ram[adr[adr_size-2:0]][2] <= d[23:16]; |
if(be[1]) ram[adr[adr_size-2:0]][1] <= d[15:8]; |
if(be[0]) ram[adr[adr_size-2:0]][0] <= d[7:0]; |
end |
q <= ram[raddr]; |
end |
`else |
genvar i; |
generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram |
always @ (posedge clk) |
1254,6 → 1270,7
endgenerate |
always @ (posedge clk) |
q <= ram[adr]; |
`endif |
endmodule |
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b ); |
parameter data_width = 32; |
2052,51 → 2069,103
module vl_wb_b3_ram_be ( |
wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i, |
wb_dat_o, wb_ack_o, wb_clk, wb_rst); |
parameter dat_width = 32; |
parameter adr_width = 8; |
input [dat_width-1:0] wb_dat_i; |
input [adr_width-1:0] wb_adr_i; |
input [2:0] wb_cti_i; |
input [dat_width/8-1:0] wb_sel_i; |
input wb_we_i, wb_stb_i, wb_cyc_i; |
output [dat_width-1:0] wb_dat_o; |
reg [dat_width-1:0] wb_dat_o; |
output wb_stall_o; |
parameter nr_of_ports = 3; |
parameter wb_arbiter_type = 1; |
parameter adr_size = 26; |
parameter adr_lo = 2; |
parameter dat_size = 32; |
parameter memory_init = 1; |
parameter memory_file = "vl_ram.vmem"; |
localparam aw = (adr_size - adr_lo) * nr_of_ports; |
localparam dw = dat_size * nr_of_ports; |
localparam sw = dat_size/8 * nr_of_ports; |
localparam cw = 3 * nr_of_ports; |
localparam bw = 2 * nr_of_ports; |
input [dw-1:0] wb_dat_i; |
input [aw-1:0] wb_adr_i; |
input [cw-1:0] wb_cti_i; |
input [sw-1:0] wb_sel_i; |
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i; |
output [dw-1:0] wb_dat_o; |
reg [dw-1:0] wb_dat_o; |
output wb_ack_o; |
reg wb_ack_o; |
input wb_clk, wb_rst; |
wire [dat_width/8-1:0] cke; |
wire [sw-1:0] cke; |
// local wb slave |
wire [dat_size-1:0] wbs_dat_i; |
wire [adr_size-1:0] wbs_adr_i; |
wire [2:0] wbs_cti_i; |
wire [(dat_size/8)-1:0] wbs_sel_i; |
wire wbs_we_i, wbs_stb_i, wbs_cyc_i; |
wire [dat_size-1:0] wbs_dat_o; |
reg wbs_ack_o; |
generate |
if (dat_width==32) begin |
reg [7:0] ram3 [1<<(adr_width-2)-1:0]; |
reg [7:0] ram2 [1<<(adr_width-2)-1:0]; |
reg [7:0] ram1 [1<<(adr_width-2)-1:0]; |
reg [7:0] ram0 [1<<(adr_width-2)-1:0]; |
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}}; |
always @ (posedge wb_clk) |
begin |
if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24]; |
if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16]; |
if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8]; |
if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0]; |
end |
always @ (posedge wb_clk or posedge wb_rst) |
begin |
if (wb_rst) |
wb_dat_o <= 32'h0; |
else |
wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]}; |
end |
if (nr_of_ports == 1) begin |
assign wbs_dat_i = wb_dat_i; |
assign wbs_adr_i = wb_adr_i; |
assign wbs_cti_i = wb_cti_i; |
assign wbs_sel_i = wb_sel_i; |
assign wbs_we_i = wb_we_i; |
assign wbs_stb_i = wb_stb_i; |
assign wbs_cyc_i = wb_cyc_i; |
assign wb_dat_o = wbs_dat_o; |
assign wb_ack_o = wbs_ack_o; |
end |
endgenerate |
generate |
if (nr_of_ports > 1 & wb_arbiter_type == 1) begin |
vl_wb3_arbiter_type1 wb_arbiter0( |
.wbm_dat_o(wb_dat_i), |
.wbm_adr_o(wb_adr_i), |
.wbm_sel_o(wb_sel_i), |
.wbm_cti_o(wb_cti_i), |
.wbm_bte_o(wb_bte_i), |
.wbm_we_o(wb_we_i), |
.wbm_stb_o(wb_stb_i), |
.wbm_cyc_o(wb_cyc_i), |
.wbm_dat_i(wb_dat_o), |
.wbm_ack_i(wb_ack_o), |
.wbm_err_i(), |
.wbm_rty_i(), |
.wbs_dat_i(wbs_dat_i), |
.wbs_adr_i(wbs_adr_i), |
.wbs_sel_i(wbs_sel_i), |
.wbs_cti_i(wbs_cti_i), |
.wbs_bte_i(wbs_bte_i), |
.wbs_we_i(wbs_we_i), |
.wbs_stb_i(wbs_stb_i), |
.wbs_cyc_i(wbs_cyc_i), |
.wbs_dat_o(wbs_dat_o), |
.wbs_ack_o(wbs_ack_o), |
.wbs_err_o(1'b0), |
.wbs_rty_o(1'b0), |
.wb_clk(wb_clk), |
.wb_rst(wb_rst) |
); |
end |
endgenerate |
vl_ram_be # ( |
.data_width(dat_size), |
.addr_width(adr_size), |
.memory_init(1), |
.memory_file("memory_file")) |
ram0( |
.d(wbs_dat_i), |
.adr(wbs_adr_i[adr_size-1:2]), |
.be(wbs_sel_i), |
.we(wbs_we_i), |
.q(wbs_dat_o), |
.clk(wb_clk) |
); |
always @ (posedge wb_clk or posedge wb_rst) |
if (wb_rst) |
wb_ack_o <= 1'b0; |
wbs_ack_o <= 1'b0; |
else |
if (wb_cti_i=3'b000 | wb_cti_i=3'b111) |
wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o; |
if (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) |
wbs_ack_o <= wbs_stb_i & wbs_cyc_i & !wbs_ack_o; |
else |
wb_ack_o <= wb_stb_i & wb_cyc_i; |
wbs_ack_o <= wbs_stb_i & wbs_cyc_i; |
endmodule |
// WB RAM with byte enable |
module vl_wb_b4_ram_be ( |
/rtl/verilog/defines.v
2,7 → 2,11
`define BASE vl_ |
`endif |
|
// default SYN_KEEP definition |
`define SYN_KEEP /*synthesis syn_keep = 1*/ |
|
`ifdef ACTEL |
`undef SYN_KEEP |
`define SYN_KEEP /*synthesis syn_keep = 1*/ |
`endif |
|
/rtl/verilog/memories.v
114,9 → 114,9
|
reg [data_width-1:0] ram [(1<<addr_width)-1:0]; |
|
parameter init = 0; |
parameter memory_init = 0; |
parameter memory_file = "vl_ram.vmem"; |
generate if (init) begin : init_mem |
generate if (memory_init) begin : init_mem |
initial |
begin |
$readmemh(memory_file, ram); |
124,6 → 124,24
end |
endgenerate |
|
//E2_ifdef SYSTEMVERILOG |
// use a multi-dimensional packed array |
//to model individual bytes within the word |
|
logic [dat_width/8-1:0][7:0] ram[0:1<<(adr_width-2)-1];// # words = 1 << address width |
always_ff@(posedge clk) |
begin |
if(we) begin // note: we should have a for statement to support any bus width |
if(be[3]) ram[adr[adr_size-2:0]][3] <= d[31:24]; |
if(be[2]) ram[adr[adr_size-2:0]][2] <= d[23:16]; |
if(be[1]) ram[adr[adr_size-2:0]][1] <= d[15:8]; |
if(be[0]) ram[adr[adr_size-2:0]][0] <= d[7:0]; |
end |
q <= ram[raddr]; |
end |
|
//E2_else |
|
genvar i; |
generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram |
always @ (posedge clk) |
135,6 → 153,8
always @ (posedge clk) |
q <= ram[adr]; |
|
//E2_endif |
|
endmodule |
`endif |
|
/rtl/verilog/registers.v
385,7 → 385,7
input d, le; |
input clk; |
always @ (le or d) |
if le |
if (le) |
d <= q; |
endmodule |
`endif |