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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path 
    /versatile_library/trunk
    from Rev 68 to Rev 67
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  •

Rev 68 → Rev 67

/rtl/verilog/versatile_library.v
3524,7 → 3524,6
 
parameter data_width = 32;
parameter addr_width = 8;
parameter mem_size = 256;
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input [(addr_width/4)-1:0] be;
3533,9 → 3532,9
input clk;
 
`ifdef SYSTEMVERILOG
logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
logic [data_width/8-1:0][7:0] ram[0:1<<(addr_width-2)-1];// # words = 1 << address width
`else
reg [data_width-1:0] ram [mem_size-1:0];
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
`endif
 
parameter memory_init = 0;
4790,9 → 4789,8
 
parameter nr_of_ports = 3;
parameter wb_arbiter_type = 1;
parameter adr_size = 16;
parameter adr_size = 26;
parameter adr_lo = 2;
parameter mem_size = 1<<16;
parameter dat_size = 32;
parameter memory_init = 1;
parameter memory_file = "vl_ram.vmem";
4878,8 → 4876,8
`BASE`MODULE # (
.data_width(dat_size),
.addr_width(adr_size),
.memory_init(memory_init),
.memory_file(memory_file))
.memory_init(1),
.memory_file("memory_file"))
ram0(
`undef MODULE
.d(wbs_dat_i),
/rtl/verilog/versatile_library_actel.v
1122,7 → 1122,6
module vl_ram_be ( d, adr, be, we, q, clk);
parameter data_width = 32;
parameter addr_width = 8;
parameter mem_size = 256;
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input [(addr_width/4)-1:0] be;
1130,9 → 1129,9
output reg [(data_width-1):0] q;
input clk;
`ifdef SYSTEMVERILOG
logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
logic [data_width/8-1:0][7:0] ram[0:1<<(addr_width-2)-1];// # words = 1 << address width
`else
reg [data_width-1:0] ram [mem_size-1:0];
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
`endif
parameter memory_init = 0;
parameter memory_file = "vl_ram.vmem";
2054,9 → 2053,8
wb_dat_o, wb_ack_o, wb_clk, wb_rst);
parameter nr_of_ports = 3;
parameter wb_arbiter_type = 1;
parameter adr_size = 16;
parameter adr_size = 26;
parameter adr_lo = 2;
parameter mem_size = 1<<16;
parameter dat_size = 32;
parameter memory_init = 1;
parameter memory_file = "vl_ram.vmem";
2132,8 → 2130,8
vl_ram_be # (
.data_width(dat_size),
.addr_width(adr_size),
.memory_init(memory_init),
.memory_file(memory_file))
.memory_init(1),
.memory_file("memory_file"))
ram0(
.d(wbs_dat_i),
.adr(wbs_adr_i[adr_size-1:2]),
/rtl/verilog/wb.v
582,9 → 582,8
 
parameter nr_of_ports = 3;
parameter wb_arbiter_type = 1;
parameter adr_size = 16;
parameter adr_size = 26;
parameter adr_lo = 2;
parameter mem_size = 1<<16;
parameter dat_size = 32;
parameter memory_init = 1;
parameter memory_file = "vl_ram.vmem";
670,8 → 669,8
`BASE`MODULE # (
.data_width(dat_size),
.addr_width(adr_size),
.memory_init(memory_init),
.memory_file(memory_file))
.memory_init(1),
.memory_file("memory_file"))
ram0(
`undef MODULE
.d(wbs_dat_i),
/rtl/verilog/versatile_library_altera.v
1230,7 → 1230,6
module vl_ram_be ( d, adr, be, we, q, clk);
parameter data_width = 32;
parameter addr_width = 8;
parameter mem_size = 256;
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input [(addr_width/4)-1:0] be;
1238,9 → 1237,9
output reg [(data_width-1):0] q;
input clk;
`ifdef SYSTEMVERILOG
logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
logic [data_width/8-1:0][7:0] ram[0:1<<(addr_width-2)-1];// # words = 1 << address width
`else
reg [data_width-1:0] ram [mem_size-1:0];
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
`endif
parameter memory_init = 0;
parameter memory_file = "vl_ram.vmem";
2159,9 → 2158,8
wb_dat_o, wb_ack_o, wb_clk, wb_rst);
parameter nr_of_ports = 3;
parameter wb_arbiter_type = 1;
parameter adr_size = 16;
parameter adr_size = 26;
parameter adr_lo = 2;
parameter mem_size = 1<<16;
parameter dat_size = 32;
parameter memory_init = 1;
parameter memory_file = "vl_ram.vmem";
2237,8 → 2235,8
vl_ram_be # (
.data_width(dat_size),
.addr_width(adr_size),
.memory_init(memory_init),
.memory_file(memory_file))
.memory_init(1),
.memory_file("memory_file"))
ram0(
.d(wbs_dat_i),
.adr(wbs_adr_i[adr_size-1:2]),
/rtl/verilog/memories.v
105,7 → 105,6
 
parameter data_width = 32;
parameter addr_width = 8;
parameter mem_size = 256;
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input [(addr_width/4)-1:0] be;
114,9 → 113,9
input clk;
 
//E2_ifdef SYSTEMVERILOG
logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
logic [data_width/8-1:0][7:0] ram[0:1<<(addr_width-2)-1];// # words = 1 << address width
//E2_else
reg [data_width-1:0] ram [mem_size-1:0];
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
//E2_endif
 
parameter memory_init = 0;

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